[AArch64] enable (v)select to math TLI hook (WIP)

[spatel]

Summary

I added more select-to-shift folds to DAGCombiner in:
rL374397
rL374555
...and noticed that AArch64 does not override a TLI hook that was added with:
rL296977

Not sure if that is intentional or oversight, so I flipped the setting completely and updated some auto-generated regression tests. It's not a universal win, but likely worth doing? If so, there are a few more regression tests that need updating/inspection.

I don't intend to do more with this patch, so feel free to commandeer/close.

[dmgreen]

I think I tried turning this on once upon a time, but the (very limited set of) results left me saying "meh". That was probably just codesize I was looking at at the time though.

@sanwou01 do you have times to give this a proper test? See if it helps or hurts on something bigger?

Edit: Oh, I see you are already looking!

[sanwou01]

I'm running SPEC CPU intrate for this patch as well as this patch in combination with D78880.

[greened]

In D68911#2024813, @sanwou01 wrote:

I'm running SPEC CPU intrate for this patch as well as this patch in combination with D78880.

What was the result of this experiment?

llvm/lib/Target/AArch64/AArch64ISelLowering.h

bool hasAndNot(SDValue Y) const override {
     EVT VT = Y.getValueType();
 
     if (!VT.isVector())
       return hasAndNotCompare(Y);
 
     return VT.getSizeInBits() >= 64; // vector 'bic'
   }
 
+  bool convertSelectOfConstantsToMath(EVT VT) const override {
+    return true;
+  }
+
   bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
       SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
       unsigned OldShiftOpcode, unsigned NewShiftOpcode,
       SelectionDAG &DAG) const override;
 
   bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
 
   bool shouldTransformSignedTruncationCheck(EVT XVT,

llvm/test/CodeGen/AArch64/select_const.ll

; CHECK-NEXT:    ret
   ret i32 %sel
 }
 
 ; select Cond, C+1, C --> add (zext Cond), C
 
 define i32 @select_Cplus1_C(i1 %cond) {
 ; CHECK-LABEL: select_Cplus1_C:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, ne
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    add w0, w8, #41 // =41
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
 ; CHECK-LABEL: select_Cplus1_C_zeroext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, ne
+; CHECK-NEXT:    add w0, w0, #41 // =41
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 define i32 @select_Cplus1_C_signext(i1 signext %cond) {
 ; CHECK-LABEL: select_Cplus1_C_signext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, ne
+; CHECK-NEXT:    sub w0, w8, w0
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 42, i32 41
   ret i32 %sel
 }
 
 ; select Cond, C, C+1 --> add (sext Cond), C
 
 define i32 @select_C_Cplus1(i1 %cond) {
 ; CHECK-LABEL: select_C_Cplus1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, eq
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    mov w9, #42
+; CHECK-NEXT:    sub w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
 ; CHECK-LABEL: select_C_Cplus1_zeroext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, eq
+; CHECK-NEXT:    mov w8, #42
+; CHECK-NEXT:    sub w0, w8, w0
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C_Cplus1_signext(i1 signext %cond) {
 ; CHECK-LABEL: select_C_Cplus1_signext:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, eq
+; CHECK-NEXT:    add w0, w0, #42 // =42
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i32 41, i32 42
   ret i32 %sel
 }
 
 ; In general, select of 2 constants could be:
 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 121, i8 23
   %bo = srem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_urem_constant(i1 %cond) {
 ; CHECK-LABEL: sel_constants_urem_constant:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #2
-; CHECK-NEXT:    cinc w0, w8, eq
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    mov w9, #3
+; CHECK-NEXT:    sub w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @urem_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: urem_constant_sel_constants:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    mov w8, #5
 ; CHECK-NEXT:    mov w9, #120
 ; CHECK-NEXT:    csel w0, w9, w8, ne
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = urem i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_and_constant(i1 %cond) {
 ; CHECK-LABEL: sel_constants_and_constant:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #4
-; CHECK-NEXT:    cinc w0, w8, eq
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    mov w9, #5
+; CHECK-NEXT:    sub w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = and i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; CHECK-LABEL: sel_constants_or_constant:
; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = shl i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @shl_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: shl_constant_sel_constants:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #2
-; CHECK-NEXT:    cinc x8, x8, eq
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    and x8, x0, #0x1
+; CHECK-NEXT:    mov w9, #3
+; CHECK-NEXT:    sub x8, x9, x8
 ; CHECK-NEXT:    mov w9, #1
 ; CHECK-NEXT:    lsl w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = shl i8 1, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; CHECK-LABEL: sel_constants_lshr_constant:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    tst w0, #0x1
 ; CHECK-NEXT:    mov w8, #7
 ; CHECK-NEXT:    csel w0, w8, wzr, ne
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = lshr i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @lshr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: lshr_constant_sel_constants:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #2
-; CHECK-NEXT:    cinc x8, x8, eq
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    and x8, x0, #0x1
+; CHECK-NEXT:    mov w9, #3
+; CHECK-NEXT:    sub x8, x9, x8
 ; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    lsr w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = lshr i8 64, %sel
   ret i8 %bo
 }
 
 
 define i8 @sel_constants_ashr_constant(i1 %cond) {
 ; CHECK-LABEL: sel_constants_ashr_constant:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sbfx w0, w0, #0, #1
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = ashr i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @ashr_constant_sel_constants(i1 %cond) {
 ; CHECK-LABEL: ashr_constant_sel_constants:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #2
-; CHECK-NEXT:    cinc x8, x8, eq
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    and x8, x0, #0x1
+; CHECK-NEXT:    mov w9, #3
+; CHECK-NEXT:    sub x8, x9, x8
 ; CHECK-NEXT:    mov w9, #-128
 ; CHECK-NEXT:    asr w0, w9, w8
 ; CHECK-NEXT:    ret
   %sel = select i1 %cond, i8 2, i8 3
   %bo = ashr i8 128, %sel
   ret i8 %bo
 }
 

llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

; CHECK-NEXT:    ret
   ret i32 %retval
 }
 
 ; Compare if positive and select of constants where one constant is zero and the other is a single bit.
 
 define i32 @pos_sel_special_constant(i32 %a) {
 ; CHECK-LABEL: pos_sel_special_constant:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #512
-; CHECK-NEXT:    bic w0, w8, w0, lsr #22
+; CHECK-NEXT:    mvn w8, w0
+; CHECK-NEXT:    lsr w8, w8, #22
+; CHECK-NEXT:    and w0, w8, #0x200
 ; CHECK-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select variable or zero.
 

 ; CHECK-NEXT:    ret
   %shl = select i1 %t, i8 128, i8 0
   ret i8 %shl
 }
 
 define i16 @sel_shift_bool_i16(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #128
-; CHECK-NEXT:    csel w0, w8, wzr, ne
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    lsl w0, w8, #7
 ; CHECK-NEXT:    ret
   %shl = select i1 %t, i16 128, i16 0
   ret i16 %shl
 }
 
 define i32 @sel_shift_bool_i32(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #64
-; CHECK-NEXT:    csel w0, w8, wzr, ne
+; CHECK-NEXT:    and w8, w0, #0x1
+; CHECK-NEXT:    lsl w0, w8, #6
 ; CHECK-NEXT:    ret
   %shl = select i1 %t, i32 64, i32 0
   ret i32 %shl
 }
 
 define i64 @sel_shift_bool_i64(i1 %t) {
 ; CHECK-LABEL: sel_shift_bool_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    tst w0, #0x1
-; CHECK-NEXT:    mov w8, #65536
-; CHECK-NEXT:    csel x0, x8, xzr, ne
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    and x8, x0, #0x1
+; CHECK-NEXT:    lsl x0, x8, #16
 ; CHECK-NEXT:    ret
   %shl = select i1 %t, i64 65536, i64 0
   ret i64 %shl
 }
 
 define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
 ; CHECK-LABEL: sel_shift_bool_v16i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    shl v0.16b, v0.16b, #7
-; CHECK-NEXT:    sshr v0.16b, v0.16b, #7
-; CHECK-NEXT:    movi v1.16b, #128
+; CHECK-NEXT:    movi v1.16b, #1
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    shl v0.16b, v0.16b, #7
 ; CHECK-NEXT:    ret
   %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer
   ret <16 x i8> %shl
 }
 
 define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {
 ; CHECK-LABEL: sel_shift_bool_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:    shl v0.8h, v0.8h, #15
-; CHECK-NEXT:    sshr v0.8h, v0.8h, #15
-; CHECK-NEXT:    movi v1.8h, #128
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    movi v1.8b, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #7
 ; CHECK-NEXT:    ret
   %shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer
   ret <8 x i16> %shl
 }
 
 define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {
 ; CHECK-LABEL: sel_shift_bool_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
-; CHECK-NEXT:    movi v1.4s, #64
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    movi v1.4h, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #6
 ; CHECK-NEXT:    ret
   %shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer
   ret <4 x i32> %shl
 }
 
 define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {
 ; CHECK-LABEL: sel_shift_bool_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
-; CHECK-NEXT:    mov w8, #65536
-; CHECK-NEXT:    shl v0.2d, v0.2d, #63
-; CHECK-NEXT:    sshr v0.2d, v0.2d, #63
-; CHECK-NEXT:    dup v1.2d, x8
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    movi v1.2s, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #16
 ; CHECK-NEXT:    ret
   %shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer
   ret <2 x i64> %shl
 }

llvm/test/CodeGen/AArch64/signbit-shift.ll

; CHECK-NEXT:    ret
   %e = zext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, ge
+; CHECK-NEXT:    asr w8, w0, #31
+; CHECK-NEXT:    add w0, w8, #42 // =42
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
; CHECK-NEXT:    ret
   %e = sext <4 x i1> %c to <4 x i32>
   %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
   ret <4 x i32> %r
 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, lt
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    add w0, w8, #41 // =41
 ; CHECK-NEXT:    ret
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 ; If negative...
 
; CHECK-NEXT:    ret
   %e = zext i1 %c to i32
   %r = add i32 %e, 41
   ret i32 %r
 }
 
 define i32 @sel_ifneg_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_tval_bigger:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, lt
+; CHECK-NEXT:    lsr w8, w0, #31
+; CHECK-NEXT:    add w0, w8, #41 // =41
 ; CHECK-NEXT:    ret
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifneg(i32 %x) {
 ; CHECK-LABEL: sext_ifneg:
; CHECK-NEXT:    ret
   %e = sext i1 %c to i32
   %r = add i32 %e, 42
   ret i32 %r
 }
 
 define i32 @sel_ifneg_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_fval_bigger:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmp w0, #0 // =0
-; CHECK-NEXT:    mov w8, #41
-; CHECK-NEXT:    cinc w0, w8, ge
+; CHECK-NEXT:    asr w8, w0, #31
+; CHECK-NEXT:    add w0, w8, #42 // =42
 ; CHECK-NEXT:    ret
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 define i32 @add_lshr_not(i32 %x) {
 ; CHECK-LABEL: add_lshr_not:

llvm/test/CodeGen/AArch64/vselect-constants.ll

; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cplus1_or_C_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    adrp x9, .LCPI2_1
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
-; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI2_1]
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
-; CHECK-NEXT:    bsl v0.16b, v2.16b, v1.16b
+; CHECK-NEXT:    movi v2.4h, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT:    uaddw v0.4s, v1.4s, v0.4h
 ; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI3_0
-; CHECK-NEXT:    adrp x9, .LCPI3_1
 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI3_0]
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI3_1]
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    bsl v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    sub v0.4s, v2.4s, v0.4s
 ; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_Cminus1_or_C_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI4_0
-; CHECK-NEXT:    adrp x9, .LCPI4_1
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
-; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI4_1]
 ; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
 ; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
-; CHECK-NEXT:    bsl v0.16b, v2.16b, v1.16b
+; CHECK-NEXT:    ssra v1.4s, v0.4s, #31
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI5_0
-; CHECK-NEXT:    adrp x9, .LCPI5_1
 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    ldr q3, [x9, :lo12:.LCPI5_1]
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    bsl v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    add v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_minus1_or_0_vec:
; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_minus1_vec:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    cmge v0.4s, v0.4s, #0
+; CHECK-NEXT:    movi v1.4h, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    movi v1.2d, #0xffffffffffffffff
+; CHECK-NEXT:    uaddw v0.4s, v1.4s, v0.4h
 ; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_1_or_0_vec:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4h, #1
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    sshr v0.4s, v0.4s, #31
-; CHECK-NEXT:    movi v1.4s, #1
-; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_1_or_0_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    movi v1.4s, #1
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
 ; CHECK-LABEL: sel_0_or_1_vec:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.4h, #1
+; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    shl v0.4s, v0.4s, #31
-; CHECK-NEXT:    cmge v0.4s, v0.4s, #0
 ; CHECK-NEXT:    movi v1.4s, #1
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %add
 }
 
 define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: cmp_sel_0_or_1_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    mvn v0.16b, v0.16b
 ; CHECK-NEXT:    movi v1.4s, #1
-; CHECK-NEXT:    bic v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
   %cond = icmp eq <4 x i32> %x, %y
   %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   ret <4 x i32> %add
 }