Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -6023,7 +6023,7 @@
 
     return NewLd;
   }
-  if (NumElems == 4 && LastLoadedElt == 1 &&
+  if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
       DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
     SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
     SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
Index: test/CodeGen/X86/elts-from-loads-256.ll
===================================================================
--- test/CodeGen/X86/elts-from-loads-256.ll
+++ test/CodeGen/X86/elts-from-loads-256.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mcpu=corei7-avx < %s
+; EltsFromConsecutiveLoads has a code-path that should not kick-in for AVX-sized vectors
+; Make sure there is no crash
+target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-win32"
+
+; Function Attrs: nounwind
+define void @test() #0 {
+  %1 = load i64 addrspace(1)** undef, align 8
+  %2 = getelementptr inbounds i64 addrspace(1)* %1, i64 0
+  %3 = load i64 addrspace(1)* %2
+  %4 = insertelement <4 x i64> undef, i64 %3, i32 0
+  %5 = load i64 addrspace(1)** undef, align 8
+  %6 = getelementptr inbounds i64 addrspace(1)* %5, i64 1
+  %7 = load i64 addrspace(1)* %6
+  %8 = insertelement <4 x i64> %4, i64 %7, i32 1
+  %9 = shufflevector <4 x i64> %8, <4 x i64> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  store <4 x i64> %9, <4 x i64>* undef
+  ret void
+}
+
+attributes #0 = { nounwind }
\ No newline at end of file