diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -995,7 +995,7 @@
   //   (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
   //   (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
   SDValue N0 = N->getOperand(0);
-  MVT Ty = N0.getSimpleValueType();
+  EVT Ty = N0.getValueType();
   if (Ty.isScalarInteger() &&
       (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR)) {
     auto *C1 = dyn_cast<ConstantSDNode>(N0->getOperand(1));
diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll
--- a/llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -72,3 +72,22 @@
   %3 = ashr i32 %2, 16
   ret i32 %3
 }
+
+define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
+; RV32I-LABEL: add_non_machine_type:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a0, a0, 256
+; RV32I-NEXT:    slli a0, a0, 20
+; RV32I-NEXT:    srai a0, a0, 8
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add_non_machine_type:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 256
+; RV64I-NEXT:    slli a0, a0, 52
+; RV64I-NEXT:    srai a0, a0, 40
+; RV64I-NEXT:    ret
+  %1 = add i24 %a, 256
+  %2 = shl i24 %1, 12
+  ret i24 %2
+}