diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/AsmParser/BUILD.gn
@@ -0,0 +1,23 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("RISCVGenAsmMatcher") {
+  visibility = [ ":AsmParser" ]
+  args = [ "-gen-asm-matcher" ]
+  td_file = "../RISCV.td"
+}
+
+static_library("AsmParser") {
+  output_name = "LLVMRISCVAsmParser"
+  deps = [
+    ":RISCVGenAsmMatcher",
+    "//llvm/lib/MC",
+    "//llvm/lib/MC/MCParser",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/RISCV/MCTargetDesc",
+    "//llvm/lib/Target/RISCV/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "RISCVAsmParser.cpp",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -0,0 +1,86 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("RISCVGenCompressInstEmitter") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-compress-inst-emitter" ]
+  td_file = "RISCV.td"
+}
+
+tablegen("RISCVGenDAGISel") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-dag-isel" ]
+  td_file = "RISCV.td"
+}
+
+tablegen("RISCVGenMCPseudoLowering") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-pseudo-lowering" ]
+  td_file = "RISCV.td"
+}
+
+tablegen("RISCVGenSystemOperands") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-searchable-tables" ]
+  td_file = "RISCV.td"
+}
+
+group("tablegen") {
+  visibility = [
+    ":LLVMRISCVCodeGen",
+    "Utils",
+  ]
+  public_deps = [
+    ":RISCVGenCompressInstEmitter",
+    ":RISCVGenDAGISel",
+    ":RISCVGenMCPseudoLowering",
+    ":RISCVGenSystemOperands",
+  ]
+}
+
+static_library("LLVMRISCVCodeGen") {
+  deps = [
+    ":tablegen",
+    "MCTargetDesc",
+    "TargetInfo",
+    "//llvm/include/llvm/Config:llvm-config",
+    "//llvm/lib/CodeGen",
+    "//llvm/lib/CodeGen/AsmPrinter",
+    "//llvm/lib/CodeGen/SelectionDAG",
+    "//llvm/lib/IR",
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target",
+  ]
+  include_dirs = [ "." ]
+  sources = [
+    "RISCVAsmPrinter.cpp",
+    "RISCVExpandPseudoInsts.cpp",
+    "RISCVFrameLowering.cpp",
+    "RISCVInstrInfo.cpp",
+    "RISCVISelDAGToDAG.cpp",
+    "RISCVISelLowering.cpp",
+    "RISCVMCInstLower.cpp",
+    "RISCVMergeBaseOffset.cpp",
+    "RISCVRegisterInfo.cpp",
+    "RISCVSubtarget.cpp",
+    "RISCVTargetMachine.cpp",
+    "RISCVTargetObjectFile.cpp",
+  ]
+}
+
+# This is a bit different from most build files: Due to this group
+# having the directory's name, "//llvm/lib/Target/RISCV" will refer to this
+# target, which pulls in the code in this directory *and all subdirectories*.
+# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
+# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
+# different behavior.
+group("RISCV") {
+  deps = [
+    ":LLVMRISCVCodeGen",
+    "AsmParser",
+    "Disassembler",
+    "MCTargetDesc",
+    "TargetInfo",
+    "Utils",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Disassembler/BUILD.gn
@@ -0,0 +1,22 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("RISCVGenDisassemblerTables") {
+  visibility = [ ":Disassembler" ]
+  args = [ "-gen-disassembler" ]
+  td_file = "../RISCV.td"
+}
+
+static_library("Disassembler") {
+  output_name = "LLVMRISCVDisassembler"
+  deps = [
+    ":RISCVGenDisassemblerTables",
+    "//llvm/lib/MC/MCDisassembler",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/RISCV/MCTargetDesc",
+    "//llvm/lib/Target/RISCV/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "RISCVDisassembler.cpp",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn
@@ -0,0 +1,69 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+tablegen("RISCVGenAsmWriter") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-asm-writer" ]
+  td_file = "../RISCV.td"
+}
+
+tablegen("RISCVGenInstrInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-instr-info" ]
+  td_file = "../RISCV.td"
+}
+
+tablegen("RISCVGenMCCodeEmitter") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-emitter" ]
+  td_file = "../RISCV.td"
+}
+
+tablegen("RISCVGenRegisterInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-register-info" ]
+  td_file = "../RISCV.td"
+}
+
+tablegen("RISCVGenSubtargetInfo") {
+  visibility = [ ":tablegen" ]
+  args = [ "-gen-subtarget" ]
+  td_file = "../RISCV.td"
+}
+
+group("tablegen") {
+  visibility = [
+    ":MCTargetDesc",
+    "../Utils",
+  ]
+  public_deps = [
+    ":RISCVGenAsmWriter",
+    ":RISCVGenInstrInfo",
+    ":RISCVGenMCCodeEmitter",
+    ":RISCVGenRegisterInfo",
+    ":RISCVGenSubtargetInfo",
+  ]
+}
+
+static_library("MCTargetDesc") {
+  output_name = "LLVMRISCVDesc"
+  public_deps = [
+    ":tablegen",
+  ]
+  deps = [
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/RISCV/Utils",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "RISCVAsmBackend.cpp",
+    "RISCVELFObjectWriter.cpp",
+    "RISCVInstPrinter.cpp",
+    "RISCVMCAsmInfo.cpp",
+    "RISCVMCCodeEmitter.cpp",
+    "RISCVMCExpr.cpp",
+    "RISCVMCTargetDesc.cpp",
+    "RISCVTargetStreamer.cpp",
+    "RISCVELFStreamer.cpp",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/TargetInfo/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/TargetInfo/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/TargetInfo/BUILD.gn
@@ -0,0 +1,10 @@
+static_library("TargetInfo") {
+  output_name = "LLVMRISCVInfo"
+  deps = [
+    "//llvm/lib/Support",
+  ]
+  include_dirs = [ ".." ]
+  sources = [
+    "RISCVTargetInfo.cpp",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn
new file mode 100644
--- /dev/null
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn
@@ -0,0 +1,19 @@
+import("//llvm/utils/TableGen/tablegen.gni")
+
+static_library("Utils") {
+  output_name = "LLVMRISCVUtils"
+  public_deps = [
+    "//llvm/lib/Target/RISCV:tablegen",
+  ]
+  deps = [
+    "//llvm/lib/MC",
+    "//llvm/lib/Support",
+    "//llvm/lib/Target/RISCV/MCTargetDesc:tablegen",
+  ]
+
+  include_dirs = [ ".." ]
+  sources = [
+    "RISCVBaseInfo.cpp",
+    "RISCVMatInt.cpp",
+  ]
+}
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni b/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni
--- a/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni
@@ -26,6 +26,7 @@
     "Hexagon",
     "Lanai",
     "PowerPC",
+    "RISCV",
     "Sparc",
     "WebAssembly",
     "X86",
@@ -40,6 +41,7 @@
 llvm_build_Hexagon = false
 llvm_build_Lanai = false
 llvm_build_PowerPC = false
+llvm_build_RISCV = false
 llvm_build_Sparc = false
 llvm_build_WebAssembly = false
 llvm_build_X86 = false
@@ -56,6 +58,8 @@
     llvm_build_Lanai = true
   } else if (target == "PowerPC") {
     llvm_build_PowerPC = true
+  } else if (target == "RISCV") {
+    llvm_build_RISCV = true
   } else if (target == "Sparc") {
     llvm_build_Sparc = true
   } else if (target == "WebAssembly") {