Index: include/llvm/Support/AArch64TargetParser.h =================================================================== --- include/llvm/Support/AArch64TargetParser.h +++ include/llvm/Support/AArch64TargetParser.h @@ -49,6 +49,11 @@ AEK_SSBS = 1 << 20, AEK_SB = 1 << 21, AEK_PREDRES = 1 << 22, + AEK_SVE2 = 1 << 23, + AEK_SVE2AES = 1 << 24, + AEK_SVE2SM4 = 1 << 25, + AEK_SVE2SHA3 = 1 << 26, + AEK_BITPERM = 1 << 27, }; enum class ArchKind { Index: include/llvm/Support/AArch64TargetParser.def =================================================================== --- include/llvm/Support/AArch64TargetParser.def +++ include/llvm/Support/AArch64TargetParser.def @@ -50,30 +50,35 @@ #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #endif // FIXME: This would be nicer were it tablegen -AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr) -AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr) -AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc") -AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse") -AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm") -AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto") -AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4") -AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3") -AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2") -AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes") -AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod") -AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8") -AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon") -AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16") -AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml") -AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe") -AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras") -AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve") -AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc") -AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand") -AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") -AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") -AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb") -AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres") +AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr) +AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr) +AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc") +AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse") +AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm") +AARCH64_ARCH_EXT_NAME("crypto", AArch64::AEK_CRYPTO, "+crypto","-crypto") +AARCH64_ARCH_EXT_NAME("sm4", AArch64::AEK_SM4, "+sm4", "-sm4") +AARCH64_ARCH_EXT_NAME("sha3", AArch64::AEK_SHA3, "+sha3", "-sha3") +AARCH64_ARCH_EXT_NAME("sha2", AArch64::AEK_SHA2, "+sha2", "-sha2") +AARCH64_ARCH_EXT_NAME("aes", AArch64::AEK_AES, "+aes", "-aes") +AARCH64_ARCH_EXT_NAME("dotprod", AArch64::AEK_DOTPROD, "+dotprod","-dotprod") +AARCH64_ARCH_EXT_NAME("fp", AArch64::AEK_FP, "+fp-armv8", "-fp-armv8") +AARCH64_ARCH_EXT_NAME("simd", AArch64::AEK_SIMD, "+neon", "-neon") +AARCH64_ARCH_EXT_NAME("fp16", AArch64::AEK_FP16, "+fullfp16", "-fullfp16") +AARCH64_ARCH_EXT_NAME("fp16fml", AArch64::AEK_FP16FML, "+fp16fml", "-fp16fml") +AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe") +AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras") +AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve") +AARCH64_ARCH_EXT_NAME("sve2", AArch64::AEK_SVE2, "+sve2", "-sve2") +AARCH64_ARCH_EXT_NAME("sve2-aes", AArch64::AEK_SVE2AES, "+sve2-aes", "-sve2-aes") +AARCH64_ARCH_EXT_NAME("sve2-sm4", AArch64::AEK_SVE2SM4, "+sve2-sm4", "-sve2-sm4") +AARCH64_ARCH_EXT_NAME("sve2-sha3", AArch64::AEK_SVE2SHA3, "+sve2-sha3", "-sve2-sha3") +AARCH64_ARCH_EXT_NAME("bitperm", AArch64::AEK_BITPERM, "+bitperm", "-bitperm") +AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc") +AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand") +AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") +AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") +AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb") +AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME Index: include/llvm/Support/ARMTargetParser.h =================================================================== --- include/llvm/Support/ARMTargetParser.h +++ include/llvm/Support/ARMTargetParser.h @@ -45,6 +45,11 @@ AEK_AES = 1 << 16, AEK_FP16FML = 1 << 17, AEK_SB = 1 << 18, + AEK_SVE2 = 1 << 19, + AEK_SVE2AES = 1 << 20, + AEK_SVE2SM4 = 1 << 21, + AEK_SVE2SHA3 = 1 << 22, + AEK_BITPERM = 1 << 23, // Unsupported extensions. AEK_OS = 0x8000000, AEK_IWMMXT = 0x10000000, Index: lib/Support/AArch64TargetParser.cpp =================================================================== --- lib/Support/AArch64TargetParser.cpp +++ lib/Support/AArch64TargetParser.cpp @@ -88,6 +88,16 @@ Features.push_back("+rdm"); if (Extensions & AEK_SVE) Features.push_back("+sve"); + if (Extensions & AEK_SVE2) + Features.push_back("+sve2"); + if (Extensions & AEK_SVE2AES) + Features.push_back("+sve2-aes"); + if (Extensions & AEK_SVE2SM4) + Features.push_back("+sve2-sm4"); + if (Extensions & AEK_SVE2SHA3) + Features.push_back("+sve2-sha3"); + if (Extensions & AEK_BITPERM) + Features.push_back("+bitperm"); if (Extensions & AEK_RCPC) Features.push_back("+rcpc"); Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -103,6 +103,21 @@ def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", "Enable Scalable Vector Extension (SVE) instructions">; +def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", + "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; + +def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", + "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; + +def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", + "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; + +def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", + "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; + +def FeatureSVE2BitPerm : SubtargetFeature<"bitperm", "HasSVE2BitPerm", "true", + "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; + def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", "Has zero-cycle register moves">; def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -107,6 +107,16 @@ "fuse-aes">; def HasSVE : Predicate<"Subtarget->hasSVE()">, AssemblerPredicate<"FeatureSVE", "sve">; +def HasSVE2 : Predicate<"Subtarget->hasSVE2()">, + AssemblerPredicate<"FeatureSVE2", "sve2">; +def HasSVE2AES : Predicate<"Subtarget->hasSVE2AES()">, + AssemblerPredicate<"FeatureSVE2AES", "sve2-aes">; +def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">, + AssemblerPredicate<"FeatureSVE2SM4", "sve2-sm4">; +def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">, + AssemblerPredicate<"FeatureSVE2SHA3", "sve2-sha3">; +def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2()">, + AssemblerPredicate<"FeatureSVE2BitPerm", "bitperm">; def HasRCPC : Predicate<"Subtarget->hasRCPC()">, AssemblerPredicate<"FeatureRCPC", "rcpc">; def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, Index: lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64SVEInstrInfo.td +++ lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -875,10 +875,10 @@ defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; // Predicated shifts - defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; - defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; - defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; - defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; + defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0000, "asr">; + defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b0001, "lsr">; + defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0011, "lsl">; + defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b0100, "asrd">; defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; @@ -1021,3 +1021,406 @@ def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn", (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>; } + +let Predicates = [HasSVE2] in { + // SVE2 integer multiply-add (indexed) + defm MLA_ZZZI : sve_int_mla_by_indexed_elem<0b01, 0b0, "mla">; + defm MLS_ZZZI : sve_int_mla_by_indexed_elem<0b01, 0b1, "mls">; + + // SVE2 saturating multiply-add high (indexed) + defm SQRDMLAH_ZZZI : sve_int_mla_by_indexed_elem<0b10, 0b0, "sqrdmlah">; + defm SQRDMLSH_ZZZI : sve_int_mla_by_indexed_elem<0b10, 0b1, "sqrdmlsh">; + + // SVE2 saturating multiply-add high (vectors, unpredicated) + defm SQRDMLAH_ZZZ : sve_int_mla<0b0, "sqrdmlah">; + defm SQRDMLSH_ZZZ : sve_int_mla<0b1, "sqrdmlsh">; + + // SVE2 integer multiply (indexed) + defm MUL_ZZZI : sve_int_mul_by_indexed_elem<0b1110, "mul">; + + // SVE2 saturating multiply high (indexed) + defm SQDMULH_ZZZI : sve_int_mul_by_indexed_elem<0b1100, "sqdmulh">; + defm SQRDMULH_ZZZI : sve_int_mul_by_indexed_elem<0b1101, "sqrdmulh">; + + // SVE2 signed saturating doubling multiply high (unpredicated) + defm SQDMULH_ZZZ : sve_int_mul<0b100, "sqdmulh">; + defm SQRDMULH_ZZZ : sve_int_mul<0b101, "sqrdmulh">; + + // SVE2 integer multiply vectors (unpredicated) + defm MUL_ZZZ : sve_int_mul<0b000, "mul">; + defm SMULH_ZZZ : sve_int_mul<0b010, "smulh">; + defm UMULH_ZZZ : sve_int_mul<0b011, "umulh">; + def PMUL_ZZZ_B : sve_int_mul<0b00, 0b001, "pmul", ZPR8>; + + // SVE2 complex integer dot product (indexed) + defm CDOT_ZZZI : sve_cintx_dot_by_indexed_elem<"cdot">; + + // SVE2 complex integer dot product + defm CDOT_ZZZ : sve_cintx_dot<"cdot">; + + // SVE2 complex integer multiply-add (indexed) + defm CMLA_ZZZI : sve_cmla_by_indexed_elem<0b0, "cmla">; + // SVE2 complex saturating multiply-add (indexed) + defm SQRDCMLAH_ZZZI : sve_cmla_by_indexed_elem<0b1, "sqrdcmlah">; + + // SVE2 complex integer multiply-add + defm CMLA_ZZZ : sve_int_cmla<0b0, "cmla">; + defm SQRDCMLAH_ZZZ : sve_int_cmla<0b1, "sqrdcmlah">; + + // SVE2 integer multiply long (indexed) + defm SMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b000, "smullb">; + defm SMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b001, "smullt">; + defm UMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b010, "umullb">; + defm UMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b011, "umullt">; + + // SVE2 saturating multiply (indexed) + defm SQDMULLB_ZZZI : sve_int_mul_long_by_indexed_elem<0b100, "sqdmullb">; + defm SQDMULLT_ZZZI : sve_int_mul_long_by_indexed_elem<0b101, "sqdmullt">; + + // SVE2 integer multiply-add long (indexed) + defm SMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1000, "smlalb">; + defm SMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1001, "smlalt">; + defm UMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1010, "umlalb">; + defm UMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1011, "umlalt">; + defm SMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1100, "smlslb">; + defm SMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1101, "smlslt">; + defm UMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b1110, "umlslb">; + defm UMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b1111, "umlslt">; + + // SVE2 integer multiply-add long (vectors, unpredicated) + defm SMLALB_ZZZ : sve_int_mla_long<0b10000, "smlalb">; + defm SMLALT_ZZZ : sve_int_mla_long<0b10001, "smlalt">; + defm UMLALB_ZZZ : sve_int_mla_long<0b10010, "umlalb">; + defm UMLALT_ZZZ : sve_int_mla_long<0b10011, "umlalt">; + defm SMLSLB_ZZZ : sve_int_mla_long<0b10100, "smlslb">; + defm SMLSLT_ZZZ : sve_int_mla_long<0b10101, "smlslt">; + defm UMLSLB_ZZZ : sve_int_mla_long<0b10110, "umlslb">; + defm UMLSLT_ZZZ : sve_int_mla_long<0b10111, "umlslt">; + + // SVE2 saturating multiply-add (indexed) + defm SQDMLALB_ZZZI : sve_int_mla_long_by_indexed_elem<0b0100, "sqdmlalb">; + defm SQDMLALT_ZZZI : sve_int_mla_long_by_indexed_elem<0b0101, "sqdmlalt">; + defm SQDMLSLB_ZZZI : sve_int_mla_long_by_indexed_elem<0b0110, "sqdmlslb">; + defm SQDMLSLT_ZZZI : sve_int_mla_long_by_indexed_elem<0b0111, "sqdmlslt">; + + // SVE2 saturating multiply-add (vectors, unpredicated) + defm SQDMLALB_ZZZ : sve_int_mla_long<0b11000, "sqdmlalb">; + defm SQDMLALT_ZZZ : sve_int_mla_long<0b11001, "sqdmlalt">; + defm SQDMLSLB_ZZZ : sve_int_mla_long<0b11010, "sqdmlslb">; + defm SQDMLSLT_ZZZ : sve_int_mla_long<0b11011, "sqdmlslt">; + + // SVE2 saturating multiply-add interleaved long + defm SQDMLALBT_ZZZ : sve_int_mla_long<0b00010, "sqdmlalbt">; + defm SQDMLSLBT_ZZZ : sve_int_mla_long<0b00011, "sqdmlslbt">; + + // SVE2 integer halving add/subtract (predicated) + defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd">; + defm UHADD_ZPmZ : sve2_int_arith_pred<0b100010, "uhadd">; + defm SHSUB_ZPmZ : sve2_int_arith_pred<0b100100, "shsub">; + defm UHSUB_ZPmZ : sve2_int_arith_pred<0b100110, "uhsub">; + defm SRHADD_ZPmZ : sve2_int_arith_pred<0b101000, "srhadd">; + defm URHADD_ZPmZ : sve2_int_arith_pred<0b101010, "urhadd">; + defm SHSUBR_ZPmZ : sve2_int_arith_pred<0b101100, "shsubr">; + defm UHSUBR_ZPmZ : sve2_int_arith_pred<0b101110, "uhsubr">; + + // SVE2 integer pairwise add and accumulate long + defm SADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<0, "sadalp">; + defm UADALP_ZPmZ : sve2_int_sadd_long_accum_pairwise<1, "uadalp">; + + // SVE2 integer pairwise arithmetic + defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">; + defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">; + defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">; + defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">; + defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">; + + // SVE2 integer unary operations (predicated) + defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe">; + defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte">; + defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs">; + defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg">; + + // SVE2 saturating add/subtract + defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd">; + defm UQADD_ZPmZ : sve2_int_arith_pred<0b110010, "uqadd">; + defm SQSUB_ZPmZ : sve2_int_arith_pred<0b110100, "sqsub">; + defm UQSUB_ZPmZ : sve2_int_arith_pred<0b110110, "uqsub">; + defm SUQADD_ZPmZ : sve2_int_arith_pred<0b111000, "suqadd">; + defm USQADD_ZPmZ : sve2_int_arith_pred<0b111010, "usqadd">; + defm SQSUBR_ZPmZ : sve2_int_arith_pred<0b111100, "sqsubr">; + defm UQSUBR_ZPmZ : sve2_int_arith_pred<0b111110, "uqsubr">; + + // SVE2 saturating/rounding bitwise shift left (predicated) + defm SRSHL_ZPmZ : sve2_int_arith_pred<0b000100, "srshl">; + defm URSHL_ZPmZ : sve2_int_arith_pred<0b000110, "urshl">; + defm SRSHLR_ZPmZ : sve2_int_arith_pred<0b001100, "srshlr">; + defm URSHLR_ZPmZ : sve2_int_arith_pred<0b001110, "urshlr">; + defm SQSHL_ZPmZ : sve2_int_arith_pred<0b010000, "sqshl">; + defm UQSHL_ZPmZ : sve2_int_arith_pred<0b010010, "uqshl">; + defm SQRSHL_ZPmZ : sve2_int_arith_pred<0b010100, "sqrshl">; + defm UQRSHL_ZPmZ : sve2_int_arith_pred<0b010110, "uqrshl">; + defm SQSHLR_ZPmZ : sve2_int_arith_pred<0b011000, "sqshlr">; + defm UQSHLR_ZPmZ : sve2_int_arith_pred<0b011010, "uqshlr">; + defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">; + defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">; + + // SVE2 integer add/subtract long + defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb">; + defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt">; + defm UADDLB_ZZZ : sve2_wide_int_arith_long<0b00010, "uaddlb">; + defm UADDLT_ZZZ : sve2_wide_int_arith_long<0b00011, "uaddlt">; + defm SSUBLB_ZZZ : sve2_wide_int_arith_long<0b00100, "ssublb">; + defm SSUBLT_ZZZ : sve2_wide_int_arith_long<0b00101, "ssublt">; + defm USUBLB_ZZZ : sve2_wide_int_arith_long<0b00110, "usublb">; + defm USUBLT_ZZZ : sve2_wide_int_arith_long<0b00111, "usublt">; + defm SABDLB_ZZZ : sve2_wide_int_arith_long<0b01100, "sabdlb">; + defm SABDLT_ZZZ : sve2_wide_int_arith_long<0b01101, "sabdlt">; + defm UABDLB_ZZZ : sve2_wide_int_arith_long<0b01110, "uabdlb">; + defm UABDLT_ZZZ : sve2_wide_int_arith_long<0b01111, "uabdlt">; + + // SVE2 integer add/subtract wide + defm SADDWB_ZZZ : sve2_wide_int_arith_wide<0b000, "saddwb">; + defm SADDWT_ZZZ : sve2_wide_int_arith_wide<0b001, "saddwt">; + defm UADDWB_ZZZ : sve2_wide_int_arith_wide<0b010, "uaddwb">; + defm UADDWT_ZZZ : sve2_wide_int_arith_wide<0b011, "uaddwt">; + defm SSUBWB_ZZZ : sve2_wide_int_arith_wide<0b100, "ssubwb">; + defm SSUBWT_ZZZ : sve2_wide_int_arith_wide<0b101, "ssubwt">; + defm USUBWB_ZZZ : sve2_wide_int_arith_wide<0b110, "usubwb">; + defm USUBWT_ZZZ : sve2_wide_int_arith_wide<0b111, "usubwt">; + + // SVE2 integer multiply long + defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; + defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; + defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">; + defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">; + defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">; + defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">; + defm PMULLB_ZZZ : sve2_pmul_long<0b0, "pmullb">; + defm PMULLT_ZZZ : sve2_pmul_long<0b1, "pmullt">; + + // SVE2 bitwise shift and insert + defm SRI_ZZI : sve2_int_bin_cons_shift_imm_right<0b0, "sri">; + defm SLI_ZZI : sve2_int_bin_cons_shift_imm_left< 0b1, "sli">; + + // SVE2 bitwise shift right and accumulate + defm SSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b00, "ssra">; + defm USRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b01, "usra">; + defm SRSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b10, "srsra">; + defm URSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b11, "ursra">; + + // SVE2 complex integer add + defm CADD_ZZI : sve2_int_cadd<0b0, "cadd">; + defm SQCADD_ZZI : sve2_int_cadd<0b1, "sqcadd">; + + // SVE2 integer absolute difference and accumulate + defm SABA_ZZZ : sve2_int_absdiff_accum<0b0, "saba">; + defm UABA_ZZZ : sve2_int_absdiff_accum<0b1, "uaba">; + + // SVE2 integer absolute difference and accumulate long + defm SABALB_ZZZ : sve2_int_absdiff_accum_long<0b00, "sabalb">; + defm SABALT_ZZZ : sve2_int_absdiff_accum_long<0b01, "sabalt">; + defm UABALB_ZZZ : sve2_int_absdiff_accum_long<0b10, "uabalb">; + defm UABALT_ZZZ : sve2_int_absdiff_accum_long<0b11, "uabalt">; + + // SVE2 integer add/subtract long with carry + defm ADCLB_ZZZ : sve2_int_addsub_long_carry<0b00, "adclb">; + defm ADCLT_ZZZ : sve2_int_addsub_long_carry<0b01, "adclt">; + defm SBCLB_ZZZ : sve2_int_addsub_long_carry<0b10, "sbclb">; + defm SBCLT_ZZZ : sve2_int_addsub_long_carry<0b11, "sbclt">; + + // SVE2 bitwise shift right narrow + defm SQSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0000, "sqshrunb">; + defm SQSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0001, "sqshrunt">; + defm SQRSHRUNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0010, "sqrshrunb">; + defm SQRSHRUNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0011, "sqrshrunt">; + defm SHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0100, "shrnb">; + defm SHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0101, "shrnt">; + defm RSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0110, "rshrnb">; + defm RSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b0111, "rshrnt">; + defm SQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1000, "sqshrnb">; + defm SQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1001, "sqshrnt">; + defm SQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1010, "sqrshrnb">; + defm SQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1011, "sqrshrnt">; + defm UQSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1100, "uqshrnb">; + defm UQSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1101, "uqshrnt">; + defm UQRSHRNB_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1110, "uqrshrnb">; + defm UQRSHRNT_ZZI : sve2_int_bin_cons_shift_imm_right_narrow<0b1111, "uqrshrnt">; + + // SVE2 integer add/subtract narrow high part + defm ADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b000, "addhnb">; + defm ADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b001, "addhnt">; + defm RADDHNB_ZZZ : sve2_int_addsub_narrow_high<0b010, "raddhnb">; + defm RADDHNT_ZZZ : sve2_int_addsub_narrow_high<0b011, "raddhnt">; + defm SUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b100, "subhnb">; + defm SUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b101, "subhnt">; + defm RSUBHNB_ZZZ : sve2_int_addsub_narrow_high<0b110, "rsubhnb">; + defm RSUBHNT_ZZZ : sve2_int_addsub_narrow_high<0b111, "rsubhnt">; + + // SVE2 saturating extract narrow + defm SQXTNB_ZZ : sve2_int_sat_extract_narrow<0b000, "sqxtnb">; + defm SQXTNT_ZZ : sve2_int_sat_extract_narrow<0b001, "sqxtnt">; + defm UQXTNB_ZZ : sve2_int_sat_extract_narrow<0b010, "uqxtnb">; + defm UQXTNT_ZZ : sve2_int_sat_extract_narrow<0b011, "uqxtnt">; + defm SQXTUNB_ZZ : sve2_int_sat_extract_narrow<0b100, "sqxtunb">; + defm SQXTUNT_ZZ : sve2_int_sat_extract_narrow<0b101, "sqxtunt">; + + // SVE2 character match + defm MATCH_PPzZZ : sve2_char_match<0b0, "match">; + defm NMATCH_PPzZZ : sve2_char_match<0b1, "nmatch">; + + // SVE2 bitwise exclusive-or interleaved + defm EORBT_ZZZ : sve2_bitwise_xor_interleaved<0b0, "eorbt">; + defm EORTB_ZZZ : sve2_bitwise_xor_interleaved<0b1, "eortb">; + + // SVE2 bitwise shift left long + defm SSHLLB_ZZI : sve2_bitwise_shift_left_long<0b00, "sshllb">; + defm SSHLLT_ZZI : sve2_bitwise_shift_left_long<0b01, "sshllt">; + defm USHLLB_ZZI : sve2_bitwise_shift_left_long<0b10, "ushllb">; + defm USHLLT_ZZI : sve2_bitwise_shift_left_long<0b11, "ushllt">; + + // SVE2 integer add/subtract interleaved long + defm SADDLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b00, "saddlbt">; + defm SSUBLBT_ZZZ : sve2_misc_int_addsub_long_interleaved<0b10, "ssublbt">; + defm SSUBLTB_ZZZ : sve2_misc_int_addsub_long_interleaved<0b11, "ssubltb">; + + // SVE2 histogram generation (segment) + def HISTSEG_ZZZ : sve2_hist_gen_segment<"histseg">; + + // SVE2 histogram generation (vector) + defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">; + + // SVE2 floating-point convert precision + defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">; + defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">; + defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">; + + // SVE2 floating-point pairwise operations + defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">; + defm FMAXNMP_ZPmZZ : sve2_fp_pairwise_pred<0b100, "fmaxnmp">; + defm FMINNMP_ZPmZZ : sve2_fp_pairwise_pred<0b101, "fminnmp">; + defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">; + defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">; + + // SVE2 floating-point multiply-add long (indexed) + def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">; + def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">; + def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">; + def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">; + + // SVE2 floating-point multiply-add long + def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">; + def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">; + def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">; + def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">; + + // SVE2 bitwise ternary operations + defm EOR3_ZZZZ_D : sve2_int_bitwise_ternary_op<0b000, "eor3">; + defm BCAX_ZZZZ_D : sve2_int_bitwise_ternary_op<0b010, "bcax">; + def BSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b001, "bsl">; + def BSL1N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b011, "bsl1n">; + def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">; + def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">; + + // sve_int_rotate_imm + defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">; + + // SVE2 extract vector (immediate offset, constructive) + def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">; + + // SVE floating-point convert precision + def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>; + + // SVE floating-point convert to integer + defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">; + + // Non-temporal contiguous loads (vector + register) + defm LDNT1SB_ZZR_S : sve2_mem_cldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>; + defm LDNT1B_ZZR_S : sve2_mem_cldnt_vs<0b00001, "ldnt1b", Z_s, ZPR32>; + defm LDNT1SH_ZZR_S : sve2_mem_cldnt_vs<0b00100, "ldnt1sh", Z_s, ZPR32>; + defm LDNT1H_ZZR_S : sve2_mem_cldnt_vs<0b00101, "ldnt1h", Z_s, ZPR32>; + defm LDNT1W_ZZR_S : sve2_mem_cldnt_vs<0b01001, "ldnt1w", Z_s, ZPR32>; + + defm LDNT1SB_ZZR_D : sve2_mem_cldnt_vs<0b10000, "ldnt1sb", Z_d, ZPR64>; + defm LDNT1B_ZZR_D : sve2_mem_cldnt_vs<0b10010, "ldnt1b", Z_d, ZPR64>; + defm LDNT1SH_ZZR_D : sve2_mem_cldnt_vs<0b10100, "ldnt1sh", Z_d, ZPR64>; + defm LDNT1H_ZZR_D : sve2_mem_cldnt_vs<0b10110, "ldnt1h", Z_d, ZPR64>; + defm LDNT1SW_ZZR_D : sve2_mem_cldnt_vs<0b11000, "ldnt1sw", Z_d, ZPR64>; + defm LDNT1W_ZZR_D : sve2_mem_cldnt_vs<0b11010, "ldnt1w", Z_d, ZPR64>; + defm LDNT1D_ZZR_D : sve2_mem_cldnt_vs<0b11110, "ldnt1d", Z_d, ZPR64>; + + // SVE2 vector splice (constructive) + defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">; + + // Predicated shifts + defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; + defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; + defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; + defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; + defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; + + // Non-temporal contiguous stores (vector + register) + defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>; + defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>; + defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>; + + defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>; + defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>; + defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>; + defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>; + + // SVE table lookup (three sources) + defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">; + defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">; + + // SVE integer compare scalar count and limit + defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">; + defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">; + defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">; + defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi">; + + defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege">; + defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt">; + defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">; + defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">; + + // SVE pointer conflict compare + defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">; + defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">; +} + +let Predicates = [HasSVE2AES] in { + // SVE2 crypto destructive binary operations + def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>; + def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>; + + // SVE2 crypto unary operations + def AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc">; + def AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc">; + + // PMULLB and PMULLT instructions which operate with 64-bit source and + // 128-bit destination elements are enabled with crypto extensions, similar + // to NEON PMULL2 instruction. + def PMULLB_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11010, "pmullb", + ZPR128, ZPR64, ZPR64>; + def PMULLT_ZZZ_Q : sve2_wide_int_arith<0b00, 0b11011, "pmullt", + ZPR128, ZPR64, ZPR64>; +} + +let Predicates = [HasSVE2SM4] in { + // SVE2 crypto constructive binary operations + def SM4EKEY_ZZZ_S : sve2_crypto_cons_bin_op<0b0, "sm4ekey", ZPR32>; + // SVE2 crypto destructive binary operations + def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32>; +} + +let Predicates = [HasSVE2SHA3] in { + // SVE2 crypto constructive binary operations + def RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64>; +} + +let Predicates = [HasSVE2BitPerm] in { + // SVE2 bitwise permute + defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext">; + defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep">; + defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp">; +} Index: lib/Target/AArch64/AArch64SchedA53.td =================================================================== --- lib/Target/AArch64/AArch64SchedA53.td +++ lib/Target/AArch64/AArch64SchedA53.td @@ -26,7 +26,9 @@ // v 1.0 Spreadsheet let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } Index: lib/Target/AArch64/AArch64SchedA57.td =================================================================== --- lib/Target/AArch64/AArch64SchedA57.td +++ lib/Target/AArch64/AArch64SchedA57.td @@ -31,7 +31,9 @@ let LoopMicroOpBufferSize = 16; let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64SchedCyclone.td =================================================================== --- lib/Target/AArch64/AArch64SchedCyclone.td +++ lib/Target/AArch64/AArch64SchedCyclone.td @@ -18,7 +18,9 @@ let MispredictPenalty = 16; // 14-19 cycles are typical. let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64SchedExynosM1.td =================================================================== --- lib/Target/AArch64/AArch64SchedExynosM1.td +++ lib/Target/AArch64/AArch64SchedExynosM1.td @@ -24,7 +24,9 @@ let MispredictPenalty = 14; // Minimum branch misprediction penalty. let CompleteModel = 1; // Use the default model otherwise. - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64SchedExynosM3.td =================================================================== --- lib/Target/AArch64/AArch64SchedExynosM3.td +++ lib/Target/AArch64/AArch64SchedExynosM3.td @@ -24,7 +24,9 @@ let MispredictPenalty = 16; // Minimum branch misprediction penalty. let CompleteModel = 1; // Use the default model otherwise. - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64SchedExynosM4.td =================================================================== --- lib/Target/AArch64/AArch64SchedExynosM4.td +++ lib/Target/AArch64/AArch64SchedExynosM4.td @@ -24,7 +24,9 @@ let MispredictPenalty = 16; // Minimum branch misprediction penalty. let CompleteModel = 1; // Use the default model otherwise. - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; } //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64SchedFalkor.td =================================================================== --- lib/Target/AArch64/AArch64SchedFalkor.td +++ lib/Target/AArch64/AArch64SchedFalkor.td @@ -23,7 +23,9 @@ let MispredictPenalty = 11; // Minimum branch misprediction penalty. let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; Index: lib/Target/AArch64/AArch64SchedKryo.td =================================================================== --- lib/Target/AArch64/AArch64SchedKryo.td +++ lib/Target/AArch64/AArch64SchedKryo.td @@ -27,7 +27,9 @@ let LoopMicroOpBufferSize = 16; let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; Index: lib/Target/AArch64/AArch64SchedThunderX.td =================================================================== --- lib/Target/AArch64/AArch64SchedThunderX.td +++ lib/Target/AArch64/AArch64SchedThunderX.td @@ -25,7 +25,9 @@ let PostRAScheduler = 1; // Use PostRA scheduler. let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; Index: lib/Target/AArch64/AArch64SchedThunderX2T99.td =================================================================== --- lib/Target/AArch64/AArch64SchedThunderX2T99.td +++ lib/Target/AArch64/AArch64SchedThunderX2T99.td @@ -25,7 +25,9 @@ let PostRAScheduler = 1; // Using PostRA sched. let CompleteModel = 1; - list UnsupportedFeatures = [HasSVE]; + list UnsupportedFeatures = [HasSVE, HasSVE2, HasSVE2AES, + HasSVE2SM4, HasSVE2SHA3, + HasSVE2BitPerm]; // FIXME: Remove when all errors have been fixed. let FullInstRWOverlapCheck = 0; Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -119,6 +119,7 @@ bool HasLSLFast = false; bool HasSVE = false; + bool HasSVE2 = false; bool HasRCPC = false; bool HasAggressiveFMA = false; @@ -134,6 +135,12 @@ bool HasRandGen = false; bool HasMTE = false; + // Arm SVE2 extensions + bool HasSVE2AES = true; + bool HasSVE2SM4 = true; + bool HasSVE2SHA3 = true; + bool HasSVE2BitPerm = true; + // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove = false; @@ -360,6 +367,7 @@ bool hasSPE() const { return HasSPE; } bool hasLSLFast() const { return HasLSLFast; } bool hasSVE() const { return HasSVE; } + bool hasSVE2() const { return HasSVE2; } bool hasRCPC() const { return HasRCPC; } bool hasAggressiveFMA() const { return HasAggressiveFMA; } bool hasAlternativeNZCV() const { return HasAlternativeNZCV; } @@ -372,6 +380,11 @@ bool hasBTI() const { return HasBTI; } bool hasRandGen() const { return HasRandGen; } bool hasMTE() const { return HasMTE; } + // Arm SVE2 extensions + bool hasSVE2AES() const { return HasSVE2AES; } + bool hasSVE2SM4() const { return HasSVE2SM4; } + bool hasSVE2SHA3() const { return HasSVE2SHA3; } + bool hasSVE2BitPerm() const { return HasSVE2BitPerm; } bool isLittleEndian() const { return IsLittle; } Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2831,6 +2831,11 @@ {"pan-rwv", {AArch64::FeaturePAN_RWV}}, {"ccpp", {AArch64::FeatureCCPP}}, {"sve", {AArch64::FeatureSVE}}, + {"sve2", {AArch64::FeatureSVE2}}, + {"sve2-aes", {AArch64::FeatureSVE2AES}}, + {"sve2-sm4", {AArch64::FeatureSVE2SM4}}, + {"sve2-sha3", {AArch64::FeatureSVE2SHA3}}, + {"bitperm", {AArch64::FeatureSVE2BitPerm}}, // FIXME: Unsupported extensions {"pan", {}}, {"lor", {}}, Index: lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- lib/Target/AArch64/SVEInstrFormats.td +++ lib/Target/AArch64/SVEInstrFormats.td @@ -700,8 +700,8 @@ (!cast(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>; } -class sve_int_perm_tbl sz8_64, string asm, ZPRRegOp zprty, - RegisterOperand VecList> +class sve_int_perm_tbl sz8_64, bits<2> opc, string asm, + ZPRRegOp zprty, RegisterOperand VecList> : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm), asm, "\t$Zd, $Zn, $Zm", "", @@ -713,16 +713,18 @@ let Inst{23-22} = sz8_64; let Inst{21} = 0b1; let Inst{20-16} = Zm; - let Inst{15-10} = 0b001100; + let Inst{15-13} = 0b001; + let Inst{12-11} = opc; + let Inst{10} = 0b0; let Inst{9-5} = Zn; let Inst{4-0} = Zd; } multiclass sve_int_perm_tbl { - def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>; - def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>; - def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>; - def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>; + def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>; + def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>; + def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>; + def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>; def : InstAlias(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>; @@ -734,6 +736,37 @@ (!cast(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>; } +multiclass sve2_int_perm_tbl { + def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>; + def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>; + def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>; + def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>; +} + +class sve2_int_perm_tbx sz8_64, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b001011; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_perm_tbx { + def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>; + def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>; + def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>; + def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>; +} + class sve_int_perm_reverse_z sz8_64, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$Zn), asm, "\t$Zd, $Zn", @@ -874,6 +907,21 @@ let ElementSize = ElementSizeNone; } +class sve2_int_perm_extract_i_cons +: I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8), + asm, "\t$Zd, $Zn, $imm8", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<8> imm8; + let Inst{31-21} = 0b00000101011; + let Inst{20-16} = imm8{7-3}; + let Inst{15-13} = 0b000; + let Inst{12-10} = imm8{2-0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + //===----------------------------------------------------------------------===// // SVE Vector Select Group //===----------------------------------------------------------------------===// @@ -1436,6 +1484,132 @@ } //===----------------------------------------------------------------------===// +// SVE2 Floating Point Convert Group +//===----------------------------------------------------------------------===// + +class sve2_fp_convert_precision opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn), + asm, "\t$Zd, $Pg/m, $Zn", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<3> Pg; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = opc{3-2}; + let Inst{21-18} = 0b0010; + let Inst{17-16} = opc{1-0}; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_fp_convert_down_narrow { + def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>; + def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>; +} + +multiclass sve2_fp_convert_up_long { + def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>; + def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>; +} + +multiclass sve2_fp_convert_down_odd_rounding { + def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Floating Point Pairwise Group +//===----------------------------------------------------------------------===// + +class sve2_fp_pairwise_pred sz, bits<3> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zm; + bits<5> Zdn; + let Inst{31-24} = 0b01100100; + let Inst{23-22} = sz; + let Inst{21-19} = 0b010; + let Inst{18-16} = opc; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = zprty.ElementSize; +} + +multiclass sve2_fp_pairwise_pred opc, string asm> { + def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>; + def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>; + def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Floating Point Widening Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +class sve2_fp_mla_long_by_indexed_elem opc, string asm> +: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, + VectorIndexH:$iop), + asm, "\t$Zda, $Zn, $Zm$iop", + "", + []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<3> Zm; + bits<3> iop; + let Inst{31-21} = 0b01100100101; + let Inst{20-19} = iop{2-1}; + let Inst{18-16} = Zm; + let Inst{15-14} = 0b01; + let Inst{13} = opc{1}; + let Inst{12} = 0b0; + let Inst{11} = iop{0}; + let Inst{10} = opc{0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +//===----------------------------------------------------------------------===// +// SVE2 Floating Point Widening Multiply-Add Group +//===----------------------------------------------------------------------===// + +class sve2_fp_mla_long opc, string asm> +: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm), + asm, "\t$Zda, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + let Inst{31-21} = 0b01100100101; + let Inst{20-16} = Zm; + let Inst{15-14} = 0b10; + let Inst{13} = opc{1}; + let Inst{12-11} = 0b00; + let Inst{10} = opc{0}; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +//===----------------------------------------------------------------------===// // SVE Stack Allocation Group //===----------------------------------------------------------------------===// @@ -1535,6 +1709,12 @@ def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>; } +multiclass sve2_fp_flogb { + def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>; + def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>; + def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>; +} + //===----------------------------------------------------------------------===// // SVE Floating Point Unary Operations - Unpredicated Group //===----------------------------------------------------------------------===// @@ -1623,7 +1803,7 @@ } //===----------------------------------------------------------------------===// -// SVE Integer Multiply-Add Group +// SVE Integer Multiply-Add - Vectors Group (Predicated) //===----------------------------------------------------------------------===// class sve_int_mladdsub_vvv_pred sz8_64, bits<1> opc, string asm, @@ -1691,6 +1871,113 @@ } //===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_mla sz, bits<5> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve_int_mla { + def _B : sve_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>; + def _H : sve_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>; + def _S : sve_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>; + def _D : sve_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>; +} + +multiclass sve_int_mla_long opc, string asm> { + def _H : sve_int_mla<0b01, opc, asm, ZPR16, ZPR8>; + def _S : sve_int_mla<0b10, opc, asm, ZPR32, ZPR16>; + def _D : sve_int_mla<0b11, opc, asm, ZPR64, ZPR32>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +class sve_int_mla_by_indexed_elem sz, bits<6> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + ZPRRegOp zprty3, Operand itype> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop), + asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve_int_mla_by_indexed_elem opc, bit S, string asm> { + def _H : sve_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{22} = iop{2}; + let Inst{20-19} = iop{1-0}; + let Inst{18-16} = Zm; + } + def _S : sve_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { + bits<4> Zm; + bit iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer Multiply-Add Long - Indexed Group +//===----------------------------------------------------------------------===// + +multiclass sve_int_mla_long_by_indexed_elem opc, string asm> { + def _S : sve_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, + asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{20-19} = iop{2-1}; + let Inst{18-16} = Zm; + let Inst{11} = iop{0}; + } + def _D : sve_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} }, + asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> { + bits<4> Zm; + bits<2> iop; + let Inst{20} = iop{1}; + let Inst{19-16} = Zm; + let Inst{11} = iop{0}; + } +} + + +//===----------------------------------------------------------------------===// // SVE Integer Dot Product Group //===----------------------------------------------------------------------===// @@ -1732,32 +2019,671 @@ "", []>, Sched<[]> { bits<5> Zda; bits<5> Zn; - let Inst{31-23} = 0b010001001; - let Inst{22} = sz; + let Inst{31-23} = 0b010001001; + let Inst{22} = sz; + let Inst{21} = 0b1; + let Inst{15-11} = 0; + let Inst{10} = U; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve_intx_dot_by_indexed_elem { + def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { + bits<2> iop; + bits<3> Zm; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { + bits<1> iop; + bits<4> Zm; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Complex Integer Dot Product Group +//===----------------------------------------------------------------------===// + +class sve2_complex_int_arith sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm, + complexrotateop:$rot), + asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + bits<2> rot; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15-12} = opc; + let Inst{11-10} = rot; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve_cintx_dot { + def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>; + def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Complex Multiply-Add Group +//===----------------------------------------------------------------------===// + +multiclass sve_int_cmla { + def _B : sve2_complex_int_arith<0b00, { 0b001, opc }, asm, ZPR8, ZPR8>; + def _H : sve2_complex_int_arith<0b01, { 0b001, opc }, asm, ZPR16, ZPR16>; + def _S : sve2_complex_int_arith<0b10, { 0b001, opc }, asm, ZPR32, ZPR32>; + def _D : sve2_complex_int_arith<0b11, { 0b001, opc }, asm, ZPR64, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Complex Integer Dot Product - Indexed Group +//===----------------------------------------------------------------------===// + +class sve2_complex_int_arith_indexed sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + ZPRRegOp zprty3, Operand itype> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop, + complexrotateop:$rot), + asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<2> rot; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-12} = opc; + let Inst{11-10} = rot; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve_cintx_dot_by_indexed_elem { + def _S : sve2_complex_int_arith_indexed<0b10, 0b0100, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { + bits<2> iop; + bits<3> Zm; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve2_complex_int_arith_indexed<0b11, 0b0100, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { + bit iop; + bits<4> Zm; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Complex Multiply-Add - Indexed Group +//===----------------------------------------------------------------------===// + +multiclass sve_cmla_by_indexed_elem { + def _H : sve2_complex_int_arith_indexed<0b10, { 0b011, opc }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexS> { + bits<2> iop; + bits<3> Zm; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _S : sve2_complex_int_arith_indexed<0b11, { 0b011, opc }, asm, ZPR32, ZPR32, ZPR4b32, VectorIndexD> { + bit iop; + bits<4> Zm; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer Multiply - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_int_mul sz, bits<3> opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b011; + let Inst{12-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_mul opc, string asm> { + def _B : sve_int_mul<0b00, opc, asm, ZPR8>; + def _H : sve_int_mul<0b01, opc, asm, ZPR16>; + def _S : sve_int_mul<0b10, opc, asm, ZPR32>; + def _D : sve_int_mul<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer Multiply - Indexed Group +//===----------------------------------------------------------------------===// + +class sve_int_mul_by_indexed_elem sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + ZPRRegOp zprty3, Operand itype> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop), + asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{15-14} = 0b11; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_mul_by_indexed_elem opc, string asm> { + def _H : sve_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{22} = iop{2}; + let Inst{20-19} = iop{1-0}; + let Inst{18-16} = Zm; + } + def _S : sve_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> { + bits<3> Zm; + bits<2> iop; + let Inst{20-19} = iop; + let Inst{18-16} = Zm; + } + def _D : sve_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> { + bits<4> Zm; + bit iop; + let Inst{20} = iop; + let Inst{19-16} = Zm; + } +} + +multiclass sve_int_mul_long_by_indexed_elem opc, string asm> { + def _S : sve_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm, + ZPR32, ZPR16, ZPR3b16, VectorIndexH> { + bits<3> Zm; + bits<3> iop; + let Inst{20-19} = iop{2-1}; + let Inst{18-16} = Zm; + let Inst{11} = iop{0}; + } + def _D : sve_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm, + ZPR64, ZPR32, ZPR4b32, VectorIndexS> { + bits<4> Zm; + bits<2> iop; + let Inst{20} = iop{1}; + let Inst{19-16} = Zm; + let Inst{11} = iop{0}; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Integer - Predicated Group +//===----------------------------------------------------------------------===// + +class sve2_int_arith_pred sz, bits<6> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { + bits<3> Pg; + bits<5> Zm; + bits<5> Zdn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21-20} = 0b01; + let Inst{20-16} = opc{5-1}; + let Inst{15-14} = 0b10; + let Inst{13} = opc{0}; + let Inst{12-10} = Pg; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = zprty.ElementSize; +} + +multiclass sve2_int_arith_pred opc, string asm> { + def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>; + def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>; + def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>; + def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>; +} + +class sve2_int_sadd_long_accum_pairwise sz, bit U, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn), + asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> Zda; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21-17} = 0b00010; + let Inst{16} = U; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = zprty1.ElementSize; +} + +multiclass sve2_int_sadd_long_accum_pairwise { + def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>; + def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>; + def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>; +} + +class sve2_int_un_pred_arit sz, bit Q, bits<2> opc, + string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Zd, $Pg/m, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01000100; + let Inst{23-22} = sz; + let Inst{21-20} = 0b00; + let Inst{19} = Q; + let Inst{18} = 0b0; + let Inst{17-16} = opc; + let Inst{15-13} = 0b101; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; + + let Constraints = "$Zd = $_Zd"; + let DestructiveInstType = Destructive; + let ElementSize = zprty.ElementSize; +} + +multiclass sve2_int_un_pred_arit_s opc, string asm> { + def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>; +} + +multiclass sve2_int_un_pred_arit opc, string asm> { + def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>; + def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>; + def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>; + def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Widening Integer Arithmetic Group +//===----------------------------------------------------------------------===// + +class sve2_wide_int_arith sz, bits<5> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15} = 0b0; + let Inst{14-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_wide_int_arith_long opc, string asm> { + def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>; + def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>; + def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>; +} + +multiclass sve2_wide_int_arith_wide opc, string asm> { + def _H : sve2_wide_int_arith<0b01, { 0b10, opc }, asm, ZPR16, ZPR16, ZPR8>; + def _S : sve2_wide_int_arith<0b10, { 0b10, opc }, asm, ZPR32, ZPR32, ZPR16>; + def _D : sve2_wide_int_arith<0b11, { 0b10, opc }, asm, ZPR64, ZPR64, ZPR32>; +} + +multiclass sve2_pmul_long opc, string asm> { + def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>; + def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Misc Group +//===----------------------------------------------------------------------===// + +class sve2_misc sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15-14} = 0b10; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_misc_bitwise opc, string asm> { + def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>; + def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>; + def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>; + def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>; +} + +multiclass sve2_bitwise_xor_interleaved { + let DestructiveInstType = Destructive, ElementSize = ElementSizeNone in { + def _B : sve2_misc<0b00, { 0b010, opc }, asm, ZPR8, ZPR8>; + def _H : sve2_misc<0b01, { 0b010, opc }, asm, ZPR16, ZPR16>; + def _S : sve2_misc<0b10, { 0b010, opc }, asm, ZPR32, ZPR32>; + def _D : sve2_misc<0b11, { 0b010, opc }, asm, ZPR64, ZPR64>; + } +} + +multiclass sve2_misc_int_addsub_long_interleaved opc, string asm> { + def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>; + def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>; + def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>; +} + +class sve2_bitwise_shift_left_long tsz8_64, bits<2> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2, + Operand immtype> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm), + asm, "\t$Zd, $Zn, $imm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> imm; + let Inst{31-23} = 0b010001010; + let Inst{22} = tsz8_64{2}; + let Inst{21} = 0b0; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-12} = 0b1010; + let Inst{11-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_bitwise_shift_left_long opc, string asm> { + def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm, + ZPR16, ZPR8, vecshiftL8>; + def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm, + ZPR32, ZPR16, vecshiftL16> { + let Inst{19} = imm{3}; + } + def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm, + ZPR64, ZPR32, vecshiftL32> { + let Inst{20-19} = imm{4-3}; + } +} + +//===----------------------------------------------------------------------===// +// SVE2 Accumulate Group +//===----------------------------------------------------------------------===// + +class sve2_int_bin_cons_shift_imm tsz8_64, bit opc, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), + asm, "\t$Zd, $Zn, $imm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<6> imm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = tsz8_64{3-2}; + let Inst{21} = 0b0; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-11} = 0b11110; + let Inst{10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_bin_cons_shift_imm_left { + def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; + def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { + let Inst{19} = imm{3}; + } + def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { + let Inst{20-19} = imm{4-3}; + } + def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { + let Inst{22} = imm{5}; + let Inst{20-19} = imm{4-3}; + } +} + +multiclass sve2_int_bin_cons_shift_imm_right { + def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { + let Inst{19} = imm{3}; + } + def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + let Inst{20-19} = imm{4-3}; + } + def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + let Inst{22} = imm{5}; + let Inst{20-19} = imm{4-3}; + } +} + +class sve2_int_bin_accum_cons_shift_imm tsz8_64, bits<2> opc, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm), + asm, "\t$Zda, $Zn, $imm", + "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<6> imm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = tsz8_64{3-2}; + let Inst{21} = 0b0; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-12} = 0b1110; + let Inst{11-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_bin_accum_cons_shift_imm_right opc, string asm> { + def _B : sve2_int_bin_accum_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve2_int_bin_accum_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { + let Inst{19} = imm{3}; + } + def _S : sve2_int_bin_accum_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + let Inst{20-19} = imm{4-3}; + } + def _D : sve2_int_bin_accum_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + let Inst{22} = imm{5}; + let Inst{20-19} = imm{4-3}; + } +} + +class sve2_int_cadd sz, bit opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot), + asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zm; + bit rot; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21-17} = 0b00000; + let Inst{16} = opc; + let Inst{15-11} = 0b11011; + let Inst{10} = rot; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_cadd { + def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>; + def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>; + def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>; + def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>; +} + +class sve2_int_absdiff_accum sz, bits<4> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b0; + let Inst{20-16} = Zm; + let Inst{15-14} = 0b11; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_absdiff_accum { + def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>; + def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>; + def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>; + def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>; +} + +multiclass sve2_int_absdiff_accum_long opc, string asm> { + def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>; + def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>; + def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>; +} + +multiclass sve2_int_addsub_long_carry opc, string asm> { + def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm, + ZPR32, ZPR32>; + def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm, + ZPR64, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Narrowing Group +//===----------------------------------------------------------------------===// + +class sve2_int_bin_cons_shift_imm_narrow tsz8_64, bits<4> opc, + string asm, ZPRRegOp zprty1, + ZPRRegOp zprty2, Operand immtype> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm), + asm, "\t$Zd, $Zn, $imm", + "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> imm; + let Inst{31-23} = 0b010001010; + let Inst{22} = tsz8_64{2}; + let Inst{21} = 0b1; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-14} = 0b00; + let Inst{13-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_bin_cons_shift_imm_right_narrow opc, string asm> { + def _B : sve2_int_bin_cons_shift_imm_narrow<{0,0,1}, opc, asm, ZPR8, ZPR16, + vecshiftR8>; + def _H : sve2_int_bin_cons_shift_imm_narrow<{0,1,?}, opc, asm, ZPR16, ZPR32, + vecshiftR16> { + let Inst{19} = imm{3}; + } + def _S : sve2_int_bin_cons_shift_imm_narrow<{1,?,?}, opc, asm, ZPR32, ZPR64, + vecshiftR32> { + let Inst{20-19} = imm{4-3}; + } +} + +class sve2_int_addsub_narrow_high sz, bits<3> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm), + asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-24} = 0b01000101; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b011; + let Inst{12-10} = opc; // S, R, T + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_addsub_narrow_high opc, string asm> { + def _B : sve2_int_addsub_narrow_high<0b01, opc, asm, ZPR8, ZPR16>; + def _H : sve2_int_addsub_narrow_high<0b10, opc, asm, ZPR16, ZPR32>; + def _S : sve2_int_addsub_narrow_high<0b11, opc, asm, ZPR32, ZPR64>; +} + +class sve2_int_sat_extract_narrow tsz8_64, bits<3> opc, string asm, + ZPRRegOp zprty1, ZPRRegOp zprty2> +: I<(outs zprty1:$Zd), (ins zprty2:$Zn), + asm, "\t$Zd, $Zn", "", []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-23} = 0b010001010; + let Inst{22} = tsz8_64{2}; let Inst{21} = 0b1; - let Inst{15-11} = 0; - let Inst{10} = U; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-13} = 0b000010; + let Inst{12-10} = opc; let Inst{9-5} = Zn; - let Inst{4-0} = Zda; - - let Constraints = "$Zda = $_Zda"; - let DestructiveInstType = Destructive; - let ElementSize = ElementSizeNone; + let Inst{4-0} = Zd; } -multiclass sve_intx_dot_by_indexed_elem { - def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> { - bits<2> iop; - bits<3> Zm; - let Inst{20-19} = iop; - let Inst{18-16} = Zm; - } - def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> { - bits<1> iop; - bits<4> Zm; - let Inst{20} = iop; - let Inst{19-16} = Zm; - } +multiclass sve2_int_sat_extract_narrow opc, string asm> { + def _B : sve2_int_sat_extract_narrow<0b001, opc, asm, ZPR8, ZPR16>; + def _H : sve2_int_sat_extract_narrow<0b010, opc, asm, ZPR16, ZPR32>; + def _S : sve2_int_sat_extract_narrow<0b100, opc, asm, ZPR32, ZPR64>; } //===----------------------------------------------------------------------===// @@ -1982,6 +2908,75 @@ let Inst{4-0} = Zd; } +class sve2_int_bitwise_ternary_op_d opc, string asm> +: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk), + asm, "\t$Zdn, $_Zdn, $Zm, $Zk", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zk; + bits<5> Zm; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = opc{2-1}; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-11} = 0b00111; + let Inst{10} = opc{0}; + let Inst{9-5} = Zk; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_bitwise_ternary_op opc, string asm> { + def NAME : sve2_int_bitwise_ternary_op_d; + + def : InstAlias(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>; + def : InstAlias(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>; + def : InstAlias(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>; +} + +class sve2_int_rotate_right_imm tsz8_64, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm), + asm, "\t$Zdn, $_Zdn, $Zm, $imm", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zm; + bits<6> imm; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = tsz8_64{3-2}; + let Inst{21} = 0b1; + let Inst{20-19} = tsz8_64{1-0}; + let Inst{18-16} = imm{2-0}; // imm3 + let Inst{15-10} = 0b001101; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; + let DestructiveInstType = Destructive; + let ElementSize = ElementSizeNone; +} + +multiclass sve2_int_rotate_right_imm { + def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>; + def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> { + let Inst{19} = imm{3}; + } + def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> { + let Inst{20-19} = imm{4-3}; + } + def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> { + let Inst{22} = imm{5}; + let Inst{20-19} = imm{4-3}; + } +} //===----------------------------------------------------------------------===// // SVE Integer Wide Immediate - Predicated Group @@ -2265,6 +3260,33 @@ def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>; } +class sve2_int_while_rr sz8_64, bits<1> rw, string asm, + PPRRegOp pprty> +: I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm), + asm, "\t$Pd, $Rn, $Rm", + "", []>, Sched<[]> { + bits<4> Pd; + bits<5> Rm; + bits<5> Rn; + let Inst{31-24} = 0b00100101; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Rm; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Rn; + let Inst{4} = rw; + let Inst{3-0} = Pd; + + let Defs = [NZCV]; +} + +multiclass sve2_int_while_rr rw, string asm> { + def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>; + def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>; + def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>; + def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>; +} + //===----------------------------------------------------------------------===// // SVE Floating Point Fast Reduction Group @@ -2496,7 +3518,7 @@ //===----------------------------------------------------------------------===// // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_pred_shift_imm tsz8_64, bits<3> opc, string asm, +class sve_int_bin_pred_shift_imm tsz8_64, bits<4> opc, string asm, ZPRRegOp zprty, Operand immtype, ElementSizeEnum size> : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), @@ -2508,8 +3530,8 @@ bits<6> imm; let Inst{31-24} = 0b00000100; let Inst{23-22} = tsz8_64{3-2}; - let Inst{21-19} = 0b000; - let Inst{18-16} = opc; + let Inst{21-20} = 0b00; + let Inst{19-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; let Inst{9-8} = tsz8_64{1-0}; @@ -2521,7 +3543,7 @@ let ElementSize = size; } -multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16, @@ -2539,7 +3561,7 @@ } } -multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { +multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8, ElementSizeB>; def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16, @@ -2855,6 +3877,43 @@ (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } +class sve2_mem_cstnt_vs_base opc, dag iops, string asm, + RegisterOperand VecList> +: I<(outs VecList:$Zt), iops, + asm, "\t$Zt, $Pg, [$Zn, $Rm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rm; + bits<5> Zn; + bits<5> Zt; + let Inst{31-25} = 0b1110010; + let Inst{24-22} = opc; + let Inst{21} = 0b0; + let Inst{20-16} = Rm; + let Inst{15-13} = 0b001; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve2_mem_cstnt_vs opc, string asm, + RegisterOperand listty, ZPRRegOp zprty> { + def _REAL : sve2_mem_cstnt_vs_base; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; +} + class sve_mem_sst_sv opc, bit xs, bit scaled, string asm, RegisterOperand VecList, RegisterOperand zprext> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), @@ -3303,6 +4362,30 @@ def _D : sve_int_perm_splice<0b11, asm, ZPR64>; } +class sve2_int_perm_splice_cons sz8_64, string asm, + ZPRRegOp zprty, RegisterOperand VecList> +: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn), + asm, "\t$Zd, $Pg, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> Zd; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-13} = 0b101101100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_int_perm_splice_cons { + def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>; + def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>; + def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>; + def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>; +} + class sve_int_perm_rev sz8_64, bits<2> opc, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn), @@ -4002,6 +5085,46 @@ (!cast(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; } +class sve2_mem_cldnt_vs_base opc, dag iops, string asm, + RegisterOperand VecList> +: I<(outs VecList:$Zt), iops, + asm, "\t$Zt, $Pg/z, [$Zn, $Rm]", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Rm; + bits<5> Zn; + bits<5> Zt; + let Inst{31} = 0b1; + let Inst{30} = opc{4}; + let Inst{29-25} = 0b00010; + let Inst{24-23} = opc{3-2}; + let Inst{22-21} = 0b00; + let Inst{20-16} = Rm; + let Inst{15} = 0b1; + let Inst{14-13} = opc{1-0}; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zt; + + let mayLoad = 1; +} + +multiclass sve2_mem_cldnt_vs opc, string asm, + RegisterOperand listty, ZPRRegOp zprty> { + def _REAL : sve2_mem_cldnt_vs_base; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>; + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>; +} + //===----------------------------------------------------------------------===// // SVE Memory - 64-bit Gather Group //===----------------------------------------------------------------------===// @@ -4453,3 +5576,132 @@ def NAME : sve_int_break; } +//===----------------------------------------------------------------------===// +// SVE2 String Processing Group +//===----------------------------------------------------------------------===// + +class sve2_char_match +: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), + asm, "\t$Pd, $Pg/z, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<4> Pd; + bits<3> Pg; + bits<5> Zm; + bits<5> Zn; + let Inst{31-23} = 0b010001010; + let Inst{22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4} = opc; + let Inst{3-0} = Pd; + + let Defs = [NZCV]; +} + +multiclass sve2_char_match { + def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>; + def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Histogram Computation - Segment Group +//===----------------------------------------------------------------------===// + +class sve2_hist_gen_segment +: I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-21} = 0b01000101001; + let Inst{20-16} = Zm; + let Inst{15-10} = 0b101000; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +//===----------------------------------------------------------------------===// +// SVE2 Histogram Computation - Vector Group +//===----------------------------------------------------------------------===// + +class sve2_hist_gen_vector +: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Pg/z, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<3> Pg; + bits<5> Zm; + let Inst{31-23} = 0b010001011; + let Inst{22} = sz; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b110; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve2_hist_gen_vector { + def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>; + def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE2 Crypto Extensions Group +//===----------------------------------------------------------------------===// + +class sve2_crypto_cons_bin_op +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + bits<5> Zm; + let Inst{31-21} = 0b01000101001; + let Inst{20-16} = Zm; + let Inst{15-11} = 0b11110; + let Inst{10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +class sve2_crypto_des_bin_op opc, string asm, ZPRRegOp zprty> +: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm), + asm, "\t$Zdn, $_Zdn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zdn; + bits<5> Zm; + let Inst{31-17} = 0b010001010010001; + let Inst{16} = opc{1}; + let Inst{15-11} = 0b11100; + let Inst{10} = opc{0}; + let Inst{9-5} = Zm; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +class sve2_crypto_unary_op +: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn), + asm, "\t$Zdn, $_Zdn", + "", + []>, Sched<[]> { + bits<5> Zdn; + let Inst{31-11} = 0b010001010010000011100; + let Inst{10} = opc; + let Inst{9-5} = 0b00000; + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} Index: test/MC/AArch64/SVE/ldnt1b-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/ldnt1b-diagnostics.s +++ test/MC/AArch64/SVE/ldnt1b-diagnostics.s @@ -23,12 +23,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.s, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ldnt1b z0.s, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ldnt1b z0.d, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ldnt1b z0.d, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE/movprfx-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/movprfx-diagnostics.s +++ test/MC/AArch64/SVE/movprfx-diagnostics.s @@ -111,6 +111,16 @@ // ------------------------------------------------------------------------- // +// Destination used in other operand (ternary + indexed) + +movprfx z0, z1 +sdot z0.s, z1.b, z0.b[3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source +// CHECK-NEXT: sdot z0.s, z1.b, z0.b[3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // // Different general predicate (unary) movprfx z0.d, p0/m, z1.d Index: test/MC/AArch64/SVE/stnt1b-diagnostics.s =================================================================== --- test/MC/AArch64/SVE/stnt1b-diagnostics.s +++ test/MC/AArch64/SVE/stnt1b-diagnostics.s @@ -23,12 +23,12 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.s, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: stnt1b z0.s, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: stnt1b z0.d, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/adclb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/adclb-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +adclb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: adclb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +adclb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: adclb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +adclb z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: adclb z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/adclb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/adclb.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +adclb z0.s, z1.s, z31.s +// CHECK-INST: adclb z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xd0,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 1f 45 + +adclb z0.d, z1.d, z31.d +// CHECK-INST: adclb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 5f 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +adclb z0.d, z1.d, z31.d +// CHECK-INST: adclb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 5f 45 Index: test/MC/AArch64/SVE2/adclt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/adclt-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +adclt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: adclt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +adclt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: adclt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +adclt z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: adclt z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/adclt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/adclt.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +adclt z0.s, z1.s, z31.s +// CHECK-INST: adclt z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xd4,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 1f 45 + +adclt z0.d, z1.d, z31.d +// CHECK-INST: adclt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 5f 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +adclt z0.d, z1.d, z31.d +// CHECK-INST: adclt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 5f 45 Index: test/MC/AArch64/SVE2/addhnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addhnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +addhnb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +addhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +addhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/addhnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addhnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +addhnb z0.b, z1.h, z31.h +// CHECK-INST: addhnb z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x60,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 7f 45 + +addhnb z0.h, z1.s, z31.s +// CHECK-INST: addhnb z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x60,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 bf 45 + +addhnb z0.s, z1.d, z31.d +// CHECK-INST: addhnb z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x60,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 ff 45 Index: test/MC/AArch64/SVE2/addhnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addhnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +addhnt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addhnt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addhnt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +addhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +addhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: addhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/addhnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addhnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +addhnt z0.b, z1.h, z31.h +// CHECK-INST: addhnt z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x64,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 7f 45 + +addhnt z0.h, z1.s, z31.s +// CHECK-INST: addhnt z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x64,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 bf 45 + +addhnt z0.s, z1.d, z31.d +// CHECK-INST: addhnt z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x64,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 ff 45 Index: test/MC/AArch64/SVE2/addp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +addp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: addp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +addp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +addp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: addp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/addp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/addp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +addp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: addp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 11 44 + +addp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: addp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 51 44 + +addp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: addp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 91 44 + +addp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d1 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +addp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d1 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +addp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: addp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d1 44 Index: test/MC/AArch64/SVE2/aesd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesd-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +aesd z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: aesd z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +aesd z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesd z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesd z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesd z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesd z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesd z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +aesd z0.b, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesd z0.b, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +aesd z0.b, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesd z0.b, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/aesd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesd.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +aesd z0.b, z0.b, z31.b +// CHECK-INST: aesd z0.b, z0.b, z31.b +// CHECK-ENCODING: [0xe0,0xe7,0x22,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: e0 e7 22 45 Index: test/MC/AArch64/SVE2/aese-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aese-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +aese z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: aese z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +aese z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aese z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aese z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aese z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aese z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aese z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +aese z0.b, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aese z0.b, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +aese z0.b, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aese z0.b, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/aese.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aese.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +aese z0.b, z0.b, z31.b +// CHECK-INST: aese z0.b, z0.b, z31.b +// CHECK-ENCODING: [0xe0,0xe3,0x22,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: e0 e3 22 45 Index: test/MC/AArch64/SVE2/aesimc-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesimc-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +aesimc z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: aesimc z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +aesimc z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesimc z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesimc z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesimc z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesimc z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesimc z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +aesimc z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesimc z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +aesimc z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesimc z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/aesimc.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesimc.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +aesimc z0.b, z0.b +// CHECK-INST: aesimc z0.b, z0.b +// CHECK-ENCODING: [0x00,0xe4,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: 00 e4 20 45 + +aesimc z31.b, z31.b +// CHECK-INST: aesimc z31.b, z31.b +// CHECK-ENCODING: [0x1f,0xe4,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: 1f e4 20 45 Index: test/MC/AArch64/SVE2/aesmc-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesmc-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +aesmc z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: aesmc z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +aesmc z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesmc z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesmc z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesmc z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +aesmc z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: aesmc z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +aesmc z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesmc z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +aesmc z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: aesmc z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/aesmc.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/aesmc.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +aesmc z0.b, z0.b +// CHECK-INST: aesmc z0.b, z0.b +// CHECK-ENCODING: [0x00,0xe0,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: 00 e0 20 45 + +aesmc z31.b, z31.b +// CHECK-INST: aesmc z31.b, z31.b +// CHECK-ENCODING: [0x1f,0xe0,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: 1f e0 20 45 Index: test/MC/AArch64/SVE2/bcax-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bcax-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bcax z0.b, z0.b, z1.s, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bcax z0.b, z0.b, z1.s, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bcax z0.h, z0.h, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bcax z0.h, z0.h, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bcax z0.d, z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bcax z0.d, z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +bcax z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bcax z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bcax z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bcax z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bcax.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bcax.s @@ -0,0 +1,52 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bcax z29.d, z29.d, z30.d, z31.d +// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 7e 04 + + +// --------------------------------------------------------------------------// +// Test aliases. + +bcax z29.b, z29.b, z30.b, z31.b +// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 7e 04 + +bcax z29.h, z29.h, z30.h, z31.h +// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 7e 04 + +bcax z29.s, z29.s, z30.s, z31.s +// CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 7e 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +bcax z31.d, z31.d, z30.d, z29.d +// CHECK-INST: bcax z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3b,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3b 7e 04 Index: test/MC/AArch64/SVE2/bdep-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bdep-diagnostics.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bdep z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bdep z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +bdep z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bdep z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +bdep z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bdep z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bdep.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bdep.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bdep z0.b, z1.b, z31.b +// CHECK-INST: bdep z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xb4,0x1f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b4 1f 45 + +bdep z0.h, z1.h, z31.h +// CHECK-INST: bdep z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xb4,0x5f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b4 5f 45 + +bdep z0.s, z1.s, z31.s +// CHECK-INST: bdep z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xb4,0x9f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b4 9f 45 + +bdep z0.d, z1.d, z31.d +// CHECK-INST: bdep z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xb4,0xdf,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b4 df 45 Index: test/MC/AArch64/SVE2/bext-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bext-diagnostics.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bext z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bext z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +bext z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bext z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +bext z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bext z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bext.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bext.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bext z0.b, z1.b, z31.b +// CHECK-INST: bext z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xb0,0x1f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b0 1f 45 + +bext z0.h, z1.h, z31.h +// CHECK-INST: bext z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xb0,0x5f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b0 5f 45 + +bext z0.s, z1.s, z31.s +// CHECK-INST: bext z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xb0,0x9f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b0 9f 45 + +bext z0.d, z1.d, z31.d +// CHECK-INST: bext z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xb0,0xdf,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b0 df 45 Index: test/MC/AArch64/SVE2/bgrp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bgrp-diagnostics.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bgrp z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bgrp z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +bgrp z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bgrp z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +bgrp z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bgrp z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bgrp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bgrp.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+bitperm < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d -mattr=+bitperm - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+bitperm < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bgrp z0.b, z1.b, z31.b +// CHECK-INST: bgrp z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xb8,0x1f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b8 1f 45 + +bgrp z0.h, z1.h, z31.h +// CHECK-INST: bgrp z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xb8,0x5f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b8 5f 45 + +bgrp z0.s, z1.s, z31.s +// CHECK-INST: bgrp z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xb8,0x9f,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b8 9f 45 + +bgrp z0.d, z1.d, z31.d +// CHECK-INST: bgrp z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xb8,0xdf,0x45] +// CHECK-ERROR: instruction requires: bitperm +// CHECK-UNKNOWN: 20 b8 df 45 Index: test/MC/AArch64/SVE2/bsl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bsl z0.b, z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl z0.b, z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl z0.h, z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl z0.h, z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl z0.s, z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl z0.s, z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +bsl z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bsl z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bsl z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bsl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl.s @@ -0,0 +1,30 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bsl z0.d, z0.d, z1.d, z2.d +// CHECK-INST: bsl z0.d, z0.d, z1.d, z2.d +// CHECK-ENCODING: [0x40,0x3c,0x21,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 40 3c 21 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +bsl z31.d, z31.d, z30.d, z29.d +// CHECK-INST: bsl z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3f,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3f 3e 04 Index: test/MC/AArch64/SVE2/bsl1n-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl1n-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bsl1n z0.b, z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl1n z0.b, z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl1n z0.h, z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl1n z0.h, z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl1n z0.s, z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl1n z0.s, z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +bsl1n z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bsl1n z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bsl1n z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bsl1n z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bsl1n.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl1n.s @@ -0,0 +1,30 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bsl1n z0.d, z0.d, z1.d, z2.d +// CHECK-INST: bsl1n z0.d, z0.d, z1.d, z2.d +// CHECK-ENCODING: [0x40,0x3c,0x61,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 40 3c 61 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +bsl1n z31.d, z31.d, z30.d, z29.d +// CHECK-INST: bsl1n z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3f,0x7e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3f 7e 04 Index: test/MC/AArch64/SVE2/bsl2n-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl2n-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +bsl2n z0.b, z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl2n z0.b, z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl2n z0.h, z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl2n z0.h, z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bsl2n z0.s, z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bsl2n z0.s, z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +bsl2n z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: bsl2n z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +bsl2n z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: bsl2n z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/bsl2n.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/bsl2n.s @@ -0,0 +1,30 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +bsl2n z0.d, z0.d, z1.d, z2.d +// CHECK-INST: bsl2n z0.d, z0.d, z1.d, z2.d +// CHECK-ENCODING: [0x40,0x3c,0xa1,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 40 3c a1 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +bsl2n z31.d, z31.d, z30.d, z29.d +// CHECK-INST: bsl2n z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3f,0xbe,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3f be 04 Index: test/MC/AArch64/SVE2/cadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cadd-diagnostics.s @@ -0,0 +1,38 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +cadd z0.d, z1.d, z2.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: cadd z0.d, z1.d, z2.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +cadd z0.d, z0.d, z1.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cadd z0.d, z0.d, z1.d, #180 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #180 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cadd z0.d, z0.d, z1.d, #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cadd z0.d, z0.d, z31.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: cadd z0.d, z0.d, z31.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/cadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cadd.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +cadd z0.b, z0.b, z0.b, #90 +// CHECK-INST: cadd z0.b, z0.b, z0.b, #90 +// CHECK-ENCODING: [0x00,0xd8,0x00,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 00 45 + +cadd z0.h, z0.h, z0.h, #90 +// CHECK-INST: cadd z0.h, z0.h, z0.h, #90 +// CHECK-ENCODING: [0x00,0xd8,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 40 45 + +cadd z0.s, z0.s, z0.s, #90 +// CHECK-INST: cadd z0.s, z0.s, z0.s, #90 +// CHECK-ENCODING: [0x00,0xd8,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 80 45 + +cadd z0.d, z0.d, z0.d, #90 +// CHECK-INST: cadd z0.d, z0.d, z0.d, #90 +// CHECK-ENCODING: [0x00,0xd8,0xc0,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 c0 45 + +cadd z31.b, z31.b, z31.b, #270 +// CHECK-INST: cadd z31.b, z31.b, z31.b, #270 +// CHECK-ENCODING: [0xff,0xdf,0x00,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 45 + +cadd z31.h, z31.h, z31.h, #270 +// CHECK-INST: cadd z31.h, z31.h, z31.h, #270 +// CHECK-ENCODING: [0xff,0xdf,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 40 45 + +cadd z31.s, z31.s, z31.s, #270 +// CHECK-INST: cadd z31.s, z31.s, z31.s, #270 +// CHECK-ENCODING: [0xff,0xdf,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 45 + +cadd z31.d, z31.d, z31.d, #270 +// CHECK-INST: cadd z31.d, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xff,0xdf,0xc0,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df c0 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +cadd z4.d, z4.d, z31.d, #270 +// CHECK-INST: cadd z4.d, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0xdf,0xc0,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 df c0 45 Index: test/MC/AArch64/SVE2/cdot-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cdot-diagnostics.s @@ -0,0 +1,103 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +cdot z0.s, z1.h, z31.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.s, z1.h, z31.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.s, z1.s, z31.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.s, z1.s, z31.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.s, z1.d, z31.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.s, z1.d, z31.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.b, z31.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.d, z1.b, z31.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.s, z31.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.d, z1.s, z31.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.d, z31.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cdot z0.d, z1.d, z31.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid restricted register for indexed vector. + +cdot z0.s, z1.b, z8.b[3], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: cdot z0.s, z1.b, z8.b[3], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.h, z16.h[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: cdot z0.d, z1.h, z16.h[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +cdot z0.s, z1.b, z7.b[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: cdot z0.s, z1.b, z7.b[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.s, z1.b, z7.b[4], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: cdot z0.s, z1.b, z7.b[4], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.h, z15.h[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: cdot z0.d, z1.h, z15.h[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.h, z15.h[2], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: cdot z0.d, z1.h, z15.h[2], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +cdot z0.s, z1.b, z2.b[0], #360 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: cdot z0.s, z1.b, z2.b[0], #360 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cdot z0.d, z1.h, z2.h[0], #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: cdot z0.d, z1.h, z2.h[0], #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +cdot z0.d, z1.h, z31.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: cdot z0.d, z1.h, z31.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +cdot z0.d, z1.h, z15.h[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: cdot z0.d, z1.h, z15.h[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/cdot.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cdot.s @@ -0,0 +1,96 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +cdot z0.s, z1.b, z31.b, #0 +// CHECK-INST: cdot z0.s, z1.b, z31.b, #0 +// CHECK-ENCODING: [0x20,0x10,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 9f 44 + +cdot z0.d, z1.h, z31.h, #0 +// CHECK-INST: cdot z0.d, z1.h, z31.h, #0 +// CHECK-ENCODING: [0x20,0x10,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 df 44 + +cdot z0.d, z1.h, z31.h, #90 +// CHECK-INST: cdot z0.d, z1.h, z31.h, #90 +// CHECK-ENCODING: [0x20,0x14,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 df 44 + +cdot z0.d, z1.h, z31.h, #180 +// CHECK-INST: cdot z0.d, z1.h, z31.h, #180 +// CHECK-ENCODING: [0x20,0x18,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 18 df 44 + +cdot z0.d, z1.h, z31.h, #270 +// CHECK-INST: cdot z0.d, z1.h, z31.h, #270 +// CHECK-ENCODING: [0x20,0x1c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 1c df 44 + +cdot z0.s, z1.b, z7.b[3], #0 +// CHECK-INST: cdot z0.s, z1.b, z7.b[3], #0 +// CHECK-ENCODING: [0x20,0x40,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 bf 44 + +cdot z0.d, z1.h, z15.h[1], #0 +// CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0 +// CHECK-ENCODING: [0x20,0x40,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 ff 44 + +cdot z5.d, z6.h, z3.h[0], #90 +// CHECK-INST: cdot z5.d, z6.h, z3.h[0], #90 +// CHECK-ENCODING: [0xc5,0x44,0xe3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: c5 44 e3 44 + +cdot z29.d, z30.h, z0.h[0], #180 +// CHECK-INST: cdot z29.d, z30.h, z0.h[0], #180 +// CHECK-ENCODING: [0xdd,0x4b,0xe0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 4b e0 44 + +cdot z31.d, z30.h, z7.h[1], #270 +// CHECK-INST: cdot z31.d, z30.h, z7.h[1], #270 +// CHECK-ENCODING: [0xdf,0x4f,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 4f f7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +cdot z0.d, z1.h, z31.h, #0 +// CHECK-INST: cdot z0.d, z1.h, z31.h, #0 +// CHECK-ENCODING: [0x20,0x10,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 df 44 + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +cdot z0.d, z1.h, z15.h[1], #0 +// CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0 +// CHECK-ENCODING: [0x20,0x40,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 ff 44 Index: test/MC/AArch64/SVE2/cmla-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cmla-diagnostics.s @@ -0,0 +1,103 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +cmla z0.h, z1.b, z2.b[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.h, z1.b, z2.b[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.h, z1.s, z2.s[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.h, z1.s, z2.s[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.h, z1.d, z2.d[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.h, z1.d, z2.d[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.b, z2.b[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.s, z1.b, z2.b[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.h, z2.h[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.s, z1.h, z2.h[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.d, z2.d[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: cmla z0.s, z1.d, z2.d[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid restricted register for indexed vector. + +cmla z0.h, z1.h, z8.h[3], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: cmla z0.h, z1.h, z8.h[3], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.s, z16.s[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: cmla z0.s, z1.s, z16.s[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +cmla z0.h, z1.h, z7.h[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: cmla z0.h, z1.h, z7.h[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.h, z1.h, z7.h[4], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: cmla z0.h, z1.h, z7.h[4], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.s, z15.s[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: cmla z0.s, z1.s, z15.s[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.s, z15.s[2], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: cmla z0.s, z1.s, z15.s[2], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +cmla z0.h, z1.h, z2.h[0], #360 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: cmla z0.h, z1.h, z2.h[0], #360 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +cmla z0.s, z1.s, z2.s[0], #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: cmla z0.s, z1.s, z2.s[0], #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +cmla z0.b, z1.b, z31.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: cmla z0.b, z1.b, z31.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +cmla z0.s, z1.s, z15.s[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: cmla z0.s, z1.s, z15.s[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/cmla.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/cmla.s @@ -0,0 +1,156 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +cmla z0.b, z1.b, z2.b, #0 +// CHECK-INST: cmla z0.b, z1.b, z2.b, #0 +// CHECK-ENCODING: [0x20,0x20,0x02,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 02 44 + +cmla z0.h, z1.h, z2.h, #0 +// CHECK-INST: cmla z0.h, z1.h, z2.h, #0 +// CHECK-ENCODING: [0x20,0x20,0x42,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 42 44 + +cmla z0.s, z1.s, z2.s, #0 +// CHECK-INST: cmla z0.s, z1.s, z2.s, #0 +// CHECK-ENCODING: [0x20,0x20,0x82,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 82 44 + +cmla z0.d, z1.d, z2.d, #0 +// CHECK-INST: cmla z0.d, z1.d, z2.d, #0 +// CHECK-ENCODING: [0x20,0x20,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 c2 44 + +cmla z29.b, z30.b, z31.b, #90 +// CHECK-INST: cmla z29.b, z30.b, z31.b, #90 +// CHECK-ENCODING: [0xdd,0x27,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 27 1f 44 + +cmla z29.h, z30.h, z31.h, #90 +// CHECK-INST: cmla z29.h, z30.h, z31.h, #90 +// CHECK-ENCODING: [0xdd,0x27,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 27 5f 44 + +cmla z29.s, z30.s, z31.s, #90 +// CHECK-INST: cmla z29.s, z30.s, z31.s, #90 +// CHECK-ENCODING: [0xdd,0x27,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 27 9f 44 + +cmla z29.d, z30.d, z31.d, #90 +// CHECK-INST: cmla z29.d, z30.d, z31.d, #90 +// CHECK-ENCODING: [0xdd,0x27,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 27 df 44 + +cmla z31.b, z31.b, z31.b, #180 +// CHECK-INST: cmla z31.b, z31.b, z31.b, #180 +// CHECK-ENCODING: [0xff,0x2b,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 1f 44 + +cmla z31.h, z31.h, z31.h, #180 +// CHECK-INST: cmla z31.h, z31.h, z31.h, #180 +// CHECK-ENCODING: [0xff,0x2b,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 5f 44 + +cmla z31.s, z31.s, z31.s, #180 +// CHECK-INST: cmla z31.s, z31.s, z31.s, #180 +// CHECK-ENCODING: [0xff,0x2b,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 9f 44 + +cmla z31.d, z31.d, z31.d, #180 +// CHECK-INST: cmla z31.d, z31.d, z31.d, #180 +// CHECK-ENCODING: [0xff,0x2b,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b df 44 + +cmla z15.b, z16.b, z17.b, #270 +// CHECK-INST: cmla z15.b, z16.b, z17.b, #270 +// CHECK-ENCODING: [0x0f,0x2e,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 2e 11 44 + +cmla z15.h, z16.h, z17.h, #270 +// CHECK-INST: cmla z15.h, z16.h, z17.h, #270 +// CHECK-ENCODING: [0x0f,0x2e,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 2e 51 44 + +cmla z15.s, z16.s, z17.s, #270 +// CHECK-INST: cmla z15.s, z16.s, z17.s, #270 +// CHECK-ENCODING: [0x0f,0x2e,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 2e 91 44 + +cmla z15.d, z16.d, z17.d, #270 +// CHECK-INST: cmla z15.d, z16.d, z17.d, #270 +// CHECK-ENCODING: [0x0f,0x2e,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 2e d1 44 + +cmla z0.h, z1.h, z2.h[0], #0 +// CHECK-INST: cmla z0.h, z1.h, z2.h[0], #0 +// CHECK-ENCODING: [0x20,0x60,0xa2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 a2 44 + +cmla z0.s, z1.s, z2.s[0], #0 +// CHECK-INST: cmla z0.s, z1.s, z2.s[0], #0 +// CHECK-ENCODING: [0x20,0x60,0xe2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 e2 44 + +cmla z31.h, z30.h, z7.h[0], #180 +// CHECK-INST: cmla z31.h, z30.h, z7.h[0], #180 +// CHECK-ENCODING: [0xdf,0x6b,0xa7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 6b a7 44 + +cmla z31.s, z30.s, z7.s[0], #180 +// CHECK-INST: cmla z31.s, z30.s, z7.s[0], #180 +// CHECK-ENCODING: [0xdf,0x6b,0xe7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 6b e7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +cmla z4.d, z31.d, z31.d, #270 +// CHECK-INST: cmla z4.d, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x2f,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 2f df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +cmla z21.s, z10.s, z5.s[1], #90 +// CHECK-INST: cmla z21.s, z10.s, z5.s[1], #90 +// CHECK-ENCODING: [0x55,0x65,0xf5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 65 f5 44 Index: test/MC/AArch64/SVE2/directive-arch-negative.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-arch-negative.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch armv8-a+nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.arch armv8-a+nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.arch armv8-a+nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.arch armv8-a+nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.arch armv8-a+nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/directive-arch.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-arch.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch armv8-a+sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.arch armv8-a+sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.arch armv8-a+sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.arch armv8-a+sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.arch armv8-a+bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/directive-arch_extension-negative.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-arch_extension-negative.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch_extension nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.arch_extension nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.arch_extension nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.arch_extension nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.arch_extension nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/directive-arch_extension.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-arch_extension.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch_extension sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.arch_extension sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.arch_extension sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.arch_extension sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.arch_extension bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/directive-cpu-negative.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-cpu-negative.s @@ -0,0 +1,26 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.cpu generic+nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.cpu generic+nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.cpu generic+nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.cpu generic+nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.cpu generic+nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/directive-cpu.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/directive-cpu.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.cpu generic+sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.cpu generic+sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.cpu generic+sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.cpu generic+sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.cpu generic+bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s Index: test/MC/AArch64/SVE2/eor3-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eor3-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +eor3 z0.b, z0.b, z1.s, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eor3 z0.b, z0.b, z1.s, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor3 z0.h, z0.h, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eor3 z0.h, z0.h, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +eor3 z0.d, z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eor3 z0.d, z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +eor3 z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: eor3 z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eor3 z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eor3 z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/eor3.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eor3.s @@ -0,0 +1,52 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +eor3 z29.d, z29.d, z30.d, z31.d +// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 3e 04 + + +// --------------------------------------------------------------------------// +// Test aliases. + +eor3 z29.b, z29.b, z30.b, z31.b +// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 3e 04 + +eor3 z29.h, z29.h, z30.h, z31.h +// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 3e 04 + +eor3 z29.s, z29.s, z30.s, z31.s +// CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d +// CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fd 3b 3e 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +eor3 z31.d, z31.d, z30.d, z29.d +// CHECK-INST: eor3 z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3b,0x3e,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3b 3e 04 Index: test/MC/AArch64/SVE2/eorbt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eorbt-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +eorbt z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eorbt z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eorbt z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eorbt z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/eorbt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eorbt.s @@ -0,0 +1,48 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +eorbt z0.b, z1.b, z31.b +// CHECK-INST: eorbt z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x90,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 90 1f 45 + +eorbt z0.h, z1.h, z31.h +// CHECK-INST: eorbt z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x90,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 90 5f 45 + +eorbt z0.s, z1.s, z31.s +// CHECK-INST: eorbt z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x90,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 90 9f 45 + +eorbt z0.d, z1.d, z31.d +// CHECK-INST: eorbt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x90,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 90 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +eorbt z0.d, z1.d, z31.d +// CHECK-INST: eorbt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x90,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 90 df 45 Index: test/MC/AArch64/SVE2/eortb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eortb-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +eortb z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: eortb z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +eortb z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: eortb z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/eortb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/eortb.s @@ -0,0 +1,48 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +eortb z0.b, z1.b, z31.b +// CHECK-INST: eortb z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x94,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 94 1f 45 + +eortb z0.h, z1.h, z31.h +// CHECK-INST: eortb z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x94,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 94 5f 45 + +eortb z0.s, z1.s, z31.s +// CHECK-INST: eortb z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x94,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 94 9f 45 + +eortb z0.d, z1.d, z31.d +// CHECK-INST: eortb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x94,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 94 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +eortb z0.d, z1.d, z31.d +// CHECK-INST: eortb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x94,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 94 df 45 Index: test/MC/AArch64/SVE2/ext-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ext-diagnostics.s @@ -0,0 +1,84 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element widths. + +ext z0.h, { z1.h, z2.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.h, { z1.h, z2.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.s, { z1.s, z2.s }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.s, { z1.s, z2.s }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.d, { z1.d, z2.d }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ext z0.d, { z1.d, z2.d }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid immediate range. + +ext z0.b, { z1.b, z2.b }, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. +// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.b }, #256 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 255]. +// CHECK-NEXT: ext z0.b, { z1.b, z2.b }, #256 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ext z0.b, { }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ext z0.b, { }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { z1.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.b, z3.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { z1.b, z2.b, z3.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z2.h }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { z1.b, z31.b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ext z0.b, { v0.4b, v1.4b }, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +ext z31.b, { z30.b, z31.b }, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/z, z6.b +ext z31.b, { z30.b, z31.b }, #255 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ext.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ext.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ext z0.b, { z1.b, z2.b }, #0 +// CHECK-INST: ext z0.b, { z1.b, z2.b }, #0 +// CHECK-ENCODING: [0x20,0x00,0x60,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 00 60 05 + +ext z31.b, { z30.b, z31.b }, #255 +// CHECK-INST: ext z31.b, { z30.b, z31.b }, #255 +// CHECK-ENCODING: [0xdf,0x1f,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 1f 7f 05 Index: test/MC/AArch64/SVE2/faddp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/faddp-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +faddp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: faddp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +faddp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +faddp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +faddp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: faddp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +faddp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: faddp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/faddp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/faddp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +faddp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x50,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 50 64 + +faddp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x90,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 90 64 + +faddp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +faddp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d0 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +faddp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 64 Index: test/MC/AArch64/SVE2/fcvtlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtlt-diagnostics.s @@ -0,0 +1,69 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtlt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.h, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.h, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtlt z0.q, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtlt z0.q, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtlt z0.s, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtlt z0.s, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtlt z0.s, p8/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtlt z0.s, p8/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtlt z0.s, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtlt z0.s, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtlt z0.s, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtlt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtlt z0.s, p0/m, z1.h +// CHECK-INST: fcvtlt z0.s, p0/m, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x89,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 89 64 + +fcvtlt z30.d, p7/m, z31.s +// CHECK-INST: fcvtlt z30.d, p7/m, z31.s +// CHECK-ENCODING: [0xfe,0xbf,0xcb,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf cb 64 Index: test/MC/AArch64/SVE2/fcvtnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtnt-diagnostics.s @@ -0,0 +1,69 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtnt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.b, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.b, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtnt z0.d, p0/m, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtnt z0.d, p0/m, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtnt z0.h, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtnt z0.h, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtnt z0.h, p8/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtnt z0.h, p8/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtnt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtnt z0.h, p0/m, z1.s +// CHECK-INST: fcvtnt z0.h, p0/m, z1.s +// CHECK-ENCODING: [0x20,0xa0,0x88,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 88 64 + +fcvtnt z30.s, p7/m, z31.d +// CHECK-INST: fcvtnt z30.s, p7/m, z31.d +// CHECK-ENCODING: [0xfe,0xbf,0xca,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf ca 64 Index: test/MC/AArch64/SVE2/fcvtx-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtx-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtx z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// error: restricted predicate has range [0, 7]. + +fcvtx z0.s, p8/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtx z0.s, p8/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtx.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtx.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtx z0.s, p0/m, z0.d +// CHECK-INST: fcvtx z0.s, p0/m, z0.d +// CHECK-ENCODING: [0x00,0xa0,0x0a,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a0 0a 65 + +fcvtx z30.s, p7/m, z31.d +// CHECK-INST: fcvtx z30.s, p7/m, z31.d +// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf 0a 65 + + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z5.d, p0/z, z7.d +// CHECK-INST: movprfx z5.d, p0/z, z7.d +// CHECK-ENCODING: [0xe5,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 20 d0 04 + +fcvtx z5.s, p0/m, z0.d +// CHECK-INST: fcvtx z5.s, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 05 a0 0a 65 + +movprfx z5, z7 +// CHECK-INST: movprfx z5, z7 +// CHECK-ENCODING: [0xe5,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e5 bc 20 04 + +fcvtx z5.s, p0/m, z0.d +// CHECK-INST: fcvtx z5.s, p0/m, z0.d +// CHECK-ENCODING: [0x05,0xa0,0x0a,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 05 a0 0a 65 Index: test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtxnt-diagnostics.s @@ -0,0 +1,74 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtxnt z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.h, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.s, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.s, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.d, p0/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.h, p0/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.h, p0/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.b, p0/m, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.b, p0/m, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtxnt z0.d, p0/m, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtxnt z0.d, p0/m, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +fcvtxnt z0.s, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvtxnt z0.s, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtxnt z0.s, p8/m, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fcvtxnt z0.s, p8/m, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtxnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtxnt z0.s, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtxnt z0.s, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fcvtxnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fcvtxnt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fcvtxnt z0.s, p0/m, z1.d +// CHECK-INST: fcvtxnt z0.s, p0/m, z1.d +// CHECK-ENCODING: [0x20,0xa0,0x0a,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 0a 64 + +fcvtxnt z30.s, p7/m, z31.d +// CHECK-INST: fcvtxnt z30.s, p7/m, z31.d +// CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf 0a 64 Index: test/MC/AArch64/SVE2/flogb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/flogb-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +flogb z0.b, p0/m, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: flogb z0.b, p0/m, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +flogb z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: flogb z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +flogb z0.s, p8/m, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] +// CHECK-NEXT: flogb z0.s, p8/m, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/flogb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/flogb.s @@ -0,0 +1,54 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +flogb z31.h, p7/m, z31.h +// CHECK-INST: flogb z31.h, p7/m, z31.h +// CHECK-ENCODING: [0xff,0xbf,0x1a,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1a 65 + +flogb z31.s, p7/m, z31.s +// CHECK-INST: flogb z31.s, p7/m, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x1c,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1c 65 + +flogb z31.d, p7/m, z31.d +// CHECK-INST: flogb z31.d, p7/m, z31.d +// CHECK-ENCODING: [0xff,0xbf,0x1e,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1e 65 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.d, p7/z, z6.d +// CHECK-INST: movprfx z4.d, p7/z, z6.d +// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c d0 04 + +flogb z4.d, p7/m, z31.d +// CHECK-INST: flogb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 1e 65 + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +flogb z4.d, p7/m, z31.d +// CHECK-INST: flogb z4.d, p7/m, z31.d +// CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 1e 65 Index: test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmaxnmp-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fmaxnmp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fmaxnmp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fmaxnmp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmaxnmp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxnmp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fmaxnmp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmaxnmp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmaxnmp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmaxnmp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmaxnmp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x54,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 54 64 + +fmaxnmp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x94,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 94 64 + +fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fmaxnmp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d4 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 64 Index: test/MC/AArch64/SVE2/fmaxp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmaxp-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fmaxp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fmaxp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fmaxp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fmaxp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmaxp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmaxp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fmaxp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fmaxp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmaxp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmaxp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fmaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x56,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 56 64 + +fmaxp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x96,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 96 64 + +fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fmaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d6 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 64 Index: test/MC/AArch64/SVE2/fminnmp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fminnmp-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fminnmp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fminnmp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fminnmp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fminnmp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fminnmp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminnmp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fminnmp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fminnmp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fminnmp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fminnmp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fminnmp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x55,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 55 64 + +fminnmp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x95,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 95 64 + +fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fminnmp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d5 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 64 Index: test/MC/AArch64/SVE2/fminp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fminp-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +fminp z0.h, p0/m, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: fminp z0.h, p0/m, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +fminp z0.b, p0/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.b, p0/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +fminp z0.h, p0/m, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.h, p0/m, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fminp z0.h, p0/m, z0.h, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fminp z0.h, p0/m, z0.h, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fminp z0.h, p8/m, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: fminp z0.h, p8/m, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fminp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fminp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +fminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x57,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 57 64 + +fminp z29.s, p3/m, z29.s, z30.s +// CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x8f,0x97,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 8f 97 64 + +fminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +fminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d7 64 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +fminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 64 Index: test/MC/AArch64/SVE2/fmlalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlalb-diagnostics.s @@ -0,0 +1,56 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmlalb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmlalb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +fmlalb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmlalb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z29.s, p0/z, z7.s +fmlalb z29.s, z30.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlalb z29.s, z30.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +fmlalb z0.s, z1.h, z7.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmlalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlalb.s @@ -0,0 +1,54 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fmlalb z29.s, z30.h, z31.h +// CHECK-INST: fmlalb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 83 bf 64 + +fmlalb z0.s, z1.h, z7.h[0] +// CHECK-INST: fmlalb z0.s, z1.h, z7.h[0] +// CHECK-ENCODING: [0x20,0x40,0xa7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 a7 64 + +fmlalb z30.s, z31.h, z7.h[7] +// CHECK-INST: fmlalb z30.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe 4b bf 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z29, z28 +// CHECK-INST: movprfx z29, z28 +// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 9d bf 20 04 + +fmlalb z29.s, z30.h, z31.h +// CHECK-INST: fmlalb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 83 bf 64 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +fmlalb z21.s, z1.h, z7.h[7] +// CHECK-INST: fmlalb z21.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x35,0x48,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 48 bf 64 Index: test/MC/AArch64/SVE2/fmlalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlalt-diagnostics.s @@ -0,0 +1,56 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmlalt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmlalt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +fmlalt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmlalt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlalt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z29.s, p0/z, z7.s +fmlalt z29.s, z30.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlalt z29.s, z30.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +fmlalt z0.s, z1.h, z7.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmlalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlalt.s @@ -0,0 +1,54 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fmlalt z29.s, z30.h, z31.h +// CHECK-INST: fmlalt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 87 bf 64 + +fmlalt z0.s, z1.h, z7.h[0] +// CHECK-INST: fmlalt z0.s, z1.h, z7.h[0] +// CHECK-ENCODING: [0x20,0x44,0xa7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 44 a7 64 + +fmlalt z30.s, z31.h, z7.h[7] +// CHECK-INST: fmlalt z30.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe 4f bf 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z29, z28 +// CHECK-INST: movprfx z29, z28 +// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 9d bf 20 04 + +fmlalt z29.s, z30.h, z31.h +// CHECK-INST: fmlalt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 87 bf 64 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +fmlalt z21.s, z1.h, z7.h[7] +// CHECK-INST: fmlalt z21.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x35,0x4c,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 4c bf 64 Index: test/MC/AArch64/SVE2/fmlslb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlslb-diagnostics.s @@ -0,0 +1,56 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmlslb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmlslb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +fmlslb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmlslb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z29.s, p0/z, z7.s +fmlslb z29.s, z30.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlslb z29.s, z30.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +fmlslb z0.s, z1.h, z7.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmlslb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlslb.s @@ -0,0 +1,54 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fmlslb z29.s, z30.h, z31.h +// CHECK-INST: fmlslb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a3 bf 64 + +fmlslb z0.s, z1.h, z7.h[0] +// CHECK-INST: fmlslb z0.s, z1.h, z7.h[0] +// CHECK-ENCODING: [0x20,0x60,0xa7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 a7 64 + +fmlslb z30.s, z31.h, z7.h[7] +// CHECK-INST: fmlslb z30.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe 6b bf 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z29, z28 +// CHECK-INST: movprfx z29, z28 +// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 9d bf 20 04 + +fmlslb z29.s, z30.h, z31.h +// CHECK-INST: fmlslb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a3 bf 64 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +fmlslb z21.s, z1.h, z7.h[7] +// CHECK-INST: fmlslb z21.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x35,0x68,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 68 bf 64 Index: test/MC/AArch64/SVE2/fmlslt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlslt-diagnostics.s @@ -0,0 +1,56 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +fmlslt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fmlslt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +fmlslt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +fmlslt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fmlslt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z29.s, p0/z, z7.s +fmlslt z29.s, z30.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlslt z29.s, z30.h, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +fmlslt z0.s, z1.h, z7.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/fmlslt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/fmlslt.s @@ -0,0 +1,54 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +fmlslt z29.s, z30.h, z31.h +// CHECK-INST: fmlslt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a7 bf 64 + +fmlslt z0.s, z1.h, z7.h[0] +// CHECK-INST: fmlslt z0.s, z1.h, z7.h[0] +// CHECK-ENCODING: [0x20,0x64,0xa7,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 a7 64 + +fmlslt z30.s, z31.h, z7.h[7] +// CHECK-INST: fmlslt z30.s, z31.h, z7.h[7] +// CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe 6f bf 64 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z29, z28 +// CHECK-INST: movprfx z29, z28 +// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 9d bf 20 04 + +fmlslt z29.s, z30.h, z31.h +// CHECK-INST: fmlslt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a7 bf 64 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +fmlslt z21.s, z1.h, z7.h[7] +// CHECK-INST: fmlslt z21.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x35,0x6c,0xbf,0x64] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 6c bf 64 Index: test/MC/AArch64/SVE2/histcnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/histcnt-diagnostics.s @@ -0,0 +1,49 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +histcnt z0.b, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: histcnt z0.b, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +histcnt z0.h, p0/z, z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: histcnt z0.h, p0/z, z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +histcnt z0.s, p0/m, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: histcnt z0.s, p0/m, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +histcnt z0.s, p8/z, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: histcnt z0.s, p8/z, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +histcnt z0.s, p7/z, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +histcnt z0.s, p7/z, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: histcnt z0.s, p7/z, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/histcnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/histcnt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +histcnt z0.s, p0/z, z1.s, z2.s +// CHECK-INST: histcnt z0.s, p0/z, z1.s, z2.s +// CHECK-ENCODING: [0x20,0xc0,0xa2,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 a2 45 + +histcnt z29.d, p7/z, z30.d, z31.d +// CHECK-INST: histcnt z29.d, p7/z, z30.d, z31.d +// CHECK-ENCODING: [0xdd,0xdf,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd df ff 45 Index: test/MC/AArch64/SVE2/histseg-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/histseg-diagnostics.s @@ -0,0 +1,36 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +histseg z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: histseg z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +histseg z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: histseg z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +histseg z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: histseg z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +histseg z31.b, z30.b, z29.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: histseg z31.b, z30.b, z29.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/m, z6.b +histseg z31.b, z30.b, z29.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: histseg z31.b, z30.b, z29.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/histseg.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/histseg.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +histseg z0.b, z1.b, z31.b +// CHECK-INST: histseg z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xa0,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 3f 45 Index: test/MC/AArch64/SVE2/ldnt1b-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1b-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1b { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1b { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1b { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1b { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1b { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1b { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1b { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1b { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1b { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1b { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1b { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1b { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1b.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1b.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1b z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 84 + +ldnt1b z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 84 + +ldnt1b z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 84 + +ldnt1b z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c4 + +ldnt1b z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c4 + +ldnt1b z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c4 + +ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 84 + +ldnt1b { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 84 + +ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 84 + +ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c4 + +ldnt1b { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c4 + +ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c4 Index: test/MC/AArch64/SVE2/ldnt1d-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1d-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1d { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.s }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.s }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1d { z0.d }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1d { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1d { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1d { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1d { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1d { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1d { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1d { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1d { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1d.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1d.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1d z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c5 + +ldnt1d z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c5 + +ldnt1d z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c5 + +ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c5 + +ldnt1d { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c5 + +ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c5 Index: test/MC/AArch64/SVE2/ldnt1h-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1h-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1h { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1h { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1h { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1h { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1h { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1h { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1h { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1h { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1h { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1h { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1h { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1h { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1h.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1h.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1h z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 9f 84 + +ldnt1h z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 9f 84 + +ldnt1h z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 80 84 + +ldnt1h z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c4 + +ldnt1h z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c4 + +ldnt1h z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c4 + +ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 9f 84 + +ldnt1h { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 9f 84 + +ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 80 84 + +ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f c4 + +ldnt1h { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 9f c4 + +ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 80 c4 Index: test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sb-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sb { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sb { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sb { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sb { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sb { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sb { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sb { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sb { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sb { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sb { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sb { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sb { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sb { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sb.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sb z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f 84 + +ldnt1sb z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f 84 + +ldnt1sb z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 84 + +ldnt1sb z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c4 + +ldnt1sb z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c4 + +ldnt1sb z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c4 + +ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f 84 + +ldnt1sb { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f 84 + +ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 84 + +ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c4 + +ldnt1sb { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c4 + +ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c4 Index: test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sh-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sh { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sh { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sh { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sh { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sh { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sh { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sh { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sh { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sh { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sh { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sh { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sh { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sh { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sh.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sh z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f 84 + +ldnt1sh z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f 84 + +ldnt1sh z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 84 + +ldnt1sh z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f c4 + +ldnt1sh z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f c4 + +ldnt1sh z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 c4 + +ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0x80,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f 84 + +ldnt1sh { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f 84 + +ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0x84] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 84 + +ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f c4 + +ldnt1sh { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 9f c4 + +ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x80,0xc4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 80 c4 Index: test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sw-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1sw { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.s }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.s }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1sw { z0.d }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1sw { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1sw { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1sw { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1sw { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1sw { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1sw { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1sw { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1sw { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1sw.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1sw.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1sw z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c5 + +ldnt1sw z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c5 + +ldnt1sw z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c5 + +ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0x80,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f c5 + +ldnt1sw { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 1f c5 + +ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x9f,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 9f 00 c5 Index: test/MC/AArch64/SVE2/ldnt1w-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1w-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +ldnt1w { z0.b }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.b }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.h }, p0/z, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.h }, p0/z, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +ldnt1w { z0.s }, p0/z, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.d }, p0/z, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +ldnt1w { z0.d }, p0/z, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldnt1w { z27.d }, p8/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldnt1w { z27.d }, p8/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +ldnt1w { }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: ldnt1w { }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { z0.d, z1.d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { z0.d, z1.d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldnt1w { v0.2d }, p0/z, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ldnt1w { v0.2d }, p0/z, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ldnt1w { z0.d }, p0/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.d }, p0/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +ldnt1w { z0.s }, p0/z, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ldnt1w { z0.s }, p0/z, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ldnt1w.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ldnt1w.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldnt1w z0.s, p0/z, [z1.s] +// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 85 + +ldnt1w z31.s, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 85 + +ldnt1w z31.s, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 85 + +ldnt1w z0.d, p0/z, [z1.d] +// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c5 + +ldnt1w z31.d, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c5 + +ldnt1w z31.d, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c5 + +ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s] +// CHECK-ENCODING: [0x20,0xa0,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 1f 85 + +ldnt1w { z31.s }, p7/z, [z31.s, xzr] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s] +// CHECK-ENCODING: [0xff,0xbf,0x1f,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 1f 85 + +ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0] +// CHECK-ENCODING: [0xff,0xbf,0x00,0x85] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 00 85 + +ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d] +// CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 1f c5 + +ldnt1w { z31.d }, p7/z, [z31.d, xzr] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d] +// CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 1f c5 + +ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0] +// CHECK-ENCODING: [0xff,0xdf,0x00,0xc5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 00 c5 Index: test/MC/AArch64/SVE2/match-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/match-diagnostics.s @@ -0,0 +1,61 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Restricted predicate out of range. + +match p0.b, p8/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: match p0.b, p8/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +match p0.b, p0/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: match p0.b, p0/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid destination predicate register + +match p0.s, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: match p0.s, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +match p0.d, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: match p0.d, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +match p0.b, p0/z, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: match p0.b, p0/z, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +match p0.b, p0/z, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: match p0.b, p0/z, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +match p0.b, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: match p0.b, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +match p0.b, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: match p0.b, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/match.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/match.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +match p0.b, p0/z, z0.b, z0.b +// CHECK-INST: match p0.b, p0/z, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x80,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 20 45 + +match p0.h, p0/z, z0.h, z0.h +// CHECK-INST: match p0.h, p0/z, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x80,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 60 45 + +match p15.b, p7/z, z30.b, z31.b +// CHECK-INST: match p15.b, p7/z, z30.b, z31.b +// CHECK-ENCODING: [0xcf,0x9f,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 9f 3f 45 + +match p15.h, p7/z, z30.h, z31.h +// CHECK-INST: match p15.h, p7/z, z30.h, z31.h +// CHECK-ENCODING: [0xcf,0x9f,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 9f 7f 45 Index: test/MC/AArch64/SVE2/mla-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mla-diagnostics.s @@ -0,0 +1,64 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mla z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: mla z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: mla z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: mla z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mla z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mla z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mla z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mla z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mla z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mla z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mla z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mla z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mla z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mla z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mla.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mla.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mla z0.h, z1.h, z7.h[7] +// CHECK-INST: mla z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x08,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 7f 44 + +mla z0.s, z1.s, z7.s[3] +// CHECK-INST: mla z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x08,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 bf 44 + +mla z0.d, z1.d, z7.d[1] +// CHECK-INST: mla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 f7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +mla z0.d, z1.d, z7.d[1] +// CHECK-INST: mla z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x08,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 f7 44 Index: test/MC/AArch64/SVE2/mls-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mls-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mls z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h +// CHECK-NEXT: mls z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s +// CHECK-NEXT: mls z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: mls z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mls z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mls z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mls z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mls z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mls z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mls z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mls z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mls z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mls z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: mls z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mls.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mls.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mls z0.h, z1.h, z7.h[7] +// CHECK-INST: mls z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x0c,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c 7f 44 + +mls z0.s, z1.s, z7.s[3] +// CHECK-INST: mls z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x0c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c bf 44 + +mls z0.d, z1.d, z7.d[1] +// CHECK-INST: mls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c f7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +mls z0.d, z1.d, z7.d[1] +// CHECK-INST: mls z0.d, z1.d, z7.d[1] +// CHECK-ENCODING: [0x20,0x0c,0xf7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c f7 44 Index: test/MC/AArch64/SVE2/mul-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mul-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +mul z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: mul z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +mul z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mul z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: mul z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mul z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: mul z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mul z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: mul z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +mul z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +mul z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: mul z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +mul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +mul z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +mul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +mul z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: mul z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/mul.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/mul.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mul z0.b, z1.b, z2.b +// CHECK-INST: mul z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x60,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 22 04 + +mul z0.h, z1.h, z2.h +// CHECK-INST: mul z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x60,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 62 04 + +mul z29.s, z30.s, z31.s +// CHECK-INST: mul z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x63,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 63 bf 04 + +mul z31.d, z31.d, z31.d +// CHECK-INST: mul z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x63,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 63 ff 04 + +mul z0.h, z1.h, z7.h[7] +// CHECK-INST: mul z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf8,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 7f 44 + +mul z0.s, z1.s, z7.s[3] +// CHECK-INST: mul z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 bf 44 + +mul z0.d, z1.d, z15.d[1] +// CHECK-INST: mul z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf8,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 ff 44 Index: test/MC/AArch64/SVE2/nbsl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/nbsl-diagnostics.s @@ -0,0 +1,39 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +nbsl z0.b, z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: nbsl z0.b, z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +nbsl z0.h, z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: nbsl z0.h, z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +nbsl z0.s, z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: nbsl z0.s, z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +nbsl z0.d, z1.d, z2.d, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: nbsl z0.d, z1.d, z2.d, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +nbsl z0.d, z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/nbsl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/nbsl.s @@ -0,0 +1,30 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +nbsl z0.d, z0.d, z1.d, z2.d +// CHECK-INST: nbsl z0.d, z0.d, z1.d, z2.d +// CHECK-ENCODING: [0x40,0x3c,0xe1,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 40 3c e1 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +nbsl z31.d, z31.d, z30.d, z29.d +// CHECK-INST: nbsl z31.d, z31.d, z30.d, z29.d +// CHECK-ENCODING: [0xbf,0x3f,0xfe,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bf 3f fe 04 Index: test/MC/AArch64/SVE2/nmatch-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/nmatch-diagnostics.s @@ -0,0 +1,61 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Restricted predicate out of range. + +nmatch p0.b, p8/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: nmatch p0.b, p8/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +nmatch p0.b, p0/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: nmatch p0.b, p0/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid destination predicate register + +nmatch p0.s, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: nmatch p0.s, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +nmatch p0.d, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: nmatch p0.d, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +nmatch p0.b, p0/z, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: nmatch p0.b, p0/z, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +nmatch p0.b, p0/z, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: nmatch p0.b, p0/z, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +nmatch p0.b, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +nmatch p0.b, p0/z, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: nmatch p0.b, p0/z, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/nmatch.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/nmatch.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +nmatch p0.b, p0/z, z0.b, z0.b +// CHECK-INST: nmatch p0.b, p0/z, z0.b, z0.b +// CHECK-ENCODING: [0x10,0x80,0x20,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 10 80 20 45 + +nmatch p0.h, p0/z, z0.h, z0.h +// CHECK-INST: nmatch p0.h, p0/z, z0.h, z0.h +// CHECK-ENCODING: [0x10,0x80,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 10 80 60 45 + +nmatch p15.b, p7/z, z30.b, z31.b +// CHECK-INST: nmatch p15.b, p7/z, z30.b, z31.b +// CHECK-ENCODING: [0xdf,0x9f,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f 3f 45 + +nmatch p15.h, p7/z, z30.h, z31.h +// CHECK-INST: nmatch p15.h, p7/z, z30.h, z31.h +// CHECK-ENCODING: [0xdf,0x9f,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f 7f 45 Index: test/MC/AArch64/SVE2/pmul-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmul-diagnostics.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmul z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmul z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmul z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmul z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +pmul z0.b, z1.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmul z0.b, z1.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +pmul z0.b, z1.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmul z0.b, z1.b, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmul.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmul.s @@ -0,0 +1,20 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +pmul z0.b, z1.b, z2.b +// CHECK-INST: pmul z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x64,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 22 04 + +pmul z29.b, z30.b, z31.b +// CHECK-INST: pmul z29.b, z30.b, z31.b +// CHECK-ENCODING: [0xdd,0x67,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 67 3f 04 Index: test/MC/AArch64/SVE2/pmullb-128-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullb-128-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmullb z0.q, z0.q, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullb z0.q, z0.q, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +pmullb z0.q, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullb z0.q, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +pmullb z0.q, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullb z0.q, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmullb-128.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullb-128.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +pmullb z29.q, z30.d, z31.d +// CHECK-INST: pmullb z29.q, z30.d, z31.d +// CHECK-ENCODING: [0xdd,0x6b,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: dd 6b 1f 45 Index: test/MC/AArch64/SVE2/pmullb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullb-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullb z0.q, z0.q, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: pmullb z0.q, z0.q, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +pmullb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +pmullb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmullb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullb.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +pmullb z0.h, z1.b, z2.b +// CHECK-INST: pmullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x68,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 42 45 + +pmullb z31.d, z31.s, z31.s +// CHECK-INST: pmullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x6b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6b df 45 Index: test/MC/AArch64/SVE2/pmullt-128-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullt-128-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmullt z0.q, z0.q, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullt z0.q, z0.q, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +pmullt z0.q, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullt z0.q, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +pmullt z0.q, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullt z0.q, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmullt-128.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullt-128.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +pmullt z29.q, z30.d, z31.d +// CHECK-INST: pmullt z29.q, z30.d, z31.d +// CHECK-ENCODING: [0xdd,0x6f,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2-aes +// CHECK-UNKNOWN: dd 6f 1f 45 Index: test/MC/AArch64/SVE2/pmullt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullt-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +pmullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: pmullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +pmullt z0.q, z0.q, z0.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: pmullt z0.q, z0.q, z0.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +pmullt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +pmullt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: pmullt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/pmullt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/pmullt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +pmullt z0.h, z1.b, z2.b +// CHECK-INST: pmullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x6c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 42 45 + +pmullt z31.d, z31.s, z31.s +// CHECK-INST: pmullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x6f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6f df 45 Index: test/MC/AArch64/SVE2/raddhnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/raddhnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +raddhnb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +raddhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: raddhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +raddhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: raddhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/raddhnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/raddhnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +raddhnb z0.b, z1.h, z31.h +// CHECK-INST: raddhnb z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x68,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 7f 45 + +raddhnb z0.h, z1.s, z31.s +// CHECK-INST: raddhnb z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x68,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 bf 45 + +raddhnb z0.s, z1.d, z31.d +// CHECK-INST: raddhnb z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x68,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 ff 45 Index: test/MC/AArch64/SVE2/raddhnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/raddhnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +raddhnt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +raddhnt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: raddhnt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +raddhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: raddhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +raddhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: raddhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/raddhnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/raddhnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +raddhnt z0.b, z1.h, z31.h +// CHECK-INST: raddhnt z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x6c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 7f 45 + +raddhnt z0.h, z1.s, z31.s +// CHECK-INST: raddhnt z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x6c,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c bf 45 + +raddhnt z0.s, z1.d, z31.d +// CHECK-INST: raddhnt z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x6c,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c ff 45 Index: test/MC/AArch64/SVE2/rax1-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rax1-diagnostics.s @@ -0,0 +1,36 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sha3 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +rax1 z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rax1 z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rax1 z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rax1 z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rax1 z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rax1 z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +rax1 z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rax1 z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +rax1 z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rax1 z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/rax1.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rax1.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sha3 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-sha3 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sha3 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +rax1 z0.d, z1.d, z31.d +// CHECK-INST: rax1 z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xf4,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2-sha3 +// CHECK-UNKNOWN: 20 f4 3f 45 Index: test/MC/AArch64/SVE2/rshrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rshrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +rshrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: rshrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: rshrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: rshrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: rshrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: rshrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: rshrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +rshrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +rshrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rshrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/rshrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rshrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +rshrnb z0.b, z0.h, #1 +// CHECK-INST: rshrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x18,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 18 2f 45 + +rshrnb z31.b, z31.h, #8 +// CHECK-INST: rshrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x1b,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b 28 45 + +rshrnb z0.h, z0.s, #1 +// CHECK-INST: rshrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x18,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 18 3f 45 + +rshrnb z31.h, z31.s, #16 +// CHECK-INST: rshrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x1b,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b 30 45 + +rshrnb z0.s, z0.d, #1 +// CHECK-INST: rshrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x18,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 18 7f 45 + +rshrnb z31.s, z31.d, #32 +// CHECK-INST: rshrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x1b,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b 60 45 Index: test/MC/AArch64/SVE2/rshrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rshrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +rshrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: rshrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: rshrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: rshrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: rshrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: rshrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: rshrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +rshrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rshrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rshrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +rshrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rshrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/rshrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rshrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +rshrnt z0.b, z0.h, #1 +// CHECK-INST: rshrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x1c,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 1c 2f 45 + +rshrnt z31.b, z31.h, #8 +// CHECK-INST: rshrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x1f,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1f 28 45 + +rshrnt z0.h, z0.s, #1 +// CHECK-INST: rshrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x1c,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 1c 3f 45 + +rshrnt z31.h, z31.s, #16 +// CHECK-INST: rshrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x1f,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1f 30 45 + +rshrnt z0.s, z0.d, #1 +// CHECK-INST: rshrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x1c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 1c 7f 45 + +rshrnt z31.s, z31.d, #32 +// CHECK-INST: rshrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x1f,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1f 60 45 Index: test/MC/AArch64/SVE2/rsubhnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rsubhnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +rsubhnb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +rsubhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rsubhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +rsubhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rsubhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/rsubhnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rsubhnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +rsubhnb z0.b, z1.h, z31.h +// CHECK-INST: rsubhnb z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x78,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 78 7f 45 + +rsubhnb z0.h, z1.s, z31.s +// CHECK-INST: rsubhnb z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x78,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 78 bf 45 + +rsubhnb z0.s, z1.d, z31.d +// CHECK-INST: rsubhnb z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x78,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 78 ff 45 Index: test/MC/AArch64/SVE2/rsubhnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rsubhnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +rsubhnt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +rsubhnt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: rsubhnt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +rsubhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rsubhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +rsubhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: rsubhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/rsubhnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/rsubhnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +rsubhnt z0.b, z1.h, z31.h +// CHECK-INST: rsubhnt z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x7c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 7c 7f 45 + +rsubhnt z0.h, z1.s, z31.s +// CHECK-INST: rsubhnt z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x7c,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 7c bf 45 + +rsubhnt z0.s, z1.d, z31.d +// CHECK-INST: rsubhnt z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x7c,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 7c ff 45 Index: test/MC/AArch64/SVE2/saba-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saba-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saba z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saba z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +saba z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: saba z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saba.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saba.s @@ -0,0 +1,48 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +saba z0.b, z1.b, z31.b +// CHECK-INST: saba z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xf8,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 1f 45 + +saba z0.h, z1.h, z31.h +// CHECK-INST: saba z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xf8,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 5f 45 + +saba z0.s, z1.s, z31.s +// CHECK-INST: saba z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xf8,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 9f 45 + +saba z0.d, z1.d, z31.d +// CHECK-INST: saba z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +saba z0.d, z1.d, z31.d +// CHECK-INST: saba z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f8 df 45 Index: test/MC/AArch64/SVE2/sabalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabalb-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sabalb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sabalb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sabalb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sabalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabalb.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sabalb z0.h, z1.b, z31.b +// CHECK-INST: sabalb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xc0,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 5f 45 + +sabalb z0.s, z1.h, z31.h +// CHECK-INST: sabalb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xc0,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 9f 45 + +sabalb z0.d, z1.s, z31.s +// CHECK-INST: sabalb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xc0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c0 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sabalb z21.d, z1.s, z31.s +// CHECK-INST: sabalb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0xc0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 c0 df 45 Index: test/MC/AArch64/SVE2/sabalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabalt-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sabalt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabalt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabalt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sabalt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sabalt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sabalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabalt.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sabalt z0.h, z1.b, z31.b +// CHECK-INST: sabalt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xc4,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c4 5f 45 + +sabalt z0.s, z1.h, z31.h +// CHECK-INST: sabalt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xc4,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c4 9f 45 + +sabalt z0.d, z1.s, z31.s +// CHECK-INST: sabalt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xc4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c4 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sabalt z21.d, z1.s, z31.s +// CHECK-INST: sabalt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0xc4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 c4 df 45 Index: test/MC/AArch64/SVE2/sabdlb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabdlb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sabdlb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sabdlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sabdlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sabdlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sabdlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sabdlb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabdlb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sabdlb z0.h, z1.b, z2.b +// CHECK-INST: sabdlb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x30,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 30 42 45 + +sabdlb z29.s, z30.h, z31.h +// CHECK-INST: sabdlb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x33,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 33 9f 45 + +sabdlb z31.d, z31.s, z31.s +// CHECK-INST: sabdlb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x33,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 33 df 45 Index: test/MC/AArch64/SVE2/sabdlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabdlt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sabdlt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sabdlt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sabdlt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sabdlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sabdlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sabdlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sabdlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sabdlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sabdlt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sabdlt z0.h, z1.b, z2.b +// CHECK-INST: sabdlt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x34,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 34 42 45 + +sabdlt z29.s, z30.h, z31.h +// CHECK-INST: sabdlt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x37,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 37 9f 45 + +sabdlt z31.d, z31.s, z31.s +// CHECK-INST: sabdlt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x37,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 37 df 45 Index: test/MC/AArch64/SVE2/sadalp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sadalp-diagnostics.s @@ -0,0 +1,42 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sadalp z0.b, p0/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sadalp z0.b, p0/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sadalp z0.h, p0/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sadalp z0.h, p0/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sadalp z0.s, p0/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sadalp z0.s, p0/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sadalp z0.d, p0/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sadalp z0.d, p0/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sadalp z0.h, p8/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sadalp z0.h, p8/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative movprfx tests + +movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination. +sadalp z31.d, p0/m, z30.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: sadalp z31.d, p0/m, z30.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sadalp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sadalp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sadalp z0.h, p0/m, z1.b +// CHECK-INST: sadalp z0.h, p0/m, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x44,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 44 44 + +sadalp z29.s, p0/m, z30.h +// CHECK-INST: sadalp z29.s, p0/m, z30.h +// CHECK-ENCODING: [0xdd,0xa3,0x84,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a3 84 44 + +sadalp z30.d, p7/m, z31.s +// CHECK-INST: sadalp z30.d, p7/m, z31.s +// CHECK-ENCODING: [0xfe,0xbf,0xc4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf c4 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sadalp z31.d, p0/m, z30.s +// CHECK-INST: sadalp z31.d, p0/m, z30.s +// CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 c4 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sadalp z31.d, p0/m, z30.s +// CHECK-INST: sadalp z31.d, p0/m, z30.s +// CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 c4 44 Index: test/MC/AArch64/SVE2/saddlb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saddlb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +saddlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saddlb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +saddlb z0.h, z1.b, z2.b +// CHECK-INST: saddlb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x00,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 00 42 45 + +saddlb z29.s, z30.h, z31.h +// CHECK-INST: saddlb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x03,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 03 9f 45 + +saddlb z31.d, z31.s, z31.s +// CHECK-INST: saddlb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x03,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 df 45 Index: test/MC/AArch64/SVE2/saddlbt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlbt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saddlbt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlbt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlbt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlbt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlbt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlbt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlbt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlbt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +saddlbt z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlbt z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +saddlbt z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlbt z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saddlbt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlbt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +saddlbt z0.h, z1.b, z31.b +// CHECK-INST: saddlbt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x80,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5f 45 + +saddlbt z0.s, z1.h, z31.h +// CHECK-INST: saddlbt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x80,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 9f 45 + +saddlbt z0.d, z1.s, z31.s +// CHECK-INST: saddlbt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x80,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 df 45 Index: test/MC/AArch64/SVE2/saddlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saddlt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddlt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddlt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +saddlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saddlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddlt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +saddlt z0.h, z1.b, z2.b +// CHECK-INST: saddlt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x04,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 04 42 45 + +saddlt z29.s, z30.h, z31.h +// CHECK-INST: saddlt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x07,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 07 9f 45 + +saddlt z31.d, z31.s, z31.s +// CHECK-INST: saddlt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x07,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 07 df 45 Index: test/MC/AArch64/SVE2/saddwb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddwb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saddwb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +saddwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saddwb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddwb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +saddwb z0.h, z1.h, z2.b +// CHECK-INST: saddwb z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x40,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 42 45 + +saddwb z29.s, z30.s, z31.h +// CHECK-INST: saddwb z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x43,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 43 9f 45 + +saddwb z31.d, z31.d, z31.s +// CHECK-INST: saddwb z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x43,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 43 df 45 Index: test/MC/AArch64/SVE2/saddwt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddwt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +saddwt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +saddwt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: saddwt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +saddwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +saddwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: saddwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/saddwt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/saddwt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +saddwt z0.h, z1.h, z2.b +// CHECK-INST: saddwt z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x44,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 44 42 45 + +saddwt z29.s, z30.s, z31.h +// CHECK-INST: saddwt z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x47,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 47 9f 45 + +saddwt z31.d, z31.d, z31.s +// CHECK-INST: saddwt z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x47,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 47 df 45 Index: test/MC/AArch64/SVE2/sbclb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sbclb-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sbclb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sbclb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sbclb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sbclb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sbclb z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sbclb z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sbclb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sbclb.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sbclb z0.s, z1.s, z31.s +// CHECK-INST: sbclb z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xd0,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 9f 45 + +sbclb z0.d, z1.d, z31.d +// CHECK-INST: sbclb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sbclb z0.d, z1.d, z31.d +// CHECK-INST: sbclb z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d0 df 45 Index: test/MC/AArch64/SVE2/sbclt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sbclt-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sbclt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sbclt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sbclt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sbclt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sbclt z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sbclt z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sbclt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sbclt.s @@ -0,0 +1,36 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sbclt z0.s, z1.s, z31.s +// CHECK-INST: sbclt z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xd4,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 9f 45 + +sbclt z0.d, z1.d, z31.d +// CHECK-INST: sbclt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sbclt z0.d, z1.d, z31.d +// CHECK-INST: sbclt z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d4 df 45 Index: test/MC/AArch64/SVE2/shadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +shadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/shadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x10,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 10 44 + +shadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x50,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 50 44 + +shadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x90,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 90 44 + +shadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d0 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d0 44 Index: test/MC/AArch64/SVE2/shrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +shrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: shrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: shrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: shrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: shrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: shrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: shrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +shrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +shrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: shrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/shrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shrnb z0.b, z0.h, #1 +// CHECK-INST: shrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x10,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 10 2f 45 + +shrnb z31.b, z31.h, #8 +// CHECK-INST: shrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x13,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 28 45 + +shrnb z0.h, z0.s, #1 +// CHECK-INST: shrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x10,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 10 3f 45 + +shrnb z31.h, z31.s, #16 +// CHECK-INST: shrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x13,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 30 45 + +shrnb z0.s, z0.d, #1 +// CHECK-INST: shrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x10,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 10 7f 45 + +shrnb z31.s, z31.d, #32 +// CHECK-INST: shrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x13,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 60 45 Index: test/MC/AArch64/SVE2/shrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +shrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: shrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: shrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: shrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: shrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: shrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: shrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +shrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +shrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: shrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/shrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shrnt z0.b, z0.h, #1 +// CHECK-INST: shrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x14,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 14 2f 45 + +shrnt z31.b, z31.h, #8 +// CHECK-INST: shrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x17,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 17 28 45 + +shrnt z0.h, z0.s, #1 +// CHECK-INST: shrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x14,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 14 3f 45 + +shrnt z31.h, z31.s, #16 +// CHECK-INST: shrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x17,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 17 30 45 + +shrnt z0.s, z0.d, #1 +// CHECK-INST: shrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x14,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 14 7f 45 + +shrnt z31.s, z31.d, #32 +// CHECK-INST: shrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x17,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 17 60 45 Index: test/MC/AArch64/SVE2/shsub-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shsub-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +shsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/shsub.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x12,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 12 44 + +shsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x52,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 52 44 + +shsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x92,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 92 44 + +shsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d2 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d2 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d2 44 Index: test/MC/AArch64/SVE2/shsubr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shsubr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +shsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: shsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +shsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +shsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: shsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +shsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: shsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/shsubr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/shsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +shsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x16,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 16 44 + +shsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x56,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 56 44 + +shsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x96,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 96 44 + +shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +shsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d6 44 Index: test/MC/AArch64/SVE2/sli-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sli-diagnostics.s @@ -0,0 +1,59 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sli z18.b, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sli z18.b, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z1.b, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sli z1.b, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z21.h, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sli z21.h, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z14.h, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sli z14.h, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z6.s, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sli z6.s, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z23.s, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sli z23.s, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z3.d, z24.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sli z3.d, z24.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sli z25.d, z16.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sli z25.d, z16.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sli z0.b, z0.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sli z0.b, z0.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sli z31.d, z31.d, #63 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sli z31.d, z31.d, #63 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sli.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sli.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sli z0.b, z0.b, #0 +// CHECK-INST: sli z0.b, z0.b, #0 +// CHECK-ENCODING: [0x00,0xf4,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f4 08 45 + +sli z31.b, z31.b, #7 +// CHECK-INST: sli z31.b, z31.b, #7 +// CHECK-ENCODING: [0xff,0xf7,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f7 0f 45 + +sli z0.h, z0.h, #0 +// CHECK-INST: sli z0.h, z0.h, #0 +// CHECK-ENCODING: [0x00,0xf4,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f4 10 45 + +sli z31.h, z31.h, #15 +// CHECK-INST: sli z31.h, z31.h, #15 +// CHECK-ENCODING: [0xff,0xf7,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f7 1f 45 + +sli z0.s, z0.s, #0 +// CHECK-INST: sli z0.s, z0.s, #0 +// CHECK-ENCODING: [0x00,0xf4,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f4 40 45 + +sli z31.s, z31.s, #31 +// CHECK-INST: sli z31.s, z31.s, #31 +// CHECK-ENCODING: [0xff,0xf7,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f7 5f 45 + +sli z0.d, z0.d, #0 +// CHECK-INST: sli z0.d, z0.d, #0 +// CHECK-ENCODING: [0x00,0xf4,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f4 80 45 + +sli z31.d, z31.d, #63 +// CHECK-INST: sli z31.d, z31.d, #63 +// CHECK-ENCODING: [0xff,0xf7,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f7 df 45 Index: test/MC/AArch64/SVE2/sm4e-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sm4e-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sm4e z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sm4e z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sm4e z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4e z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sm4e z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4e z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sm4e z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4e z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sm4e z0.s, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sm4e z0.s, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sm4e z0.s, z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sm4e z0.s, z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sm4e.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sm4e.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sm4e z0.s, z0.s, z31.s +// CHECK-INST: sm4e z0.s, z0.s, z31.s +// CHECK-ENCODING: [0xe0,0xe3,0x23,0x45] +// CHECK-ERROR: instruction requires: sve2-sm4 +// CHECK-UNKNOWN: e0 e3 23 45 Index: test/MC/AArch64/SVE2/sm4ekey-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sm4ekey-diagnostics.s @@ -0,0 +1,36 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid element width + +sm4ekey z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4ekey z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sm4ekey z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4ekey z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sm4ekey z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sm4ekey z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/z, z7.s +sm4ekey z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sm4ekey z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +sm4ekey z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sm4ekey z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sm4ekey.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sm4ekey.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-sm4 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2-sm4 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-sm4 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sm4ekey z0.s, z1.s, z31.s +// CHECK-INST: sm4ekey z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xf0,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2-sm4 +// CHECK-UNKNOWN: 20 f0 3f 45 Index: test/MC/AArch64/SVE2/smaxp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smaxp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +smaxp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: smaxp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +smaxp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smaxp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smaxp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smaxp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +smaxp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: smaxp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smaxp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smaxp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +smaxp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x14,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 14 44 + +smaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x54,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 54 44 + +smaxp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x94,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 94 44 + +smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d4 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +smaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d4 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d4 44 Index: test/MC/AArch64/SVE2/sminp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sminp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sminp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sminp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sminp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sminp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sminp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sminp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sminp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sminp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sminp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sminp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sminp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x16,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 16 44 + +sminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x56,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 56 44 + +sminp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x96,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 96 44 + +sminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d6 44 Index: test/MC/AArch64/SVE2/smlalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlalb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smlalb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlalb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlalb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smlalb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlalb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smlalb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smlalb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlalb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +smlalb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlalb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smlalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlalb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smlalb z0.h, z1.b, z31.b +// CHECK-INST: smlalb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x40,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 5f 44 + +smlalb z0.s, z1.h, z31.h +// CHECK-INST: smlalb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x40,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 9f 44 + +smlalb z0.d, z1.s, z31.s +// CHECK-INST: smlalb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x40,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 40 df 44 + +smlalb z0.s, z1.h, z7.h[7] +// CHECK-INST: smlalb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x88,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 88 bf 44 + +smlalb z0.d, z1.s, z15.s[1] +// CHECK-INST: smlalb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0x88,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 88 ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlalb z21.d, z1.s, z31.s +// CHECK-INST: smlalb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x40,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 40 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlalb z21.d, z10.s, z5.s[1] +// CHECK-INST: smlalb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x89,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 89 e5 44 Index: test/MC/AArch64/SVE2/smlalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlalt-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smlalt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlalt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlalt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smlalt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlalt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smlalt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlalt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlalt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smlalt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlalt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +smlalt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlalt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smlalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlalt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smlalt z0.h, z1.b, z31.b +// CHECK-INST: smlalt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x44,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 44 5f 44 + +smlalt z0.s, z1.h, z31.h +// CHECK-INST: smlalt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x44,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 44 9f 44 + +smlalt z0.d, z1.s, z31.s +// CHECK-INST: smlalt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x44,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 44 df 44 + +smlalt z0.s, z1.h, z7.h[7] +// CHECK-INST: smlalt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x8c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 8c bf 44 + +smlalt z0.d, z1.s, z15.s[1] +// CHECK-INST: smlalt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0x8c,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 8c ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlalt z21.d, z1.s, z31.s +// CHECK-INST: smlalt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x44,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 44 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlalt z21.d, z10.s, z5.s[1] +// CHECK-INST: smlalt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x8d,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 8d e5 44 Index: test/MC/AArch64/SVE2/smlslb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlslb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smlslb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlslb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlslb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smlslb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlslb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smlslb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smlslb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlslb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +smlslb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlslb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smlslb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlslb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smlslb z0.h, z1.b, z31.b +// CHECK-INST: smlslb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x50,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 50 5f 44 + +smlslb z0.s, z1.h, z31.h +// CHECK-INST: smlslb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x50,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 50 9f 44 + +smlslb z0.d, z1.s, z31.s +// CHECK-INST: smlslb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x50,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 50 df 44 + +smlslb z0.s, z1.h, z7.h[7] +// CHECK-INST: smlslb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xa8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a8 bf 44 + +smlslb z0.d, z1.s, z15.s[1] +// CHECK-INST: smlslb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xa8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a8 ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlslb z21.d, z1.s, z31.s +// CHECK-INST: smlslb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x50,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 50 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlslb z21.d, z10.s, z5.s[1] +// CHECK-INST: smlslb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0xa9,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 a9 e5 44 Index: test/MC/AArch64/SVE2/smlslt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlslt-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smlslt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlslt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smlslt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smlslt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smlslt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smlslt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smlslt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smlslt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smlslt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlslt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +smlslt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: smlslt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smlslt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smlslt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smlslt z0.h, z1.b, z31.b +// CHECK-INST: smlslt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x54,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 54 5f 44 + +smlslt z0.s, z1.h, z31.h +// CHECK-INST: smlslt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x54,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 54 9f 44 + +smlslt z0.d, z1.s, z31.s +// CHECK-INST: smlslt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x54,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 54 df 44 + +smlslt z0.s, z1.h, z7.h[7] +// CHECK-INST: smlslt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xac,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ac bf 44 + +smlslt z0.d, z1.s, z15.s[1] +// CHECK-INST: smlslt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xac,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ac ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlslt z21.d, z1.s, z31.s +// CHECK-INST: smlslt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x54,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 54 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +smlslt z21.d, z10.s, z5.s[1] +// CHECK-INST: smlslt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0xad,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 ad e5 44 Index: test/MC/AArch64/SVE2/smulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smulh-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +smulh z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smulh z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smulh z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +smulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +smulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smulh.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +smulh z0.b, z1.b, z2.b +// CHECK-INST: smulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x68,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 22 04 + +smulh z0.h, z1.h, z2.h +// CHECK-INST: smulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x68,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 62 04 + +smulh z29.s, z30.s, z31.s +// CHECK-INST: smulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x6b,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 6b bf 04 + +smulh z31.d, z31.d, z31.d +// CHECK-INST: smulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6b,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6b ff 04 Index: test/MC/AArch64/SVE2/smullb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smullb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smullb z0.h, z1.b, z2.b +// CHECK-INST: smullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x70,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 42 45 + +smullb z29.s, z30.h, z31.h +// CHECK-INST: smullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x73,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 73 9f 45 + +smullb z31.d, z31.s, z31.s +// CHECK-INST: smullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x73,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 73 df 45 + +smullb z0.s, z1.h, z7.h[7] +// CHECK-INST: smullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xc8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 bf 44 + +smullb z0.d, z1.s, z15.s[1] +// CHECK-INST: smullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xc8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 ef 44 Index: test/MC/AArch64/SVE2/smullt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +smullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: smullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +smullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: smullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: smullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +smullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +smullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: smullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +smullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +smullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: smullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/smullt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/smullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +smullt z0.h, z1.b, z2.b +// CHECK-INST: smullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x74,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 42 45 + +smullt z29.s, z30.h, z31.h +// CHECK-INST: smullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x77,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 77 9f 45 + +smullt z31.d, z31.s, z31.s +// CHECK-INST: smullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x77,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 77 df 45 + +smullt z0.s, z1.h, z7.h[7] +// CHECK-INST: smullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xcc,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc bf 44 + +smullt z0.d, z1.s, z15.s[1] +// CHECK-INST: smullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xcc,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc ef 44 Index: test/MC/AArch64/SVE2/splice-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/splice-diagnostics.s @@ -0,0 +1,69 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element widths. + +splice z0.b, p0, { z1.h, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: splice z0.b, p0, { z1.h, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +splice z0.b, p0, { } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: splice z0.b, p0, { } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +splice z0.b, p0, { z1.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: splice z0.b, p0, { z1.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +splice z0.b, p0, { z1.b, z2.b, z3.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b, z3.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +splice z0.b, p0, { z1.b, z2.h } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: splice z0.b, p0, { z1.b, z2.h } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +splice z0.b, p0, { z1.b, z31.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +splice z0.b, p0, { v0.4b, v1.4b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: splice z0.b, p0, { v0.4b, v1.4b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +splice z0.b, p8, { z1.b, z2.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7] +// CHECK-NEXT: splice z0.b, p8, { z1.b, z2.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +splice z31.b, p0, { z30.b, z31.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/z, z6.b +splice z31.b, p0, { z30.b, z31.b } +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: splice z31.b, p0, { z30.b, z31.b } +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/splice.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/splice.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +splice z29.b, p7, { z30.b, z31.b } +// CHECK-INST: splice z29.b, p7, { z30.b, z31.b } +// CHECK-ENCODING: [0xdd,0x9f,0x2d,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 2d 05 + +splice z29.h, p7, { z30.h, z31.h } +// CHECK-INST: splice z29.h, p7, { z30.h, z31.h } +// CHECK-ENCODING: [0xdd,0x9f,0x6d,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 6d 05 + +splice z29.s, p7, { z30.s, z31.s } +// CHECK-INST: splice z29.s, p7, { z30.s, z31.s } +// CHECK-ENCODING: [0xdd,0x9f,0xad,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f ad 05 + +splice z29.d, p7, { z30.d, z31.d } +// CHECK-INST: splice z29.d, p7, { z30.d, z31.d } +// CHECK-ENCODING: [0xdd,0x9f,0xed,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f ed 05 Index: test/MC/AArch64/SVE2/sqabs-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqabs-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate + +sqabs z0.s, p8/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqabs z0.s, p8/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqabs z0.b, p7/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqabs z0.b, p7/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqabs.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqabs.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqabs z31.b, p7/m, z31.b +// CHECK-INST: sqabs z31.b, p7/m, z31.b +// CHECK-ENCODING: [0xff,0xbf,0x08,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 08 44 + +sqabs z31.h, p7/m, z31.h +// CHECK-INST: sqabs z31.h, p7/m, z31.h +// CHECK-ENCODING: [0xff,0xbf,0x48,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 48 44 + +sqabs z31.s, p7/m, z31.s +// CHECK-INST: sqabs z31.s, p7/m, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x88,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 88 44 + +sqabs z31.d, p7/m, z31.d +// CHECK-INST: sqabs z31.d, p7/m, z31.d +// CHECK-ENCODING: [0xff,0xbf,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf c8 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.s, p7/z, z6.s +// CHECK-INST: movprfx z4.s, p7/z, z6.s +// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 90 04 + +sqabs z4.s, p7/m, z31.s +// CHECK-INST: sqabs z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 88 44 + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +sqabs z4.s, p7/m, z31.s +// CHECK-INST: sqabs z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 88 44 Index: test/MC/AArch64/SVE2/sqadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x18,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 18 44 + +sqadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x58,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 58 44 + +sqadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x98,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 98 44 + +sqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d8 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d8 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d8 44 Index: test/MC/AArch64/SVE2/sqcadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqcadd-diagnostics.s @@ -0,0 +1,38 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqcadd z0.d, z1.d, z2.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqcadd z0.d, z1.d, z2.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +sqcadd z0.d, z0.d, z1.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqcadd z0.d, z0.d, z1.d, #180 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #180 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqcadd z0.d, z0.d, z1.d, #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270. +// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqcadd z0.d, z0.d, z31.d, #90 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqcadd z0.d, z0.d, z31.d, #90 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqcadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqcadd.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqcadd z0.b, z0.b, z0.b, #90 +// CHECK-INST: sqcadd z0.b, z0.b, z0.b, #90 +// CHECK-ENCODING: [0x00,0xd8,0x01,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 01 45 + +sqcadd z0.h, z0.h, z0.h, #90 +// CHECK-INST: sqcadd z0.h, z0.h, z0.h, #90 +// CHECK-ENCODING: [0x00,0xd8,0x41,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 41 45 + +sqcadd z0.s, z0.s, z0.s, #90 +// CHECK-INST: sqcadd z0.s, z0.s, z0.s, #90 +// CHECK-ENCODING: [0x00,0xd8,0x81,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 81 45 + +sqcadd z0.d, z0.d, z0.d, #90 +// CHECK-INST: sqcadd z0.d, z0.d, z0.d, #90 +// CHECK-ENCODING: [0x00,0xd8,0xc1,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 d8 c1 45 + +sqcadd z31.b, z31.b, z31.b, #270 +// CHECK-INST: sqcadd z31.b, z31.b, z31.b, #270 +// CHECK-ENCODING: [0xff,0xdf,0x01,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 01 45 + +sqcadd z31.h, z31.h, z31.h, #270 +// CHECK-INST: sqcadd z31.h, z31.h, z31.h, #270 +// CHECK-ENCODING: [0xff,0xdf,0x41,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 41 45 + +sqcadd z31.s, z31.s, z31.s, #270 +// CHECK-INST: sqcadd z31.s, z31.s, z31.s, #270 +// CHECK-ENCODING: [0xff,0xdf,0x81,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df 81 45 + +sqcadd z31.d, z31.d, z31.d, #270 +// CHECK-INST: sqcadd z31.d, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xff,0xdf,0xc1,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff df c1 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +sqcadd z4.d, z4.d, z31.d, #270 +// CHECK-INST: sqcadd z4.d, z4.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0xdf,0xc1,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 df c1 45 Index: test/MC/AArch64/SVE2/sqdmlalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmlalb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlalb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlalb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmlalb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlalb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlalb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlalb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlalb z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdmlalb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlalb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlalb z0.h, z1.b, z31.b +// CHECK-INST: sqdmlalb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x60,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 5f 44 + +sqdmlalb z0.s, z1.h, z31.h +// CHECK-INST: sqdmlalb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x60,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 9f 44 + +sqdmlalb z0.d, z1.s, z31.s +// CHECK-INST: sqdmlalb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x60,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 df 44 + +sqdmlalb z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmlalb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x28,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 28 bf 44 + +sqdmlalb z0.d, z1.s, z15.s[3] +// CHECK-INST: sqdmlalb z0.d, z1.s, z15.s[3] +// CHECK-ENCODING: [0x20,0x28,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 28 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlalb z21.d, z1.s, z31.s +// CHECK-INST: sqdmlalb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x60,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 60 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlalb z21.d, z10.s, z5.s[1] +// CHECK-INST: sqdmlalb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x29,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 29 e5 44 Index: test/MC/AArch64/SVE2/sqdmlalbt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalbt-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlalbt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalbt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalbt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalbt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalbt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalbt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalbt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalbt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlalbt z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlalbt z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlalbt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalbt.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlalbt z0.h, z1.b, z31.b +// CHECK-INST: sqdmlalbt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x08,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 5f 44 + +sqdmlalbt z0.s, z1.h, z31.h +// CHECK-INST: sqdmlalbt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x08,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 9f 44 + +sqdmlalbt z0.d, z1.s, z31.s +// CHECK-INST: sqdmlalbt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x08,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 df 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlalbt z21.d, z1.s, z31.s +// CHECK-INST: sqdmlalbt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x08,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 08 df 44 Index: test/MC/AArch64/SVE2/sqdmlalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalt-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmlalt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlalt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlalt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmlalt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlalt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlalt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlalt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlalt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlalt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlalt z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdmlalt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlalt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlalt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlalt z0.h, z1.b, z31.b +// CHECK-INST: sqdmlalt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x64,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 5f 44 + +sqdmlalt z0.s, z1.h, z31.h +// CHECK-INST: sqdmlalt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x64,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 9f 44 + +sqdmlalt z0.d, z1.s, z31.s +// CHECK-INST: sqdmlalt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x64,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 df 44 + +sqdmlalt z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmlalt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x2c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 2c bf 44 + +sqdmlalt z0.d, z1.s, z15.s[3] +// CHECK-INST: sqdmlalt z0.d, z1.s, z15.s[3] +// CHECK-ENCODING: [0x20,0x2c,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 2c ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlalt z21.d, z1.s, z31.s +// CHECK-INST: sqdmlalt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x64,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 64 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlalt z21.d, z10.s, z5.s[1] +// CHECK-INST: sqdmlalt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x2d,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 2d e5 44 Index: test/MC/AArch64/SVE2/sqdmlslb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmlslb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlslb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlslb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmlslb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlslb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlslb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlslb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlslb z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdmlslb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlslb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlslb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlslb z0.h, z1.b, z31.b +// CHECK-INST: sqdmlslb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x68,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 5f 44 + +sqdmlslb z0.s, z1.h, z31.h +// CHECK-INST: sqdmlslb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x68,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 9f 44 + +sqdmlslb z0.d, z1.s, z31.s +// CHECK-INST: sqdmlslb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x68,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 68 df 44 + +sqdmlslb z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmlslb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x38,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 38 bf 44 + +sqdmlslb z0.d, z1.s, z15.s[3] +// CHECK-INST: sqdmlslb z0.d, z1.s, z15.s[3] +// CHECK-ENCODING: [0x20,0x38,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 38 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlslb z21.d, z1.s, z31.s +// CHECK-INST: sqdmlslb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x68,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 68 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlslb z21.d, z10.s, z5.s[1] +// CHECK-INST: sqdmlslb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x39,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 39 e5 44 Index: test/MC/AArch64/SVE2/sqdmlslbt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslbt-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlslbt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslbt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslbt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslbt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslbt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslbt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslbt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslbt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlslbt z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlslbt z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlslbt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslbt.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlslbt z0.h, z1.b, z31.b +// CHECK-INST: sqdmlslbt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x0c,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c 5f 44 + +sqdmlslbt z0.s, z1.h, z31.h +// CHECK-INST: sqdmlslbt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x0c,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c 9f 44 + +sqdmlslbt z0.d, z1.s, z31.s +// CHECK-INST: sqdmlslbt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x0c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c df 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlslbt z21.d, z1.s, z31.s +// CHECK-INST: sqdmlslbt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x0c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 0c df 44 Index: test/MC/AArch64/SVE2/sqdmlslt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslt-diagnostics.s @@ -0,0 +1,87 @@ + +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmlslt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlslt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmlslt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmlslt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlslt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmlslt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmlslt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmlslt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmlslt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqdmlslt z0.d, z1.s, z15.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqdmlslt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqdmlslt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmlslt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmlslt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmlslt z0.h, z1.b, z31.b +// CHECK-INST: sqdmlslt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x6c,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 5f 44 + +sqdmlslt z0.s, z1.h, z31.h +// CHECK-INST: sqdmlslt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x6c,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 9f 44 + +sqdmlslt z0.d, z1.s, z31.s +// CHECK-INST: sqdmlslt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x6c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c df 44 + +sqdmlslt z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmlslt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x3c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 3c bf 44 + +sqdmlslt z0.d, z1.s, z15.s[3] +// CHECK-INST: sqdmlslt z0.d, z1.s, z15.s[3] +// CHECK-ENCODING: [0x20,0x3c,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 3c ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlslt z21.d, z1.s, z31.s +// CHECK-INST: sqdmlslt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x6c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 6c df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqdmlslt z21.d, z10.s, z5.s[1] +// CHECK-INST: sqdmlslt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x3d,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 3d e5 44 Index: test/MC/AArch64/SVE2/sqdmulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmulh-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmulh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmulh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqdmulh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmulh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmulh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqdmulh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmulh z0.b, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.b, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.h, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.h, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmulh z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmulh z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +sqdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmulh.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqdmulh z0.b, z1.b, z2.b +// CHECK-INST: sqdmulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x70,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 22 04 + +sqdmulh z0.h, z1.h, z2.h +// CHECK-INST: sqdmulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x70,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 62 04 + +sqdmulh z29.s, z30.s, z31.s +// CHECK-INST: sqdmulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x73,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 73 bf 04 + +sqdmulh z31.d, z31.d, z31.d +// CHECK-INST: sqdmulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x73,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 73 ff 04 + +sqdmulh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqdmulh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf0,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 7f 44 + +sqdmulh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqdmulh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf0,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 bf 44 + +sqdmulh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqdmulh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf0,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f0 ff 44 Index: test/MC/AArch64/SVE2/sqdmullb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmullb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmullb z0.h, z1.b, z2.b +// CHECK-INST: sqdmullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x60,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 60 42 45 + +sqdmullb z29.s, z30.h, z31.h +// CHECK-INST: sqdmullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x63,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 63 9f 45 + +sqdmullb z31.d, z31.s, z31.s +// CHECK-INST: sqdmullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x63,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 63 df 45 + +sqdmullb z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xe8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e8 bf 44 + +sqdmullb z0.d, z1.s, z15.s[1] +// CHECK-INST: sqdmullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xe8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e8 ef 44 Index: test/MC/AArch64/SVE2/sqdmullt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqdmullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqdmullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +sqdmullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqdmullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqdmullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqdmullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdmullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdmullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqdmullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqdmullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqdmullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqdmullt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqdmullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqdmullt z0.h, z1.b, z2.b +// CHECK-INST: sqdmullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x64,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 64 42 45 + +sqdmullt z29.s, z30.h, z31.h +// CHECK-INST: sqdmullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x67,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 67 9f 45 + +sqdmullt z31.d, z31.s, z31.s +// CHECK-INST: sqdmullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x67,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 67 df 45 + +sqdmullt z0.s, z1.h, z7.h[7] +// CHECK-INST: sqdmullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xec,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ec bf 44 + +sqdmullt z0.d, z1.s, z15.s[1] +// CHECK-INST: sqdmullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xec,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ec ef 44 Index: test/MC/AArch64/SVE2/sqneg-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqneg-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate + +sqneg z0.s, p8/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqneg z0.s, p8/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqneg z0.b, p7/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqneg z0.b, p7/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqneg.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqneg.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqneg z31.b, p7/m, z31.b +// CHECK-INST: sqneg z31.b, p7/m, z31.b +// CHECK-ENCODING: [0xff,0xbf,0x09,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 09 44 + +sqneg z31.h, p7/m, z31.h +// CHECK-INST: sqneg z31.h, p7/m, z31.h +// CHECK-ENCODING: [0xff,0xbf,0x49,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 49 44 + +sqneg z31.s, p7/m, z31.s +// CHECK-INST: sqneg z31.s, p7/m, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x89,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 89 44 + +sqneg z31.d, p7/m, z31.d +// CHECK-INST: sqneg z31.d, p7/m, z31.d +// CHECK-ENCODING: [0xff,0xbf,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf c9 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.s, p7/z, z6.s +// CHECK-INST: movprfx z4.s, p7/z, z6.s +// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 90 04 + +sqneg z4.s, p7/m, z31.s +// CHECK-INST: sqneg z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 89 44 + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +sqneg z4.s, p7/m, z31.s +// CHECK-INST: sqneg z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 89 44 Index: test/MC/AArch64/SVE2/sqrdcmlah-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdcmlah-diagnostics.s @@ -0,0 +1,103 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element size + +sqrdcmlah z0.h, z1.b, z2.b[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.h, z1.b, z2.b[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.h, z1.s, z2.s[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.h, z1.s, z2.s[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.h, z1.d, z2.d[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.h, z1.d, z2.d[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.b, z2.b[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.s, z1.b, z2.b[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.h, z2.h[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.s, z1.h, z2.h[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.d, z2.d[0], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdcmlah z0.s, z1.d, z2.d[0], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid restricted register for indexed vector. + +sqrdcmlah z0.h, z1.h, z8.h[3], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z8.h[3], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.s, z16.s[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z16.s[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdcmlah z0.h, z1.h, z7.h[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.h, z1.h, z7.h[4], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z7.h[4], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.s, z15.s[-1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[-1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.s, z15.s[2], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[2], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid rotation + +sqrdcmlah z0.h, z1.h, z2.h[0], #360 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: sqrdcmlah z0.h, z1.h, z2.h[0], #360 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdcmlah z0.s, z1.s, z2.s[0], #450 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270. +// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z2.s[0], #450 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.b, p0/z, z7.b +sqrdcmlah z0.b, z1.b, z31.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdcmlah z0.b, z1.b, z31.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqrdcmlah z0.s, z1.s, z15.s[1], #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdcmlah z0.s, z1.s, z15.s[1], #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdcmlah.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdcmlah.s @@ -0,0 +1,156 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrdcmlah z0.b, z1.b, z2.b, #0 +// CHECK-INST: sqrdcmlah z0.b, z1.b, z2.b, #0 +// CHECK-ENCODING: [0x20,0x30,0x02,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 30 02 44 + +sqrdcmlah z0.h, z1.h, z2.h, #0 +// CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h, #0 +// CHECK-ENCODING: [0x20,0x30,0x42,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 30 42 44 + +sqrdcmlah z0.s, z1.s, z2.s, #0 +// CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s, #0 +// CHECK-ENCODING: [0x20,0x30,0x82,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 30 82 44 + +sqrdcmlah z0.d, z1.d, z2.d, #0 +// CHECK-INST: sqrdcmlah z0.d, z1.d, z2.d, #0 +// CHECK-ENCODING: [0x20,0x30,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 30 c2 44 + +sqrdcmlah z29.b, z30.b, z31.b, #90 +// CHECK-INST: sqrdcmlah z29.b, z30.b, z31.b, #90 +// CHECK-ENCODING: [0xdd,0x37,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 37 1f 44 + +sqrdcmlah z29.h, z30.h, z31.h, #90 +// CHECK-INST: sqrdcmlah z29.h, z30.h, z31.h, #90 +// CHECK-ENCODING: [0xdd,0x37,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 37 5f 44 + +sqrdcmlah z29.s, z30.s, z31.s, #90 +// CHECK-INST: sqrdcmlah z29.s, z30.s, z31.s, #90 +// CHECK-ENCODING: [0xdd,0x37,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 37 9f 44 + +sqrdcmlah z29.d, z30.d, z31.d, #90 +// CHECK-INST: sqrdcmlah z29.d, z30.d, z31.d, #90 +// CHECK-ENCODING: [0xdd,0x37,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 37 df 44 + +sqrdcmlah z31.b, z31.b, z31.b, #180 +// CHECK-INST: sqrdcmlah z31.b, z31.b, z31.b, #180 +// CHECK-ENCODING: [0xff,0x3b,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 1f 44 + +sqrdcmlah z31.h, z31.h, z31.h, #180 +// CHECK-INST: sqrdcmlah z31.h, z31.h, z31.h, #180 +// CHECK-ENCODING: [0xff,0x3b,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 5f 44 + +sqrdcmlah z31.s, z31.s, z31.s, #180 +// CHECK-INST: sqrdcmlah z31.s, z31.s, z31.s, #180 +// CHECK-ENCODING: [0xff,0x3b,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 9f 44 + +sqrdcmlah z31.d, z31.d, z31.d, #180 +// CHECK-INST: sqrdcmlah z31.d, z31.d, z31.d, #180 +// CHECK-ENCODING: [0xff,0x3b,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b df 44 + +sqrdcmlah z15.b, z16.b, z17.b, #270 +// CHECK-INST: sqrdcmlah z15.b, z16.b, z17.b, #270 +// CHECK-ENCODING: [0x0f,0x3e,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 3e 11 44 + +sqrdcmlah z15.h, z16.h, z17.h, #270 +// CHECK-INST: sqrdcmlah z15.h, z16.h, z17.h, #270 +// CHECK-ENCODING: [0x0f,0x3e,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 3e 51 44 + +sqrdcmlah z15.s, z16.s, z17.s, #270 +// CHECK-INST: sqrdcmlah z15.s, z16.s, z17.s, #270 +// CHECK-ENCODING: [0x0f,0x3e,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 3e 91 44 + +sqrdcmlah z15.d, z16.d, z17.d, #270 +// CHECK-INST: sqrdcmlah z15.d, z16.d, z17.d, #270 +// CHECK-ENCODING: [0x0f,0x3e,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 3e d1 44 + +sqrdcmlah z0.h, z1.h, z2.h[0], #0 +// CHECK-INST: sqrdcmlah z0.h, z1.h, z2.h[0], #0 +// CHECK-ENCODING: [0x20,0x70,0xa2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 a2 44 + +sqrdcmlah z0.s, z1.s, z2.s[0], #0 +// CHECK-INST: sqrdcmlah z0.s, z1.s, z2.s[0], #0 +// CHECK-ENCODING: [0x20,0x70,0xe2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 e2 44 + +sqrdcmlah z31.h, z30.h, z7.h[0], #180 +// CHECK-INST: sqrdcmlah z31.h, z30.h, z7.h[0], #180 +// CHECK-ENCODING: [0xdf,0x7b,0xa7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 7b a7 44 + +sqrdcmlah z31.s, z30.s, z7.s[0], #180 +// CHECK-INST: sqrdcmlah z31.s, z30.s, z7.s[0], #180 +// CHECK-ENCODING: [0xdf,0x7b,0xe7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 7b e7 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +sqrdcmlah z4.d, z31.d, z31.d, #270 +// CHECK-INST: sqrdcmlah z4.d, z31.d, z31.d, #270 +// CHECK-ENCODING: [0xe4,0x3f,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 3f df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +sqrdcmlah z21.s, z10.s, z5.s[1], #90 +// CHECK-INST: sqrdcmlah z21.s, z10.s, z5.s[1], #90 +// CHECK-ENCODING: [0x55,0x75,0xf5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 75 f5 44 Index: test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlah-diagnostics.s @@ -0,0 +1,70 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmlah z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmlah z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlah z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlah z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlah z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqrdmlah z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqrdmlah z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlah z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmlah.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlah.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqrdmlah z0.b, z1.b, z31.b +// CHECK-INST: sqrdmlah z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x70,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 1f 44 + +sqrdmlah z0.h, z1.h, z31.h +// CHECK-INST: sqrdmlah z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x70,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 5f 44 + +sqrdmlah z0.s, z1.s, z31.s +// CHECK-INST: sqrdmlah z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x70,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 9f 44 + +sqrdmlah z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x70,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 df 44 + +sqrdmlah z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmlah z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x10,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 7f 44 + +sqrdmlah z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmlah z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x10,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 bf 44 + +sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x10,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlah z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlah z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x70,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 df 44 + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlah z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x10,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 ff 44 Index: test/MC/AArch64/SVE2/sqrdmlsh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlsh-diagnostics.s @@ -0,0 +1,70 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmlsh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmlsh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmlsh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmlsh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmlsh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +sqrdmlsh z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +sqrdmlsh z0.d, z1.d, z7.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: sqrdmlsh z0.d, z1.d, z7.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmlsh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmlsh.s @@ -0,0 +1,78 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrdmlsh z0.b, z1.b, z31.b +// CHECK-INST: sqrdmlsh z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x74,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 1f 44 + +sqrdmlsh z0.h, z1.h, z31.h +// CHECK-INST: sqrdmlsh z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x74,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 5f 44 + +sqrdmlsh z0.s, z1.s, z31.s +// CHECK-INST: sqrdmlsh z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x74,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 9f 44 + +sqrdmlsh z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x74,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 df 44 + +sqrdmlsh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmlsh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x14,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 7f 44 + +sqrdmlsh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmlsh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0x14,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 bf 44 + +sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x14,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 ff 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlsh z0.d, z1.d, z31.d +// CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x74,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 df 44 + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmlsh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0x14,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 ff 44 Index: test/MC/AArch64/SVE2/sqrdmulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmulh-diagnostics.s @@ -0,0 +1,104 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +sqrdmulh z0.h, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z8.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z8.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z16.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z16.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element index + +sqrdmulh z0.h, z1.h, z2.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.h, z1.h, z2.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: sqrdmulh z0.h, z1.h, z2.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z2.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.s, z2.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: sqrdmulh z0.s, z1.s, z2.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z2.d[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.d, z2.d[2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1]. +// CHECK-NEXT: sqrdmulh z0.d, z1.d, z2.d[2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqrdmulh z0.b, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.b, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.h, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.h, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrdmulh z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrdmulh z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +sqrdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqrdmulh z31.d, z31.d, z15.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/z, z6.d +sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrdmulh z31.d, z31.d, z15.d[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrdmulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrdmulh.s @@ -0,0 +1,50 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrdmulh z0.b, z1.b, z2.b +// CHECK-INST: sqrdmulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x74,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 22 04 + +sqrdmulh z0.h, z1.h, z2.h +// CHECK-INST: sqrdmulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x74,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 62 04 + +sqrdmulh z29.s, z30.s, z31.s +// CHECK-INST: sqrdmulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x77,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 77 bf 04 + +sqrdmulh z31.d, z31.d, z31.d +// CHECK-INST: sqrdmulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x77,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 77 ff 04 + +sqrdmulh z0.h, z1.h, z7.h[7] +// CHECK-INST: sqrdmulh z0.h, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xf4,0x7f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 7f 44 + +sqrdmulh z0.s, z1.s, z7.s[3] +// CHECK-INST: sqrdmulh z0.s, z1.s, z7.s[3] +// CHECK-ENCODING: [0x20,0xf4,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 bf 44 + +sqrdmulh z0.d, z1.d, z15.d[1] +// CHECK-INST: sqrdmulh z0.d, z1.d, z15.d[1] +// CHECK-ENCODING: [0x20,0xf4,0xff,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 f4 ff 44 Index: test/MC/AArch64/SVE2/sqrshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshl-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqrshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqrshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqrshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqrshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0a 44 + +sqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4a 44 + +sqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8a 44 + +sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ca 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 ca 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xca,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ca 44 Index: test/MC/AArch64/SVE2/sqrshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0e 44 + +sqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4e 44 + +sqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8e 44 + +sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ce 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 ce 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xce,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f ce 44 Index: test/MC/AArch64/SVE2/sqrshrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqrshrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqrshrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshrnb z0.b, z0.h, #1 +// CHECK-INST: sqrshrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x28,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 28 2f 45 + +sqrshrnb z31.b, z31.h, #8 +// CHECK-INST: sqrshrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x2b,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 28 45 + +sqrshrnb z0.h, z0.s, #1 +// CHECK-INST: sqrshrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x28,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 28 3f 45 + +sqrshrnb z31.h, z31.s, #16 +// CHECK-INST: sqrshrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x2b,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 30 45 + +sqrshrnb z0.s, z0.d, #1 +// CHECK-INST: sqrshrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x28,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 28 7f 45 + +sqrshrnb z31.s, z31.d, #32 +// CHECK-INST: sqrshrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x2b,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2b 60 45 Index: test/MC/AArch64/SVE2/sqrshrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqrshrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqrshrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshrnt z0.b, z0.h, #1 +// CHECK-INST: sqrshrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x2c,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 2c 2f 45 + +sqrshrnt z31.b, z31.h, #8 +// CHECK-INST: sqrshrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x2f,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f 28 45 + +sqrshrnt z0.h, z0.s, #1 +// CHECK-INST: sqrshrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x2c,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 2c 3f 45 + +sqrshrnt z31.h, z31.s, #16 +// CHECK-INST: sqrshrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x2f,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f 30 45 + +sqrshrnt z0.s, z0.d, #1 +// CHECK-INST: sqrshrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x2c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 2c 7f 45 + +sqrshrnt z31.s, z31.d, #32 +// CHECK-INST: sqrshrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x2f,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f 60 45 Index: test/MC/AArch64/SVE2/sqrshrunb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrunb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqrshrunb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrunb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrunb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrunb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrunb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrunb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrunb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrunb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqrshrunb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrunb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshrunb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrunb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshrunb z0.b, z0.h, #1 +// CHECK-INST: sqrshrunb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x08,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 08 2f 45 + +sqrshrunb z31.b, z31.h, #8 +// CHECK-INST: sqrshrunb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x0b,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b 28 45 + +sqrshrunb z0.h, z0.s, #1 +// CHECK-INST: sqrshrunb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x08,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 08 3f 45 + +sqrshrunb z31.h, z31.s, #16 +// CHECK-INST: sqrshrunb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x0b,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b 30 45 + +sqrshrunb z0.s, z0.d, #1 +// CHECK-INST: sqrshrunb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x08,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 08 7f 45 + +sqrshrunb z31.s, z31.d, #32 +// CHECK-INST: sqrshrunb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x0b,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b 60 45 Index: test/MC/AArch64/SVE2/sqrshrunt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrunt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqrshrunt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrunt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqrshrunt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrunt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqrshrunt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrunt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqrshrunt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqrshrunt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrunt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrunt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqrshrunt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqrshrunt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqrshrunt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqrshrunt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqrshrunt z0.b, z0.h, #1 +// CHECK-INST: sqrshrunt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x0c,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 0c 2f 45 + +sqrshrunt z31.b, z31.h, #8 +// CHECK-INST: sqrshrunt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x0f,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0f 28 45 + +sqrshrunt z0.h, z0.s, #1 +// CHECK-INST: sqrshrunt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x0c,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 0c 3f 45 + +sqrshrunt z31.h, z31.s, #16 +// CHECK-INST: sqrshrunt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x0f,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0f 30 45 + +sqrshrunt z0.s, z0.d, #1 +// CHECK-INST: sqrshrunt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x0c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 0c 7f 45 + +sqrshrunt z31.s, z31.d, #32 +// CHECK-INST: sqrshrunt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x0f,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0f 60 45 Index: test/MC/AArch64/SVE2/sqshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshl-diagnostics.s @@ -0,0 +1,93 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshl z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshl z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshl z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshl z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshl z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshl.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x08,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 08 44 + +sqshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x48,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 48 44 + +sqshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x88,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 88 44 + +sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c8 44 + +sqshl z0.b, p0/m, z0.b, #0 +// CHECK-INST: sqshl z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 06 04 + +sqshl z31.b, p0/m, z31.b, #7 +// CHECK-INST: sqshl z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 06 04 + +sqshl z0.h, p0/m, z0.h, #0 +// CHECK-INST: sqshl z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 06 04 + +sqshl z31.h, p0/m, z31.h, #15 +// CHECK-INST: sqshl z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x06,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 06 04 + +sqshl z0.s, p0/m, z0.s, #0 +// CHECK-INST: sqshl z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x46,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 46 04 + +sqshl z31.s, p0/m, z31.s, #31 +// CHECK-INST: sqshl z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x46,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 46 04 + +sqshl z0.d, p0/m, z0.d, #0 +// CHECK-INST: sqshl z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x86,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 86 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c8 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c8 44 + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc6,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c6 04 Index: test/MC/AArch64/SVE2/sqshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0c 44 + +sqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4c 44 + +sqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8c 44 + +sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cc 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cc 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cc 44 Index: test/MC/AArch64/SVE2/sqshlu-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshlu-diagnostics.s @@ -0,0 +1,73 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshlu z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqshlu z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqshlu z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqshlu z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlu z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshlu z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshlu z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqshlu z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshlu.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshlu.s @@ -0,0 +1,83 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshlu z0.b, p0/m, z0.b, #0 +// CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 0f 04 + +sqshlu z31.b, p0/m, z31.b, #7 +// CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 0f 04 + +sqshlu z0.h, p0/m, z0.h, #0 +// CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 0f 04 + +sqshlu z31.h, p0/m, z31.h, #15 +// CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x0f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 0f 04 + +sqshlu z0.s, p0/m, z0.s, #0 +// CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x4f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 4f 04 + +sqshlu z31.s, p0/m, z31.s, #31 +// CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x4f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 4f 04 + +sqshlu z0.d, p0/m, z0.d, #0 +// CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x8f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 8f 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xcf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 cf 04 Index: test/MC/AArch64/SVE2/sqshrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqshrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshrnb z0.b, z0.h, #1 +// CHECK-INST: sqshrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x20,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 20 2f 45 + +sqshrnb z31.b, z31.h, #8 +// CHECK-INST: sqshrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x23,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 23 28 45 + +sqshrnb z0.h, z0.s, #1 +// CHECK-INST: sqshrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x20,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 20 3f 45 + +sqshrnb z31.h, z31.s, #16 +// CHECK-INST: sqshrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x23,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 23 30 45 + +sqshrnb z0.s, z0.d, #1 +// CHECK-INST: sqshrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x20,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 20 7f 45 + +sqshrnb z31.s, z31.d, #32 +// CHECK-INST: sqshrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x23,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 23 60 45 Index: test/MC/AArch64/SVE2/sqshrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqshrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshrnt z0.b, z0.h, #1 +// CHECK-INST: sqshrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x24,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 24 2f 45 + +sqshrnt z31.b, z31.h, #8 +// CHECK-INST: sqshrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x27,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 27 28 45 + +sqshrnt z0.h, z0.s, #1 +// CHECK-INST: sqshrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x24,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 24 3f 45 + +sqshrnt z31.h, z31.s, #16 +// CHECK-INST: sqshrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x27,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 27 30 45 + +sqshrnt z0.s, z0.d, #1 +// CHECK-INST: sqshrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x24,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 24 7f 45 + +sqshrnt z31.s, z31.d, #32 +// CHECK-INST: sqshrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x27,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 27 60 45 Index: test/MC/AArch64/SVE2/sqshrunb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrunb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshrunb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrunb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrunb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrunb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrunb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrunb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrunb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrunb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqshrunb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrunb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshrunb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrunb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshrunb z0.b, z0.h, #1 +// CHECK-INST: sqshrunb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x00,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 00 2f 45 + +sqshrunb z31.b, z31.h, #8 +// CHECK-INST: sqshrunb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x03,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 28 45 + +sqshrunb z0.h, z0.s, #1 +// CHECK-INST: sqshrunb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x00,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 00 3f 45 + +sqshrunb z31.h, z31.s, #16 +// CHECK-INST: sqshrunb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x03,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 30 45 + +sqshrunb z0.s, z0.d, #1 +// CHECK-INST: sqshrunb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x00,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 00 7f 45 + +sqshrunb z31.s, z31.d, #32 +// CHECK-INST: sqshrunb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x03,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 60 45 Index: test/MC/AArch64/SVE2/sqshrunt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrunt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sqshrunt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrunt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sqshrunt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrunt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqshrunt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrunt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sqshrunt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sqshrunt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqshrunt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqshrunt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sqshrunt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqshrunt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqshrunt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqshrunt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqshrunt z0.b, z0.h, #1 +// CHECK-INST: sqshrunt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x04,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 04 2f 45 + +sqshrunt z31.b, z31.h, #8 +// CHECK-INST: sqshrunt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x07,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 07 28 45 + +sqshrunt z0.h, z0.s, #1 +// CHECK-INST: sqshrunt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x04,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 04 3f 45 + +sqshrunt z31.h, z31.s, #16 +// CHECK-INST: sqshrunt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x07,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 07 30 45 + +sqshrunt z0.s, z0.d, #1 +// CHECK-INST: sqshrunt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x04,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 04 7f 45 + +sqshrunt z31.s, z31.d, #32 +// CHECK-INST: sqshrunt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x07,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 07 60 45 Index: test/MC/AArch64/SVE2/sqsub-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqsub-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqsub.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1a 44 + +sqsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5a 44 + +sqsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9a,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9a 44 + +sqsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f da 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xda,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 da 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xda,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f da 44 Index: test/MC/AArch64/SVE2/sqsubr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqsubr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +sqsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: sqsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sqsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +sqsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: sqsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqsubr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sqsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: sqsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1e 44 + +sqsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: sqsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5e 44 + +sqsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: sqsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9e,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9e 44 + +sqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f de 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +sqsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: sqsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xde,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 de 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +sqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xde,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f de 44 Index: test/MC/AArch64/SVE2/sqxtnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqxtnb z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnb z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnb z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnb z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnb z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnb z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnb z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnb z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqxtnb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtnb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqxtnb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtnb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqxtnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqxtnb z0.b, z31.h +// CHECK-INST: sqxtnb z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x43,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 43 28 45 + +sqxtnb z0.h, z31.s +// CHECK-INST: sqxtnb z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x43,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 43 30 45 + +sqxtnb z0.s, z31.d +// CHECK-INST: sqxtnb z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x43,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 43 60 45 Index: test/MC/AArch64/SVE2/sqxtnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqxtnt z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnt z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnt z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnt z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnt z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnt z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtnt z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtnt z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqxtnt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtnt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqxtnt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtnt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqxtnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqxtnt z0.b, z31.h +// CHECK-INST: sqxtnt z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x47,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 47 28 45 + +sqxtnt z0.h, z31.s +// CHECK-INST: sqxtnt z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x47,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 47 30 45 + +sqxtnt z0.s, z31.d +// CHECK-INST: sqxtnt z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x47,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 47 60 45 Index: test/MC/AArch64/SVE2/sqxtunb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtunb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqxtunb z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunb z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunb z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunb z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunb z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunb z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunb z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunb z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqxtunb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtunb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqxtunb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtunb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqxtunb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtunb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqxtunb z0.b, z31.h +// CHECK-INST: sqxtunb z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x53,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 53 28 45 + +sqxtunb z0.h, z31.s +// CHECK-INST: sqxtunb z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x53,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 53 30 45 + +sqxtunb z0.s, z31.d +// CHECK-INST: sqxtunb z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x53,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 53 60 45 Index: test/MC/AArch64/SVE2/sqxtunt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtunt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +sqxtunt z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunt z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunt z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunt z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunt z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunt z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqxtunt z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqxtunt z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +sqxtunt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtunt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +sqxtunt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sqxtunt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sqxtunt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sqxtunt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +sqxtunt z0.b, z31.h +// CHECK-INST: sqxtunt z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x57,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 57 28 45 + +sqxtunt z0.h, z31.s +// CHECK-INST: sqxtunt z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x57,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 57 30 45 + +sqxtunt z0.s, z31.d +// CHECK-INST: sqxtunt z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x57,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 57 60 45 Index: test/MC/AArch64/SVE2/srhadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srhadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +srhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/srhadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x14,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 14 44 + +srhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x54,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 54 44 + +srhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x94,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 94 44 + +srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d4 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d4 44 Index: test/MC/AArch64/SVE2/sri-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sri-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sri z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sri z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: sri z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sri z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sri z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sri z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: sri z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: sri z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sri z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: sri z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +sri z0.b, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sri z0.b, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sri z31.d, z31.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sri z31.d, z31.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sri.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sri.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sri z0.b, z0.b, #1 +// CHECK-INST: sri z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0xf0,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f0 0f 45 + +sri z31.b, z31.b, #8 +// CHECK-INST: sri z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0xf3,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f3 08 45 + +sri z0.h, z0.h, #1 +// CHECK-INST: sri z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0xf0,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f0 1f 45 + +sri z31.h, z31.h, #16 +// CHECK-INST: sri z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0xf3,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f3 10 45 + +sri z0.s, z0.s, #1 +// CHECK-INST: sri z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0xf0,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f0 5f 45 + +sri z31.s, z31.s, #32 +// CHECK-INST: sri z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0xf3,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f3 40 45 + +sri z0.d, z0.d, #1 +// CHECK-INST: sri z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0xf0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 f0 df 45 + +sri z31.d, z31.d, #64 +// CHECK-INST: sri z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0xf3,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff f3 80 45 Index: test/MC/AArch64/SVE2/srshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshl-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +srshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/srshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x02,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 02 44 + +srshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x42,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 42 44 + +srshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x82,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 82 44 + +srshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c2 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c2 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c2 44 Index: test/MC/AArch64/SVE2/srshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +srshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: srshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +srshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: srshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/srshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: srshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x06,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 06 44 + +srshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: srshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x46,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 46 44 + +srshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: srshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x86,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 86 44 + +srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c6 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c6 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c6 44 Index: test/MC/AArch64/SVE2/srshr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshr-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +srshr z18.b, p0/m, z18.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srshr z18.b, p0/m, z18.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z1.b, p0/m, z1.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srshr z1.b, p0/m, z1.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z21.h, p0/m, z21.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srshr z21.h, p0/m, z21.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z14.h, p0/m, z14.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srshr z14.h, p0/m, z14.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z6.s, p0/m, z6.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srshr z6.s, p0/m, z6.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z23.s, p0/m, z23.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srshr z23.s, p0/m, z23.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z3.d, p0/m, z3.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srshr z3.d, p0/m, z3.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshr z25.d, p0/m, z25.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srshr z25.d, p0/m, z25.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/srshr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srshr.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srshr z0.b, p0/m, z0.b, #1 +// CHECK-INST: srshr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 81 0c 04 + +srshr z31.b, p0/m, z31.b, #8 +// CHECK-INST: srshr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 81 0c 04 + +srshr z0.h, p0/m, z0.h, #1 +// CHECK-INST: srshr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 0c 04 + +srshr z31.h, p0/m, z31.h, #16 +// CHECK-INST: srshr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x0c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 82 0c 04 + +srshr z0.s, p0/m, z0.s, #1 +// CHECK-INST: srshr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x4c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 4c 04 + +srshr z31.s, p0/m, z31.s, #32 +// CHECK-INST: srshr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x4c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 4c 04 + +srshr z0.d, p0/m, z0.d, #1 +// CHECK-INST: srshr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xcc,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 cc 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +srshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: srshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8c,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8c 04 Index: test/MC/AArch64/SVE2/srsra-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srsra-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +srsra z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srsra z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: srsra z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srsra z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: srsra z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srsra z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: srsra z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srsra z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srsra z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: srsra z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +srsra z0.b, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: srsra z0.b, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +srsra z0.d, z1.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: srsra z0.d, z1.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/srsra.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/srsra.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +srsra z0.b, z0.b, #1 +// CHECK-INST: srsra z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0xe8,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e8 0f 45 + +srsra z31.b, z31.b, #8 +// CHECK-INST: srsra z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0xeb,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff eb 08 45 + +srsra z0.h, z0.h, #1 +// CHECK-INST: srsra z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0xe8,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e8 1f 45 + +srsra z31.h, z31.h, #16 +// CHECK-INST: srsra z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0xeb,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff eb 10 45 + +srsra z0.s, z0.s, #1 +// CHECK-INST: srsra z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0xe8,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e8 5f 45 + +srsra z31.s, z31.s, #32 +// CHECK-INST: srsra z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0xeb,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff eb 40 45 + +srsra z0.d, z0.d, #1 +// CHECK-INST: srsra z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0xe8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e8 df 45 + +srsra z31.d, z31.d, #64 +// CHECK-INST: srsra z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0xeb,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff eb 80 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +srsra z0.d, z1.d, #1 +// CHECK-INST: srsra z0.d, z1.d, #1 +// CHECK-ENCODING: [0x20,0xe8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e8 df 45 Index: test/MC/AArch64/SVE2/sshllb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sshllb-diagnostics.s @@ -0,0 +1,71 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sshllb z18.h, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sshllb z18.h, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z1.h, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sshllb z1.h, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z21.s, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sshllb z21.s, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z14.s, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sshllb z14.s, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z6.d, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sshllb z6.d, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z23.d, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sshllb z23.d, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sshllb z0.b, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllb z0.b, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z0.h, z0.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllb z0.h, z0.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z0.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllb z0.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllb z0.d, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllb z0.d, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sshllb z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sshllb z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/m, z6.d +sshllb z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sshllb z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sshllb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sshllb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sshllb z0.h, z0.b, #0 +// CHECK-INST: sshllb z0.h, z0.b, #0 +// CHECK-ENCODING: [0x00,0xa0,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a0 08 45 + +sshllb z31.h, z31.b, #7 +// CHECK-INST: sshllb z31.h, z31.b, #7 +// CHECK-ENCODING: [0xff,0xa3,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a3 0f 45 + +sshllb z0.s, z0.h, #0 +// CHECK-INST: sshllb z0.s, z0.h, #0 +// CHECK-ENCODING: [0x00,0xa0,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a0 10 45 + +sshllb z31.s, z31.h, #15 +// CHECK-INST: sshllb z31.s, z31.h, #15 +// CHECK-ENCODING: [0xff,0xa3,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a3 1f 45 + +sshllb z0.d, z0.s, #0 +// CHECK-INST: sshllb z0.d, z0.s, #0 +// CHECK-ENCODING: [0x00,0xa0,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a0 40 45 + +sshllb z31.d, z31.s, #31 +// CHECK-INST: sshllb z31.d, z31.s, #31 +// CHECK-ENCODING: [0xff,0xa3,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a3 5f 45 Index: test/MC/AArch64/SVE2/sshllt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sshllt-diagnostics.s @@ -0,0 +1,71 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +sshllt z18.h, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sshllt z18.h, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z1.h, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: sshllt z1.h, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z21.s, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sshllt z21.s, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z14.s, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: sshllt z14.s, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z6.d, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sshllt z6.d, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z23.d, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: sshllt z23.d, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +sshllt z0.b, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllt z0.b, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z0.h, z0.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllt z0.h, z0.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z0.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllt z0.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sshllt z0.d, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sshllt z0.d, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +sshllt z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sshllt z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/m, z6.d +sshllt z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: sshllt z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/sshllt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/sshllt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +sshllt z0.h, z0.b, #0 +// CHECK-INST: sshllt z0.h, z0.b, #0 +// CHECK-ENCODING: [0x00,0xa4,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a4 08 45 + +sshllt z31.h, z31.b, #7 +// CHECK-INST: sshllt z31.h, z31.b, #7 +// CHECK-ENCODING: [0xff,0xa7,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a7 0f 45 + +sshllt z0.s, z0.h, #0 +// CHECK-INST: sshllt z0.s, z0.h, #0 +// CHECK-ENCODING: [0x00,0xa4,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a4 10 45 + +sshllt z31.s, z31.h, #15 +// CHECK-INST: sshllt z31.s, z31.h, #15 +// CHECK-ENCODING: [0xff,0xa7,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a7 1f 45 + +sshllt z0.d, z0.s, #0 +// CHECK-INST: sshllt z0.d, z0.s, #0 +// CHECK-ENCODING: [0x00,0xa4,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a4 40 45 + +sshllt z31.d, z31.s, #31 +// CHECK-INST: sshllt z31.d, z31.s, #31 +// CHECK-ENCODING: [0xff,0xa7,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff a7 5f 45 Index: test/MC/AArch64/SVE2/ssra-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssra-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +ssra z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: ssra z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: ssra z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: ssra z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: ssra z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: ssra z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: ssra z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: ssra z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssra z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: ssra z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +ssra z0.b, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssra z0.b, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ssra z0.d, z1.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ssra z0.d, z1.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssra.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssra.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ssra z0.b, z0.b, #1 +// CHECK-INST: ssra z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0xe0,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e0 0f 45 + +ssra z31.b, z31.b, #8 +// CHECK-INST: ssra z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0xe3,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e3 08 45 + +ssra z0.h, z0.h, #1 +// CHECK-INST: ssra z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0xe0,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e0 1f 45 + +ssra z31.h, z31.h, #16 +// CHECK-INST: ssra z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0xe3,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e3 10 45 + +ssra z0.s, z0.s, #1 +// CHECK-INST: ssra z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0xe0,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e0 5f 45 + +ssra z31.s, z31.s, #32 +// CHECK-INST: ssra z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0xe3,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e3 40 45 + +ssra z0.d, z0.d, #1 +// CHECK-INST: ssra z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0xe0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e0 df 45 + +ssra z31.d, z31.d, #64 +// CHECK-INST: ssra z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0xe3,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e3 80 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +ssra z0.d, z1.d, #1 +// CHECK-INST: ssra z0.d, z1.d, #1 +// CHECK-ENCODING: [0x20,0xe0,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e0 df 45 Index: test/MC/AArch64/SVE2/ssublb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssublb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +ssublb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ssublb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssublb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssublb z0.h, z1.b, z2.b +// CHECK-INST: ssublb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x10,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 10 42 45 + +ssublb z29.s, z30.h, z31.h +// CHECK-INST: ssublb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x13,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 13 9f 45 + +ssublb z31.d, z31.s, z31.s +// CHECK-INST: ssublb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x13,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 df 45 Index: test/MC/AArch64/SVE2/ssublbt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublbt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssublbt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublbt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublbt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublbt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublbt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublbt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublbt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublbt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ssublbt z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublbt z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +ssublbt z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublbt z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssublbt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublbt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssublbt z0.h, z1.b, z31.b +// CHECK-INST: ssublbt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x88,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 88 5f 45 + +ssublbt z0.s, z1.h, z31.h +// CHECK-INST: ssublbt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x88,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 88 9f 45 + +ssublbt z0.d, z1.s, z31.s +// CHECK-INST: ssublbt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x88,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 88 df 45 Index: test/MC/AArch64/SVE2/ssublt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssublt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssublt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssublt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +ssublt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ssublt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssublt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssublt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssublt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssublt z0.h, z1.b, z2.b +// CHECK-INST: ssublt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x14,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 14 42 45 + +ssublt z29.s, z30.h, z31.h +// CHECK-INST: ssublt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x17,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 17 9f 45 + +ssublt z31.d, z31.s, z31.s +// CHECK-INST: ssublt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x17,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 17 df 45 Index: test/MC/AArch64/SVE2/ssubltb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubltb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssubltb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubltb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubltb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubltb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubltb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubltb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubltb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubltb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +ssubltb z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubltb z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.h, p0/z, z7.h +ssubltb z0.h, z1.b, z7.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubltb z0.h, z1.b, z7.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssubltb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubltb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssubltb z0.h, z1.b, z31.b +// CHECK-INST: ssubltb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x8c,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 8c 5f 45 + +ssubltb z0.s, z1.h, z31.h +// CHECK-INST: ssubltb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x8c,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 8c 9f 45 + +ssubltb z0.d, z1.s, z31.s +// CHECK-INST: ssubltb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x8c,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 8c df 45 Index: test/MC/AArch64/SVE2/ssubwb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubwb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssubwb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +ssubwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ssubwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssubwb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubwb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssubwb z0.h, z1.h, z2.b +// CHECK-INST: ssubwb z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x50,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 50 42 45 + +ssubwb z29.s, z30.s, z31.h +// CHECK-INST: ssubwb z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x53,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 53 9f 45 + +ssubwb z31.d, z31.d, z31.s +// CHECK-INST: ssubwb z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x53,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 53 df 45 Index: test/MC/AArch64/SVE2/ssubwt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubwt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ssubwt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ssubwt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ssubwt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +ssubwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +ssubwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ssubwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ssubwt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ssubwt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +ssubwt z0.h, z1.h, z2.b +// CHECK-INST: ssubwt z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x54,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 54 42 45 + +ssubwt z29.s, z30.s, z31.h +// CHECK-INST: ssubwt z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x57,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 57 9f 45 + +ssubwt z31.d, z31.d, z31.s +// CHECK-INST: ssubwt z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x57,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 57 df 45 Index: test/MC/AArch64/SVE2/stnt1b-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1b-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1b { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1b { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1b { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1b { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1b { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1b { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1b { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1b { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/stnt1b.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1b.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1b z0.s, p0, [z1.s] +// CHECK-INST: stnt1b { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e4 + +stnt1b z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e4 + +stnt1b z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e4 + +stnt1b z0.d, p0, [z1.d] +// CHECK-INST: stnt1b { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e4 + +stnt1b z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e4 + +stnt1b z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e4 + +stnt1b { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1b { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e4 + +stnt1b { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e4 + +stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e4 + +stnt1b { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1b { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e4 + +stnt1b { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e4 + +stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e4 Index: test/MC/AArch64/SVE2/stnt1d-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1d-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1d { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.s }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1d { z0.d }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1d { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1d { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1d { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1d { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/stnt1d.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1d.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1d z0.d, p0, [z1.d] +// CHECK-INST: stnt1d { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e5 + +stnt1d z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e5 + +stnt1d z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e5 + +stnt1d { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1d { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e5 + +stnt1d { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e5 + +stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e5 Index: test/MC/AArch64/SVE2/stnt1h-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1h-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1h { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1h { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1h { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1h { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1h { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1h { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1h { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1h { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/stnt1h.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1h.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1h z0.s, p0, [z1.s] +// CHECK-INST: stnt1h { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 df e4 + +stnt1h z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f df e4 + +stnt1h z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f c0 e4 + +stnt1h z0.d, p0, [z1.d] +// CHECK-INST: stnt1h { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e4 + +stnt1h z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e4 + +stnt1h z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e4 + +stnt1h { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1h { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 df e4 + +stnt1h { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f df e4 + +stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f c0 e4 + +stnt1h { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1h { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 9f e4 + +stnt1h { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 9f e4 + +stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 80 e4 Index: test/MC/AArch64/SVE2/stnt1w-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1w-diagnostics.s @@ -0,0 +1,82 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Invalid result type. + +stnt1w { z0.b }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.b }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.h }, p0, [z0.s] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.h }, p0, [z0.s] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid base vector. + +stnt1w { z0.s }, p0, [z0.b] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.b] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.d }, p0, [z0.h] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.h] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid offset type. + +stnt1w { z0.d }, p0, [z0.d, z1.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +stnt1w { z27.d }, p8, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +stnt1w { }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: stnt1w { }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { z0.d, z1.d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { z0.d, z1.d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w { v0.2d }, p0, [z0.d] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w { v0.2d }, p0, [z0.d] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +stnt1w { z0.d }, p0, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +stnt1w { z0.s }, p0, [z0.s, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.s, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/stnt1w.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/stnt1w.s @@ -0,0 +1,80 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +stnt1w z0.s, p0, [z1.s] +// CHECK-INST: stnt1w { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e5 + +stnt1w z31.s, p7, [z31.s, xzr] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e5 + +stnt1w z31.s, p7, [z31.s, x0] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e5 + +stnt1w z0.d, p0, [z1.d] +// CHECK-INST: stnt1w { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e5 + +stnt1w z31.d, p7, [z31.d, xzr] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e5 + +stnt1w z31.d, p7, [z31.d, x0] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e5 + +stnt1w { z0.s }, p0, [z1.s] +// CHECK-INST: stnt1w { z0.s }, p0, [z1.s] +// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 5f e5 + +stnt1w { z31.s }, p7, [z31.s, xzr] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s] +// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 5f e5 + +stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0] +// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 40 e5 + +stnt1w { z0.d }, p0, [z1.d] +// CHECK-INST: stnt1w { z0.d }, p0, [z1.d] +// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 20 1f e5 + +stnt1w { z31.d }, p7, [z31.d, xzr] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 1f e5 + +stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0] +// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 00 e5 Index: test/MC/AArch64/SVE2/subhnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/subhnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +subhnb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +subhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: subhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +subhnb z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: subhnb z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/subhnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/subhnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +subhnb z0.b, z1.h, z31.h +// CHECK-INST: subhnb z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x70,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 7f 45 + +subhnb z0.h, z1.s, z31.s +// CHECK-INST: subhnb z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x70,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 bf 45 + +subhnb z0.s, z1.d, z31.d +// CHECK-INST: subhnb z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x70,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 70 ff 45 Index: test/MC/AArch64/SVE2/subhnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/subhnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +subhnt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +subhnt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: subhnt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +subhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: subhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +subhnt z0.s, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: subhnt z0.s, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/subhnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/subhnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +subhnt z0.b, z1.h, z31.h +// CHECK-INST: subhnt z0.b, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x74,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 7f 45 + +subhnt z0.h, z1.s, z31.s +// CHECK-INST: subhnt z0.h, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x74,0xbf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 bf 45 + +subhnt z0.s, z1.d, z31.d +// CHECK-INST: subhnt z0.s, z1.d, z31.d +// CHECK-ENCODING: [0x20,0x74,0xff,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 74 ff 45 Index: test/MC/AArch64/SVE2/suqadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/suqadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +suqadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: suqadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +suqadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: suqadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +suqadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: suqadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +suqadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: suqadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/suqadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/suqadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +suqadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: suqadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1c 44 + +suqadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: suqadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5c 44 + +suqadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: suqadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9c,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9c 44 + +suqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f dc 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +suqadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: suqadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xdc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 dc 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +suqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f dc 44 Index: test/MC/AArch64/SVE2/tbl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/tbl-diagnostics.s @@ -0,0 +1,51 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +tbl z0.b, { z1.b, z2.b }, z3.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: tbl z0.b, { z1.b, z2.b }, z3.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid vector list. + +tbl z0.d, { }, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected +// CHECK-NEXT: tbl z0.d, { }, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +tbl z0.d, { z1.d, z2.d, z3.d }, z4.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: tbl z0.d, { z1.d, z2.d, z3.d }, z4.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +tbl z0.d, { z1.d, z2.b }, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix +// CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +tbl z0.d, { z1.d, z21.d }, z3.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +tbl z0.d, { v0.2d, v1.2d }, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +tbl z31.d, { z30.d, z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +tbl z31.d, { z30.d, z31.d }, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbl z31.d, { z30.d, z31.d }, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/tbl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/tbl.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +tbl z28.b, { z29.b, z30.b }, z31.b +// CHECK-INST: tbl z28.b, { z29.b, z30.b }, z31.b +// CHECK-ENCODING: [0xbc,0x2b,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bc 2b 3f 05 + +tbl z28.h, { z29.h, z30.h }, z31.h +// CHECK-INST: tbl z28.h, { z29.h, z30.h }, z31.h +// CHECK-ENCODING: [0xbc,0x2b,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bc 2b 7f 05 + +tbl z28.s, { z29.s, z30.s }, z31.s +// CHECK-INST: tbl z28.s, { z29.s, z30.s }, z31.s +// CHECK-ENCODING: [0xbc,0x2b,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bc 2b bf 05 + +tbl z28.d, { z29.d, z30.d }, z31.d +// CHECK-INST: tbl z28.d, { z29.d, z30.d }, z31.d +// CHECK-ENCODING: [0xbc,0x2b,0xff,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: bc 2b ff 05 Index: test/MC/AArch64/SVE2/tbx-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/tbx-diagnostics.s @@ -0,0 +1,22 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +tbx z0.b, z1.b, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: tbx z0.b, z1.b, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +tbx z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbx z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +tbx z31.d, z31.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: tbx z31.d, z31.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/tbx.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/tbx.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +tbx z31.b, z31.b, z31.b +// CHECK-INST: tbx z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x2f,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f 3f 05 + +tbx z31.h, z31.h, z31.h +// CHECK-INST: tbx z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x2f,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f 7f 05 + +tbx z31.s, z31.s, z31.s +// CHECK-INST: tbx z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x2f,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f bf 05 + +tbx z31.d, z31.d, z31.d +// CHECK-INST: tbx z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x2f,0xff,0x05] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 2f ff 05 Index: test/MC/AArch64/SVE2/uaba-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaba-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uaba z0.b, z1.h, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaba z0.b, z1.h, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uaba z0.d, z1.d, z7.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uaba z0.d, z1.d, z7.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uaba.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaba.s @@ -0,0 +1,48 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uaba z0.b, z1.b, z31.b +// CHECK-INST: uaba z0.b, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xfc,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 fc 1f 45 + +uaba z0.h, z1.h, z31.h +// CHECK-INST: uaba z0.h, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xfc,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 fc 5f 45 + +uaba z0.s, z1.s, z31.s +// CHECK-INST: uaba z0.s, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xfc,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 fc 9f 45 + +uaba z0.d, z1.d, z31.d +// CHECK-INST: uaba z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 fc df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +uaba z0.d, z1.d, z31.d +// CHECK-INST: uaba z0.d, z1.d, z31.d +// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 fc df 45 Index: test/MC/AArch64/SVE2/uabalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabalb-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uabalb z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalb z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalb z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalb z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalb z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalb z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalb z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalb z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uabalb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uabalb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uabalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabalb.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uabalb z0.h, z1.b, z31.b +// CHECK-INST: uabalb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xc8,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 5f 45 + +uabalb z0.s, z1.h, z31.h +// CHECK-INST: uabalb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xc8,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 9f 45 + +uabalb z0.d, z1.s, z31.s +// CHECK-INST: uabalb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xc8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 c8 df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +uabalb z21.d, z1.s, z31.s +// CHECK-INST: uabalb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0xc8,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 c8 df 45 Index: test/MC/AArch64/SVE2/uabalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabalt-diagnostics.s @@ -0,0 +1,34 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uabalt z0.b, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalt z0.b, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalt z0.h, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalt z0.h, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalt z0.s, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalt z0.s, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabalt z0.d, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabalt z0.d, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +uabalt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: uabalt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uabalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabalt.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uabalt z0.h, z1.b, z31.b +// CHECK-INST: uabalt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0xcc,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc 5f 45 + +uabalt z0.s, z1.h, z31.h +// CHECK-INST: uabalt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0xcc,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc 9f 45 + +uabalt z0.d, z1.s, z31.s +// CHECK-INST: uabalt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0xcc,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 cc df 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +uabalt z21.d, z1.s, z31.s +// CHECK-INST: uabalt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0xcc,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 cc df 45 Index: test/MC/AArch64/SVE2/uabdlb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabdlb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uabdlb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uabdlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uabdlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uabdlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uabdlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uabdlb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabdlb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uabdlb z0.h, z1.b, z2.b +// CHECK-INST: uabdlb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x38,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 38 42 45 + +uabdlb z29.s, z30.h, z31.h +// CHECK-INST: uabdlb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x3b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 3b 9f 45 + +uabdlb z31.d, z31.s, z31.s +// CHECK-INST: uabdlb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x3b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b df 45 Index: test/MC/AArch64/SVE2/uabdlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabdlt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uabdlt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uabdlt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uabdlt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uabdlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uabdlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uabdlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uabdlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uabdlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uabdlt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uabdlt z0.h, z1.b, z2.b +// CHECK-INST: uabdlt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x3c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 3c 42 45 + +uabdlt z29.s, z30.h, z31.h +// CHECK-INST: uabdlt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x3f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 3f 9f 45 + +uabdlt z31.d, z31.s, z31.s +// CHECK-INST: uabdlt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x3f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f df 45 Index: test/MC/AArch64/SVE2/uadalp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uadalp-diagnostics.s @@ -0,0 +1,42 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uadalp z0.b, p0/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uadalp z0.b, p0/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uadalp z0.h, p0/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uadalp z0.h, p0/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uadalp z0.s, p0/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uadalp z0.s, p0/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uadalp z0.d, p0/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uadalp z0.d, p0/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uadalp z0.h, p8/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uadalp z0.h, p8/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative movprfx tests + +movprfx z31.s, p0/z, z6.s // element type of the source operand, rather than destination. +uadalp z31.d, p0/m, z30.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx with a different element size +// CHECK-NEXT: uadalp z31.d, p0/m, z30.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uadalp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uadalp.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uadalp z0.h, p0/m, z1.b +// CHECK-INST: uadalp z0.h, p0/m, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x45,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 45 44 + +uadalp z29.s, p0/m, z30.h +// CHECK-INST: uadalp z29.s, p0/m, z30.h +// CHECK-ENCODING: [0xdd,0xa3,0x85,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd a3 85 44 + +uadalp z30.d, p7/m, z31.s +// CHECK-INST: uadalp z30.d, p7/m, z31.s +// CHECK-ENCODING: [0xfe,0xbf,0xc5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: fe bf c5 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uadalp z31.d, p0/m, z30.s +// CHECK-INST: uadalp z31.d, p0/m, z30.s +// CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 c5 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uadalp z31.d, p0/m, z30.s +// CHECK-INST: uadalp z31.d, p0/m, z30.s +// CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 c5 44 Index: test/MC/AArch64/SVE2/uaddlb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddlb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uaddlb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uaddlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddlb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddlb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uaddlb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddlb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uaddlb z0.h, z1.b, z2.b +// CHECK-INST: uaddlb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x08,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 08 42 45 + +uaddlb z29.s, z30.h, z31.h +// CHECK-INST: uaddlb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x0b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 0b 9f 45 + +uaddlb z31.d, z31.s, z31.s +// CHECK-INST: uaddlb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x0b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b df 45 Index: test/MC/AArch64/SVE2/uaddlt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddlt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uaddlt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddlt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddlt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uaddlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddlt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddlt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uaddlt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddlt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uaddlt z0.h, z1.b, z2.b +// CHECK-INST: uaddlt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x0c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 0c 42 45 + +uaddlt z29.s, z30.h, z31.h +// CHECK-INST: uaddlt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x0f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 0f 9f 45 + +uaddlt z31.d, z31.s, z31.s +// CHECK-INST: uaddlt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x0f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0f df 45 Index: test/MC/AArch64/SVE2/uaddwb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddwb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uaddwb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uaddwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uaddwb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddwb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uaddwb z0.h, z1.h, z2.b +// CHECK-INST: uaddwb z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x48,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 48 42 45 + +uaddwb z29.s, z30.s, z31.h +// CHECK-INST: uaddwb z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x4b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 4b 9f 45 + +uaddwb z31.d, z31.d, z31.s +// CHECK-INST: uaddwb z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x4b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 4b df 45 Index: test/MC/AArch64/SVE2/uaddwt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddwt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uaddwt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uaddwt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uaddwt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +uaddwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +uaddwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uaddwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uaddwt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uaddwt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uaddwt z0.h, z1.h, z2.b +// CHECK-INST: uaddwt z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x4c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 4c 42 45 + +uaddwt z29.s, z30.s, z31.h +// CHECK-INST: uaddwt z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x4f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 4f 9f 45 + +uaddwt z31.d, z31.d, z31.s +// CHECK-INST: uaddwt z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x4f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 4f df 45 Index: test/MC/AArch64/SVE2/uhadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uhadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x11,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 11 44 + +uhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x51,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 51 44 + +uhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x91,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 91 44 + +uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d1 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d1 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d1 44 Index: test/MC/AArch64/SVE2/uhsub-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhsub-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uhsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uhsub.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x13,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 13 44 + +uhsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x53,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 53 44 + +uhsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x93,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 93 44 + +uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d3 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d3 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d3 44 Index: test/MC/AArch64/SVE2/uhsubr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhsubr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uhsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uhsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uhsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uhsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uhsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uhsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uhsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uhsubr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uhsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uhsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x17,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 17 44 + +uhsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x57,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 57 44 + +uhsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x97,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 97 44 + +uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uhsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d7 44 Index: test/MC/AArch64/SVE2/umaxp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umaxp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +umaxp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: umaxp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +umaxp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umaxp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umaxp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umaxp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +umaxp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: umaxp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umaxp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umaxp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +umaxp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x15,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 15 44 + +umaxp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x55,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 55 44 + +umaxp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x95,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 95 44 + +umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d5 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +umaxp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d5 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d5 44 Index: test/MC/AArch64/SVE2/uminp-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uminp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uminp z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uminp z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uminp z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uminp z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uminp z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uminp z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uminp z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uminp z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uminp.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uminp.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uminp z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0xa0,0x17,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 17 44 + +uminp z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0xa0,0x57,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 a0 57 44 + +uminp z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0xbf,0x97,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd bf 97 44 + +uminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uminp z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df a3 d7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uminp z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df bf d7 44 Index: test/MC/AArch64/SVE2/umlalb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlalb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umlalb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlalb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlalb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umlalb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlalb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umlalb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umlalb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlalb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +umlalb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlalb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umlalb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlalb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umlalb z0.h, z1.b, z31.b +// CHECK-INST: umlalb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x48,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 48 5f 44 + +umlalb z0.s, z1.h, z31.h +// CHECK-INST: umlalb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x48,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 48 9f 44 + +umlalb z0.d, z1.s, z31.s +// CHECK-INST: umlalb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x48,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 48 df 44 + +umlalb z0.s, z1.h, z7.h[7] +// CHECK-INST: umlalb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x98,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 98 bf 44 + +umlalb z0.d, z1.s, z15.s[1] +// CHECK-INST: umlalb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0x98,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 98 ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlalb z21.d, z1.s, z31.s +// CHECK-INST: umlalb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x48,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 48 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlalb z21.d, z10.s, z5.s[1] +// CHECK-INST: umlalb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x99,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 99 e5 44 Index: test/MC/AArch64/SVE2/umlalt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlalt-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umlalt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlalt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlalt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umlalt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlalt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umlalt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlalt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlalt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umlalt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlalt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +umlalt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlalt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umlalt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlalt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umlalt z0.h, z1.b, z31.b +// CHECK-INST: umlalt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x4c,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 4c 5f 44 + +umlalt z0.s, z1.h, z31.h +// CHECK-INST: umlalt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x4c,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 4c 9f 44 + +umlalt z0.d, z1.s, z31.s +// CHECK-INST: umlalt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x4c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 4c df 44 + +umlalt z0.s, z1.h, z7.h[7] +// CHECK-INST: umlalt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0x9c,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 9c bf 44 + +umlalt z0.d, z1.s, z15.s[1] +// CHECK-INST: umlalt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0x9c,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 9c ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlalt z21.d, z1.s, z31.s +// CHECK-INST: umlalt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x4c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 4c df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlalt z21.d, z10.s, z5.s[1] +// CHECK-INST: umlalt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0x9d,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 9d e5 44 Index: test/MC/AArch64/SVE2/umlslb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlslb-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umlslb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlslb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlslb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umlslb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlslb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umlslb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umlslb z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlslb z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +umlslb z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlslb z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umlslb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlslb.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umlslb z0.h, z1.b, z31.b +// CHECK-INST: umlslb z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x58,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 58 5f 44 + +umlslb z0.s, z1.h, z31.h +// CHECK-INST: umlslb z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x58,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 58 9f 44 + +umlslb z0.d, z1.s, z31.s +// CHECK-INST: umlslb z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x58,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 58 df 44 + +umlslb z0.s, z1.h, z7.h[7] +// CHECK-INST: umlslb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xb8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 b8 bf 44 + +umlslb z0.d, z1.s, z15.s[1] +// CHECK-INST: umlslb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xb8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 b8 ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlslb z21.d, z1.s, z31.s +// CHECK-INST: umlslb z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x58,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 58 df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlslb z21.d, z10.s, z5.s[1] +// CHECK-INST: umlslb z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0xb9,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 b9 e5 44 Index: test/MC/AArch64/SVE2/umlslt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlslt-diagnostics.s @@ -0,0 +1,86 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umlslt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlslt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umlslt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umlslt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umlslt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umlslt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umlslt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umlslt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umlslt z0.d, z1.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlslt z0.d, z1.s, z31.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.d, p0/z, z7.d +umlslt z0.d, z1.s, z15.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: umlslt z0.d, z1.s, z15.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umlslt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umlslt.s @@ -0,0 +1,67 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umlslt z0.h, z1.b, z31.b +// CHECK-INST: umlslt z0.h, z1.b, z31.b +// CHECK-ENCODING: [0x20,0x5c,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 5c 5f 44 + +umlslt z0.s, z1.h, z31.h +// CHECK-INST: umlslt z0.s, z1.h, z31.h +// CHECK-ENCODING: [0x20,0x5c,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 5c 9f 44 + +umlslt z0.d, z1.s, z31.s +// CHECK-INST: umlslt z0.d, z1.s, z31.s +// CHECK-ENCODING: [0x20,0x5c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 5c df 44 + +umlslt z0.s, z1.h, z7.h[7] +// CHECK-INST: umlslt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xbc,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 bc bf 44 + +umlslt z0.d, z1.s, z15.s[1] +// CHECK-INST: umlslt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xbc,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 bc ef 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlslt z21.d, z1.s, z31.s +// CHECK-INST: umlslt z21.d, z1.s, z31.s +// CHECK-ENCODING: [0x35,0x5c,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 35 5c df 44 + +movprfx z21, z28 +// CHECK-INST: movprfx z21, z28 +// CHECK-ENCODING: [0x95,0xbf,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 95 bf 20 04 + +umlslt z21.d, z10.s, z5.s[1] +// CHECK-INST: umlslt z21.d, z10.s, z5.s[1] +// CHECK-ENCODING: [0x55,0xbd,0xe5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 55 bd e5 44 Index: test/MC/AArch64/SVE2/umulh-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umulh-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +umulh z0.b, z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.b, z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.h, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.h, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.s, z1.d, z2.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.s, z1.d, z2.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umulh z0.d, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umulh z0.d, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +umulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +umulh z0.d, z1.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umulh z0.d, z1.d, z31.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umulh.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umulh.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +umulh z0.b, z1.b, z2.b +// CHECK-INST: umulh z0.b, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x6c,0x22,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 22 04 + +umulh z0.h, z1.h, z2.h +// CHECK-INST: umulh z0.h, z1.h, z2.h +// CHECK-ENCODING: [0x20,0x6c,0x62,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 6c 62 04 + +umulh z29.s, z30.s, z31.s +// CHECK-INST: umulh z29.s, z30.s, z31.s +// CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 6f bf 04 + +umulh z31.d, z31.d, z31.d +// CHECK-INST: umulh z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6f,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 6f ff 04 Index: test/MC/AArch64/SVE2/umullb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umullb-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umullb z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullb z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullb z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umullb z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullb z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullb z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullb z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullb z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umullb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullb z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullb z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +umullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umullb z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullb z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umullb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umullb.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umullb z0.h, z1.b, z2.b +// CHECK-INST: umullb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x78,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 78 42 45 + +umullb z29.s, z30.h, z31.h +// CHECK-INST: umullb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x7b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 7b 9f 45 + +umullb z31.d, z31.s, z31.s +// CHECK-INST: umullb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x7b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 7b df 45 + +umullb z0.s, z1.h, z7.h[7] +// CHECK-INST: umullb z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xd8,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d8 bf 44 + +umullb z0.d, z1.s, z15.s[1] +// CHECK-INST: umullb z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xd8,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 d8 ef 44 Index: test/MC/AArch64/SVE2/umullt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umullt-diagnostics.s @@ -0,0 +1,106 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// z register out of range for index + +umullt z0.s, z1.h, z8.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullt z0.s, z1.h, z8.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z16.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: umullt z0.d, z1.s, z16.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Index out of bounds + +umullt z0.s, z1.h, z7.h[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullt z0.s, z1.h, z7.h[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.h, z7.h[8] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. +// CHECK-NEXT: umullt z0.s, z1.h, z7.h[8] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z15.s[-1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullt z0.d, z1.s, z15.s[-1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.s, z15.s[4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]. +// CHECK-NEXT: umullt z0.d, z1.s, z15.s[4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid element width + +umullt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.s, z2.s[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.s, z2.s[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.s, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.s, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.b, z2.b[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.b, z2.b[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.h, z2.h[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.h, z2.h[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +umullt z0.d, z1.d, z2.d[0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: umullt z0.d, z1.d, z2.d[0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +umullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +umullt z31.d, z31.s, z15.s[1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: umullt z31.d, z31.s, z15.s[1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/umullt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/umullt.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +umullt z0.h, z1.b, z2.b +// CHECK-INST: umullt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x7c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 7c 42 45 + +umullt z29.s, z30.h, z31.h +// CHECK-INST: umullt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x7f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 7f 9f 45 + +umullt z31.d, z31.s, z31.s +// CHECK-INST: umullt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x7f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 7f df 45 + +umullt z0.s, z1.h, z7.h[7] +// CHECK-INST: umullt z0.s, z1.h, z7.h[7] +// CHECK-ENCODING: [0x20,0xdc,0xbf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 dc bf 44 + +umullt z0.d, z1.s, z15.s[1] +// CHECK-INST: umullt z0.d, z1.s, z15.s[1] +// CHECK-ENCODING: [0x20,0xdc,0xef,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 dc ef 44 Index: test/MC/AArch64/SVE2/uqadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x19,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 19 44 + +uqadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x59,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 59 44 + +uqadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x99,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 99 44 + +uqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d9 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d9 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d9 44 Index: test/MC/AArch64/SVE2/uqrshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshl-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqrshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqrshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqrshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqrshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqrshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqrshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqrshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0b 44 + +uqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqrshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4b 44 + +uqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqrshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8b 44 + +uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cb 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cb 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cb 44 Index: test/MC/AArch64/SVE2/uqrshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqrshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqrshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqrshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqrshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0f 44 + +uqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqrshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4f 44 + +uqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqrshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8f 44 + +uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cf 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cf 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cf 44 Index: test/MC/AArch64/SVE2/uqrshrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqrshrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqrshrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqrshrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqrshrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqrshrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqrshrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqrshrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +uqrshrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +uqrshrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqrshrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqrshrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshrnb z0.b, z0.h, #1 +// CHECK-INST: uqrshrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x38,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 38 2f 45 + +uqrshrnb z31.b, z31.h, #8 +// CHECK-INST: uqrshrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x3b,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 28 45 + +uqrshrnb z0.h, z0.s, #1 +// CHECK-INST: uqrshrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x38,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 38 3f 45 + +uqrshrnb z31.h, z31.s, #16 +// CHECK-INST: uqrshrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x3b,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 30 45 + +uqrshrnb z0.s, z0.d, #1 +// CHECK-INST: uqrshrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x38,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 38 7f 45 + +uqrshrnb z31.s, z31.d, #32 +// CHECK-INST: uqrshrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x3b,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3b 60 45 Index: test/MC/AArch64/SVE2/uqrshrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqrshrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqrshrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqrshrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqrshrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqrshrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqrshrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqrshrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +uqrshrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +uqrshrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqrshrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqrshrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqrshrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqrshrnt z0.b, z0.h, #1 +// CHECK-INST: uqrshrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x3c,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 3c 2f 45 + +uqrshrnt z31.b, z31.h, #8 +// CHECK-INST: uqrshrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x3f,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 28 45 + +uqrshrnt z0.h, z0.s, #1 +// CHECK-INST: uqrshrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x3c,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 3c 3f 45 + +uqrshrnt z31.h, z31.s, #16 +// CHECK-INST: uqrshrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x3f,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 30 45 + +uqrshrnt z0.s, z0.d, #1 +// CHECK-INST: uqrshrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x3c,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 3c 7f 45 + +uqrshrnt z31.s, z31.d, #32 +// CHECK-INST: uqrshrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x3f,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 3f 60 45 Index: test/MC/AArch64/SVE2/uqshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshl-diagnostics.s @@ -0,0 +1,93 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqshl z0.b, p0/m, z0.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.h, p0/m, z0.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.h, p0/m, z0.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.s, p0/m, z0.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.s, p0/m, z0.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z1.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshl z0.b, p0/m, z1.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p0/m, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.b, p0/m, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.d, p0/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshl z0.d, p0/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshl z0.b, p8/m, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshl z0.b, p8/m, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshl.s @@ -0,0 +1,131 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x09,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 09 44 + +uqshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x49,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 49 44 + +uqshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x89,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 89 44 + +uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c9 44 + +uqshl z0.b, p0/m, z0.b, #0 +// CHECK-INST: uqshl z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 81 07 04 + +uqshl z31.b, p0/m, z31.b, #7 +// CHECK-INST: uqshl z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 81 07 04 + +uqshl z0.h, p0/m, z0.h, #0 +// CHECK-INST: uqshl z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 82 07 04 + +uqshl z31.h, p0/m, z31.h, #15 +// CHECK-INST: uqshl z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x07,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 07 04 + +uqshl z0.s, p0/m, z0.s, #0 +// CHECK-INST: uqshl z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x47,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 47 04 + +uqshl z31.s, p0/m, z31.s, #31 +// CHECK-INST: uqshl z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x47,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 47 04 + +uqshl z0.d, p0/m, z0.d, #0 +// CHECK-INST: uqshl z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x87,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 80 87 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c9 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c9 44 + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshl z31.d, p0/m, z31.d, #63 +// CHECK-INST: uqshl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc7,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 83 c7 04 Index: test/MC/AArch64/SVE2/uqshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x0d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 0d 44 + +uqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x4d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 4d 44 + +uqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x8d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 8d 44 + +uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cd 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 cd 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f cd 44 Index: test/MC/AArch64/SVE2/uqshrnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshrnb-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqshrnb z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqshrnb z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqshrnb z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqshrnb z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqshrnb z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqshrnb z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqshrnb z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +uqshrnb z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnb z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnb z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnb z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnb z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnb z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +uqshrnb z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqshrnb z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqshrnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshrnb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshrnb z0.b, z0.h, #1 +// CHECK-INST: uqshrnb z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x30,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 30 2f 45 + +uqshrnb z31.b, z31.h, #8 +// CHECK-INST: uqshrnb z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x33,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 33 28 45 + +uqshrnb z0.h, z0.s, #1 +// CHECK-INST: uqshrnb z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x30,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 30 3f 45 + +uqshrnb z31.h, z31.s, #16 +// CHECK-INST: uqshrnb z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x33,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 33 30 45 + +uqshrnb z0.s, z0.d, #1 +// CHECK-INST: uqshrnb z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x30,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 30 7f 45 + +uqshrnb z31.s, z31.d, #32 +// CHECK-INST: uqshrnb z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x33,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 33 60 45 Index: test/MC/AArch64/SVE2/uqshrnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshrnt-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +uqshrnt z30.b, z10.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqshrnt z30.b, z10.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z18.b, z27.h, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: uqshrnt z18.b, z27.h, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z26.h, z4.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqshrnt z26.h, z4.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z25.h, z10.s, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: uqshrnt z25.h, z10.s, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z17.s, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqshrnt z17.s, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z0.s, z15.d, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: uqshrnt z0.s, z15.d, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +uqshrnt z0.b, z0.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnt z0.b, z0.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z0.h, z0.h, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnt z0.h, z0.h, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z0.s, z0.s, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnt z0.s, z0.s, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqshrnt z0.d, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqshrnt z0.d, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +uqshrnt z31.s, z31.d, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqshrnt z31.s, z31.d, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqshrnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqshrnt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqshrnt z0.b, z0.h, #1 +// CHECK-INST: uqshrnt z0.b, z0.h, #1 +// CHECK-ENCODING: [0x00,0x34,0x2f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 34 2f 45 + +uqshrnt z31.b, z31.h, #8 +// CHECK-INST: uqshrnt z31.b, z31.h, #8 +// CHECK-ENCODING: [0xff,0x37,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 37 28 45 + +uqshrnt z0.h, z0.s, #1 +// CHECK-INST: uqshrnt z0.h, z0.s, #1 +// CHECK-ENCODING: [0x00,0x34,0x3f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 34 3f 45 + +uqshrnt z31.h, z31.s, #16 +// CHECK-INST: uqshrnt z31.h, z31.s, #16 +// CHECK-ENCODING: [0xff,0x37,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 37 30 45 + +uqshrnt z0.s, z0.d, #1 +// CHECK-INST: uqshrnt z0.s, z0.d, #1 +// CHECK-ENCODING: [0x00,0x34,0x7f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 34 7f 45 + +uqshrnt z31.s, z31.d, #32 +// CHECK-INST: uqshrnt z31.s, z31.d, #32 +// CHECK-ENCODING: [0xff,0x37,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 37 60 45 Index: test/MC/AArch64/SVE2/uqsub-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqsub-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqsub z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqsub z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqsub z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqsub z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsub z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqsub z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqsub z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqsub z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqsub.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqsub.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqsub z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqsub z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1b 44 + +uqsub z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqsub z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5b 44 + +uqsub z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqsub z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9b,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9b 44 + +uqsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f db 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqsub z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqsub z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xdb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 db 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqsub z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f db 44 Index: test/MC/AArch64/SVE2/uqsubr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqsubr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +uqsubr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: uqsubr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +uqsubr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqsubr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqsubr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqsubr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +uqsubr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: uqsubr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqsubr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqsubr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uqsubr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: uqsubr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1f 44 + +uqsubr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: uqsubr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5f 44 + +uqsubr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: uqsubr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9f,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9f 44 + +uqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f df 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +uqsubr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: uqsubr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 df 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +uqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f df 44 Index: test/MC/AArch64/SVE2/uqxtnb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqxtnb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uqxtnb z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnb z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnb z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnb z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnb z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnb z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnb z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnb z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqxtnb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqxtnb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqxtnb z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqxtnb z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqxtnb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqxtnb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uqxtnb z0.b, z31.h +// CHECK-INST: uqxtnb z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x4b,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4b 28 45 + +uqxtnb z0.h, z31.s +// CHECK-INST: uqxtnb z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x4b,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4b 30 45 + +uqxtnb z0.s, z31.d +// CHECK-INST: uqxtnb z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x4b,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4b 60 45 Index: test/MC/AArch64/SVE2/uqxtnt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqxtnt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +uqxtnt z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnt z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnt z0.h, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnt z0.h, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnt z0.s, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnt z0.s, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqxtnt z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqxtnt z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0, z7 +uqxtnt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqxtnt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0.s, p0/z, z7.s +uqxtnt z0.s, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: uqxtnt z0.s, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/uqxtnt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/uqxtnt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +uqxtnt z0.b, z31.h +// CHECK-INST: uqxtnt z0.b, z31.h +// CHECK-ENCODING: [0xe0,0x4f,0x28,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4f 28 45 + +uqxtnt z0.h, z31.s +// CHECK-INST: uqxtnt z0.h, z31.s +// CHECK-ENCODING: [0xe0,0x4f,0x30,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4f 30 45 + +uqxtnt z0.s, z31.d +// CHECK-INST: uqxtnt z0.s, z31.d +// CHECK-ENCODING: [0xe0,0x4f,0x60,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 4f 60 45 Index: test/MC/AArch64/SVE2/urecpe-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urecpe-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate + +urecpe z0.s, p8/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urecpe z0.s, p8/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +urecpe z0.b, p7/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z0.b, p7/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urecpe z0.h, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z0.h, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urecpe z0.d, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urecpe z0.d, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/urecpe.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urecpe.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urecpe z31.s, p7/m, z31.s +// CHECK-INST: urecpe z31.s, p7/m, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x80,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 80 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.s, p7/z, z6.s +// CHECK-INST: movprfx z4.s, p7/z, z6.s +// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 90 04 + +urecpe z4.s, p7/m, z31.s +// CHECK-INST: urecpe z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 80 44 + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +urecpe z4.s, p7/m, z31.s +// CHECK-INST: urecpe z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 80 44 Index: test/MC/AArch64/SVE2/urhadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urhadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urhadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urhadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urhadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urhadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urhadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urhadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +urhadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urhadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/urhadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urhadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urhadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x15,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 15 44 + +urhadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x55,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 55 44 + +urhadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x95,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 95 44 + +urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urhadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 d5 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f d5 44 Index: test/MC/AArch64/SVE2/urshl-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshl-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urshl z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urshl z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urshl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshl z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +urshl z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urshl z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/urshl.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshl.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshl z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urshl z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x03,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 03 44 + +urshl z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urshl z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x43,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 43 44 + +urshl z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urshl z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x83,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 83 44 + +urshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c3 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshl z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c3 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshl z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c3 44 Index: test/MC/AArch64/SVE2/urshlr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshlr-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +urshlr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: urshlr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +urshlr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshlr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshlr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +urshlr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: urshlr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/urshlr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshlr.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshlr z0.b, p0/m, z0.b, z1.b +// CHECK-INST: urshlr z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x07,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 07 44 + +urshlr z0.h, p0/m, z0.h, z1.h +// CHECK-INST: urshlr z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x47,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 47 44 + +urshlr z29.s, p7/m, z29.s, z30.s +// CHECK-INST: urshlr z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x87,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 87 44 + +urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c7 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshlr z31.d, p0/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 c7 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f c7 44 Index: test/MC/AArch64/SVE2/urshr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshr-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +urshr z18.b, p0/m, z18.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: urshr z18.b, p0/m, z18.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z1.b, p0/m, z1.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: urshr z1.b, p0/m, z1.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z21.h, p0/m, z21.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: urshr z21.h, p0/m, z21.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z14.h, p0/m, z14.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: urshr z14.h, p0/m, z14.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z6.s, p0/m, z6.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: urshr z6.s, p0/m, z6.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z23.s, p0/m, z23.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: urshr z23.s, p0/m, z23.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z3.d, p0/m, z3.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: urshr z3.d, p0/m, z3.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshr z25.d, p0/m, z25.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: urshr z25.d, p0/m, z25.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/urshr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/urshr.s @@ -0,0 +1,84 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +urshr z0.b, p0/m, z0.b, #1 +// CHECK-INST: urshr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 81 0d 04 + +urshr z31.b, p0/m, z31.b, #8 +// CHECK-INST: urshr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 81 0d 04 + +urshr z0.h, p0/m, z0.h, #1 +// CHECK-INST: urshr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 0d 04 + +urshr z31.h, p0/m, z31.h, #16 +// CHECK-INST: urshr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x0d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 82 0d 04 + +urshr z0.s, p0/m, z0.s, #1 +// CHECK-INST: urshr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x4d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 4d 04 + +urshr z31.s, p0/m, z31.s, #32 +// CHECK-INST: urshr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x4d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 4d 04 + +urshr z0.d, p0/m, z0.d, #1 +// CHECK-INST: urshr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xcd,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e0 83 cd 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +urshr z31.d, p0/m, z31.d, #64 +// CHECK-INST: urshr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x8d,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 80 8d 04 Index: test/MC/AArch64/SVE2/ursqrte-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ursqrte-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate + +ursqrte z0.s, p8/m, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ursqrte z0.s, p8/m, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid element width + +ursqrte z0.b, p7/m, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z0.b, p7/m, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursqrte z0.h, p7/m, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z0.h, p7/m, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursqrte z0.d, p7/m, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursqrte z0.d, p7/m, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ursqrte.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ursqrte.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ursqrte z31.s, p7/m, z31.s +// CHECK-INST: ursqrte z31.s, p7/m, z31.s +// CHECK-ENCODING: [0xff,0xbf,0x81,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff bf 81 44 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z4.s, p7/z, z6.s +// CHECK-INST: movprfx z4.s, p7/z, z6.s +// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 3c 90 04 + +ursqrte z4.s, p7/m, z31.s +// CHECK-INST: ursqrte z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 81 44 + +movprfx z4, z6 +// CHECK-INST: movprfx z4, z6 +// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: c4 bc 20 04 + +ursqrte z4.s, p7/m, z31.s +// CHECK-INST: ursqrte z4.s, p7/m, z31.s +// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: e4 bf 81 44 Index: test/MC/AArch64/SVE2/ursra-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ursra-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +ursra z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: ursra z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: ursra z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: ursra z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: ursra z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: ursra z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: ursra z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: ursra z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ursra z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: ursra z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +ursra z0.b, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ursra z0.b, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +ursra z0.d, z1.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: ursra z0.d, z1.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ursra.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ursra.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ursra z0.b, z0.b, #1 +// CHECK-INST: ursra z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0xec,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ec 0f 45 + +ursra z31.b, z31.b, #8 +// CHECK-INST: ursra z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0xef,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ef 08 45 + +ursra z0.h, z0.h, #1 +// CHECK-INST: ursra z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0xec,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ec 1f 45 + +ursra z31.h, z31.h, #16 +// CHECK-INST: ursra z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0xef,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ef 10 45 + +ursra z0.s, z0.s, #1 +// CHECK-INST: ursra z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0xec,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ec 5f 45 + +ursra z31.s, z31.s, #32 +// CHECK-INST: ursra z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0xef,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ef 40 45 + +ursra z0.d, z0.d, #1 +// CHECK-INST: ursra z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0xec,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ec df 45 + +ursra z31.d, z31.d, #64 +// CHECK-INST: ursra z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0xef,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ef 80 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +ursra z0.d, z1.d, #1 +// CHECK-INST: ursra z0.d, z1.d, #1 +// CHECK-ENCODING: [0x20,0xec,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 ec df 45 Index: test/MC/AArch64/SVE2/ushllb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ushllb-diagnostics.s @@ -0,0 +1,71 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +ushllb z18.h, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: ushllb z18.h, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z1.h, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: ushllb z1.h, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z21.s, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: ushllb z21.s, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z14.s, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: ushllb z14.s, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z6.d, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: ushllb z6.d, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z23.d, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: ushllb z23.d, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +ushllb z0.b, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllb z0.b, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z0.h, z0.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllb z0.h, z0.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z0.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllb z0.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllb z0.d, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllb z0.d, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +ushllb z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ushllb z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/m, z6.d +ushllb z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ushllb z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ushllb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ushllb.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ushllb z0.h, z0.b, #0 +// CHECK-INST: ushllb z0.h, z0.b, #0 +// CHECK-ENCODING: [0x00,0xa8,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a8 08 45 + +ushllb z31.h, z31.b, #7 +// CHECK-INST: ushllb z31.h, z31.b, #7 +// CHECK-ENCODING: [0xff,0xab,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ab 0f 45 + +ushllb z0.s, z0.h, #0 +// CHECK-INST: ushllb z0.s, z0.h, #0 +// CHECK-ENCODING: [0x00,0xa8,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a8 10 45 + +ushllb z31.s, z31.h, #15 +// CHECK-INST: ushllb z31.s, z31.h, #15 +// CHECK-ENCODING: [0xff,0xab,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ab 1f 45 + +ushllb z0.d, z0.s, #0 +// CHECK-INST: ushllb z0.d, z0.s, #0 +// CHECK-ENCODING: [0x00,0xa8,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 a8 40 45 + +ushllb z31.d, z31.s, #31 +// CHECK-INST: ushllb z31.d, z31.s, #31 +// CHECK-ENCODING: [0xff,0xab,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff ab 5f 45 Index: test/MC/AArch64/SVE2/ushllt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ushllt-diagnostics.s @@ -0,0 +1,71 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +ushllt z18.h, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: ushllt z18.h, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z1.h, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: ushllt z1.h, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z21.s, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: ushllt z21.s, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z14.s, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: ushllt z14.s, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z6.d, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: ushllt z6.d, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z23.d, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: ushllt z23.d, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Invalid element width + +ushllt z0.b, z0.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllt z0.b, z0.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z0.h, z0.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllt z0.h, z0.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z0.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllt z0.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ushllt z0.d, z0.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: ushllt z0.d, z0.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +ushllt z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ushllt z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.d, p0/m, z6.d +ushllt z31.d, z31.s, #31 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: ushllt z31.d, z31.s, #31 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/ushllt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/ushllt.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ushllt z0.h, z0.b, #0 +// CHECK-INST: ushllt z0.h, z0.b, #0 +// CHECK-ENCODING: [0x00,0xac,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ac 08 45 + +ushllt z31.h, z31.b, #7 +// CHECK-INST: ushllt z31.h, z31.b, #7 +// CHECK-ENCODING: [0xff,0xaf,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff af 0f 45 + +ushllt z0.s, z0.h, #0 +// CHECK-INST: ushllt z0.s, z0.h, #0 +// CHECK-ENCODING: [0x00,0xac,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ac 10 45 + +ushllt z31.s, z31.h, #15 +// CHECK-INST: ushllt z31.s, z31.h, #15 +// CHECK-ENCODING: [0xff,0xaf,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff af 1f 45 + +ushllt z0.d, z0.s, #0 +// CHECK-INST: ushllt z0.d, z0.s, #0 +// CHECK-ENCODING: [0x00,0xac,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 ac 40 45 + +ushllt z31.d, z31.s, #31 +// CHECK-INST: ushllt z31.d, z31.s, #31 +// CHECK-ENCODING: [0xff,0xaf,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff af 5f 45 Index: test/MC/AArch64/SVE2/usqadd-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usqadd-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +usqadd z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: usqadd z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +usqadd z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usqadd z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usqadd z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usqadd z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +usqadd z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: usqadd z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usqadd.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usqadd.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +usqadd z0.b, p0/m, z0.b, z1.b +// CHECK-INST: usqadd z0.b, p0/m, z0.b, z1.b +// CHECK-ENCODING: [0x20,0x80,0x1d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 1d 44 + +usqadd z0.h, p0/m, z0.h, z1.h +// CHECK-INST: usqadd z0.h, p0/m, z0.h, z1.h +// CHECK-ENCODING: [0x20,0x80,0x5d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 80 5d 44 + +usqadd z29.s, p7/m, z29.s, z30.s +// CHECK-INST: usqadd z29.s, p7/m, z29.s, z30.s +// CHECK-ENCODING: [0xdd,0x9f,0x9d,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 9f 9d 44 + +usqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f dd 44 + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31.d, p0/z, z6.d +// CHECK-INST: movprfx z31.d, p0/z, z6.d +// CHECK-ENCODING: [0xdf,0x20,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df 20 d0 04 + +usqadd z31.d, p0/m, z31.d, z30.d +// CHECK-INST: usqadd z31.d, p0/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x83,0xdd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 83 dd 44 + +movprfx z31, z6 +// CHECK-INST: movprfx z31, z6 +// CHECK-ENCODING: [0xdf,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: df bc 20 04 + +usqadd z31.d, p7/m, z31.d, z30.d +// CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d +// CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 9f dd 44 Index: test/MC/AArch64/SVE2/usra-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usra-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +usra z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: usra z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: usra z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: usra z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: usra z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: usra z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: usra z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: usra z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usra z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: usra z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +usra z0.b, z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usra z0.b, z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +usra z0.d, z1.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: usra z0.d, z1.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usra.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usra.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +usra z0.b, z0.b, #1 +// CHECK-INST: usra z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0xe4,0x0f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e4 0f 45 + +usra z31.b, z31.b, #8 +// CHECK-INST: usra z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0xe7,0x08,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e7 08 45 + +usra z0.h, z0.h, #1 +// CHECK-INST: usra z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0xe4,0x1f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e4 1f 45 + +usra z31.h, z31.h, #16 +// CHECK-INST: usra z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0xe7,0x10,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e7 10 45 + +usra z0.s, z0.s, #1 +// CHECK-INST: usra z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0xe4,0x5f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e4 5f 45 + +usra z31.s, z31.s, #32 +// CHECK-INST: usra z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0xe7,0x40,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e7 40 45 + +usra z0.d, z0.d, #1 +// CHECK-INST: usra z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0xe4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 00 e4 df 45 + +usra z31.d, z31.d, #64 +// CHECK-INST: usra z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0xe7,0x80,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff e7 80 45 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z0, z7 +// CHECK-INST: movprfx z0, z7 +// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 bc 20 04 + +usra z0.d, z1.d, #1 +// CHECK-INST: usra z0.d, z1.d, #1 +// CHECK-ENCODING: [0x20,0xe4,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 e4 df 45 Index: test/MC/AArch64/SVE2/usublb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usublb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +usublb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +usublb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usublb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +usublb z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usublb z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usublb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usublb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +usublb z0.h, z1.b, z2.b +// CHECK-INST: usublb z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x18,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 18 42 45 + +usublb z29.s, z30.h, z31.h +// CHECK-INST: usublb z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x1b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 1b 9f 45 + +usublb z31.d, z31.s, z31.s +// CHECK-INST: usublb z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b df 45 Index: test/MC/AArch64/SVE2/usublt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usublt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +usublt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usublt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usublt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +usublt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usublt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +usublt z0.d, z1.s, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usublt z0.d, z1.s, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usublt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usublt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +usublt z0.h, z1.b, z2.b +// CHECK-INST: usublt z0.h, z1.b, z2.b +// CHECK-ENCODING: [0x20,0x1c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 1c 42 45 + +usublt z29.s, z30.h, z31.h +// CHECK-INST: usublt z29.s, z30.h, z31.h +// CHECK-ENCODING: [0xdd,0x1f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 1f 9f 45 + +usublt z31.d, z31.s, z31.s +// CHECK-INST: usublt z31.d, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x1f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1f df 45 Index: test/MC/AArch64/SVE2/usubwb-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usubwb-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +usubwb z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwb z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwb z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwb z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwb z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwb z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwb z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwb z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +usubwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usubwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +usubwb z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usubwb z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usubwb.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usubwb.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +usubwb z0.h, z1.h, z2.b +// CHECK-INST: usubwb z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x58,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 58 42 45 + +usubwb z29.s, z30.s, z31.h +// CHECK-INST: usubwb z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x5b,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 5b 9f 45 + +usubwb z31.d, z31.d, z31.s +// CHECK-INST: usubwb z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x5b,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 5b df 45 Index: test/MC/AArch64/SVE2/usubwt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usubwt-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid element width + +usubwt z0.b, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwt z0.b, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwt z0.h, z0.h, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwt z0.h, z0.h, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwt z0.s, z0.s, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwt z0.s, z0.s, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +usubwt z0.d, z0.d, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: usubwt z0.d, z0.d, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.d, p0/z, z6.d +usubwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usubwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +usubwt z0.d, z1.d, z2.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: usubwt z0.d, z1.d, z2.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/usubwt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/usubwt.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + + +usubwt z0.h, z1.h, z2.b +// CHECK-INST: usubwt z0.h, z1.h, z2.b +// CHECK-ENCODING: [0x20,0x5c,0x42,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 5c 42 45 + +usubwt z29.s, z30.s, z31.h +// CHECK-INST: usubwt z29.s, z30.s, z31.h +// CHECK-ENCODING: [0xdd,0x5f,0x9f,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: dd 5f 9f 45 + +usubwt z31.d, z31.d, z31.s +// CHECK-INST: usubwt z31.d, z31.d, z31.s +// CHECK-ENCODING: [0xff,0x5f,0xdf,0x45] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 5f df 45 Index: test/MC/AArch64/SVE2/whilege-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilege-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilege p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilege p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilege p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilege p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilege p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilege p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilege.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilege.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilege p15.b, xzr, x0 +// CHECK-INST: whilege p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x13,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 13 20 25 + +whilege p15.b, x0, xzr +// CHECK-INST: whilege p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 3f 25 + +whilege p15.b, wzr, w0 +// CHECK-INST: whilege p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x03,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 03 20 25 + +whilege p15.b, w0, wzr +// CHECK-INST: whilege p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 3f 25 + +whilege p15.h, x0, xzr +// CHECK-INST: whilege p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 7f 25 + +whilege p15.h, w0, wzr +// CHECK-INST: whilege p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 7f 25 + +whilege p15.s, x0, xzr +// CHECK-INST: whilege p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 bf 25 + +whilege p15.s, w0, wzr +// CHECK-INST: whilege p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 bf 25 + +whilege p15.d, w0, wzr +// CHECK-INST: whilege p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x00,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 00 ff 25 + +whilege p15.d, x0, xzr +// CHECK-INST: whilege p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x10,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 10 ff 25 Index: test/MC/AArch64/SVE2/whilegt-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilegt-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilegt p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilegt p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilegt p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilegt p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilegt p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilegt p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilegt.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilegt.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilegt p15.b, xzr, x0 +// CHECK-INST: whilegt p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x13,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 13 20 25 + +whilegt p15.b, x0, xzr +// CHECK-INST: whilegt p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 3f 25 + +whilegt p15.b, wzr, w0 +// CHECK-INST: whilegt p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x03,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 03 20 25 + +whilegt p15.b, w0, wzr +// CHECK-INST: whilegt p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 3f 25 + +whilegt p15.h, x0, xzr +// CHECK-INST: whilegt p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 7f 25 + +whilegt p15.h, w0, wzr +// CHECK-INST: whilegt p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 7f 25 + +whilegt p15.s, x0, xzr +// CHECK-INST: whilegt p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 bf 25 + +whilegt p15.s, w0, wzr +// CHECK-INST: whilegt p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 bf 25 + +whilegt p15.d, w0, wzr +// CHECK-INST: whilegt p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x00,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 00 ff 25 + +whilegt p15.d, x0, xzr +// CHECK-INST: whilegt p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x10,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 10 ff 25 Index: test/MC/AArch64/SVE2/whilehi-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilehi-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilehi p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehi p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehi p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehi p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilehi p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilehi p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilehi.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilehi.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilehi p15.b, xzr, x0 +// CHECK-INST: whilehi p15.b, xzr, x0 +// CHECK-ENCODING: [0xff,0x1b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 1b 20 25 + +whilehi p15.b, x0, xzr +// CHECK-INST: whilehi p15.b, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 3f 25 + +whilehi p15.b, wzr, w0 +// CHECK-INST: whilehi p15.b, wzr, w0 +// CHECK-ENCODING: [0xff,0x0b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ff 0b 20 25 + +whilehi p15.b, w0, wzr +// CHECK-INST: whilehi p15.b, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 3f 25 + +whilehi p15.h, x0, xzr +// CHECK-INST: whilehi p15.h, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 7f 25 + +whilehi p15.h, w0, wzr +// CHECK-INST: whilehi p15.h, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 7f 25 + +whilehi p15.s, x0, xzr +// CHECK-INST: whilehi p15.s, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 bf 25 + +whilehi p15.s, w0, wzr +// CHECK-INST: whilehi p15.s, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 bf 25 + +whilehi p15.d, w0, wzr +// CHECK-INST: whilehi p15.d, w0, wzr +// CHECK-ENCODING: [0x1f,0x08,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 08 ff 25 + +whilehi p15.d, x0, xzr +// CHECK-INST: whilehi p15.d, x0, xzr +// CHECK-ENCODING: [0x1f,0x18,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 1f 18 ff 25 Index: test/MC/AArch64/SVE2/whilehs-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilehs-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilehs p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehs p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilehs p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilehs p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate + +whilehs p15, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: whilehs p15, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilehs.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilehs.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilehs p15.b, xzr, x0 +// CHECK-INST: whilehs p15.b, xzr, x0 +// CHECK-ENCODING: [0xef,0x1b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 1b 20 25 + +whilehs p15.b, x0, xzr +// CHECK-INST: whilehs p15.b, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 3f 25 + +whilehs p15.b, wzr, w0 +// CHECK-INST: whilehs p15.b, wzr, w0 +// CHECK-ENCODING: [0xef,0x0b,0x20,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: ef 0b 20 25 + +whilehs p15.b, w0, wzr +// CHECK-INST: whilehs p15.b, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0x3f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 3f 25 + +whilehs p15.h, x0, xzr +// CHECK-INST: whilehs p15.h, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 7f 25 + +whilehs p15.h, w0, wzr +// CHECK-INST: whilehs p15.h, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0x7f,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 7f 25 + +whilehs p15.s, x0, xzr +// CHECK-INST: whilehs p15.s, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 bf 25 + +whilehs p15.s, w0, wzr +// CHECK-INST: whilehs p15.s, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0xbf,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 bf 25 + +whilehs p15.d, w0, wzr +// CHECK-INST: whilehs p15.d, w0, wzr +// CHECK-ENCODING: [0x0f,0x08,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 08 ff 25 + +whilehs p15.d, x0, xzr +// CHECK-INST: whilehs p15.d, x0, xzr +// CHECK-ENCODING: [0x0f,0x18,0xff,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 0f 18 ff 25 Index: test/MC/AArch64/SVE2/whilerw-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilerw-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilerw p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilerw p15.b, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilerw p15.b, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilerw.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilerw.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilerw p15.b, x30, x30 +// CHECK-INST: whilerw p15.b, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0x3e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 3e 25 + +whilerw p15.h, x30, x30 +// CHECK-INST: whilerw p15.h, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0x7e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 7e 25 + +whilerw p15.s, x30, x30 +// CHECK-INST: whilerw p15.s, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 be 25 + +whilerw p15.d, x30, x30 +// CHECK-INST: whilerw p15.d, x30, x30 +// CHECK-ENCODING: [0xdf,0x33,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 33 fe 25 Index: test/MC/AArch64/SVE2/whilewr-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilewr-diagnostics.s @@ -0,0 +1,25 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + + +// ------------------------------------------------------------------------- // +// Invalid scalar registers + +whilewr p15.b, xzr, sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, xzr, sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, xzr, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, xzr, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, w0, x0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, w0, x0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +whilewr p15.b, w0, w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: whilewr p15.b, w0, w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/whilewr.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/whilewr.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +whilewr p15.b, x30, x30 +// CHECK-INST: whilewr p15.b, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0x3e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 3e 25 + +whilewr p15.h, x30, x30 +// CHECK-INST: whilewr p15.h, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0x7e,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 7e 25 + +whilewr p15.s, x30, x30 +// CHECK-INST: whilewr p15.s, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0xbe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 be 25 + +whilewr p15.d, x30, x30 +// CHECK-INST: whilewr p15.d, x30, x30 +// CHECK-ENCODING: [0xcf,0x33,0xfe,0x25] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: cf 33 fe 25 Index: test/MC/AArch64/SVE2/xar-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/xar-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s + +xar z30.b, z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: xar z30.b, z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z18.b, z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: xar z18.b, z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z26.h, z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: xar z26.h, z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z25.h, z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: xar z25.h, z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z17.s, z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: xar z17.s, z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z0.s, z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: xar z0.s, z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z4.d, z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: xar z4.d, z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +xar z26.d, z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: xar z26.d, z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +xar z0.b, z0.b , z0.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: xar z0.b, z0.b , z0.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.d, p0/z, z7.d +xar z0.d, z0.d, z1.d, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx +// CHECK-NEXT: xar z0.d, z0.d, z1.d, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: test/MC/AArch64/SVE2/xar.s =================================================================== --- /dev/null +++ test/MC/AArch64/SVE2/xar.s @@ -0,0 +1,72 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +xar z0.b, z0.b, z1.b, #1 +// CHECK-INST: xar z0.b, z0.b, z1.b, #1 +// CHECK-ENCODING: [0x20,0x34,0x2f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 34 2f 04 + +xar z31.b, z31.b, z30.b, #8 +// CHECK-INST: xar z31.b, z31.b, z30.b, #8 +// CHECK-ENCODING: [0xdf,0x37,0x28,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 37 28 04 + +xar z0.h, z0.h, z1.h, #1 +// CHECK-INST: xar z0.h, z0.h, z1.h, #1 +// CHECK-ENCODING: [0x20,0x34,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 34 3f 04 + +xar z31.h, z31.h, z30.h, #16 +// CHECK-INST: xar z31.h, z31.h, z30.h, #16 +// CHECK-ENCODING: [0xdf,0x37,0x30,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 37 30 04 + +xar z0.s, z0.s, z1.s, #1 +// CHECK-INST: xar z0.s, z0.s, z1.s, #1 +// CHECK-ENCODING: [0x20,0x34,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 34 7f 04 + +xar z31.s, z31.s, z30.s, #32 +// CHECK-INST: xar z31.s, z31.s, z30.s, #32 +// CHECK-ENCODING: [0xdf,0x37,0x60,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 37 60 04 + +xar z0.d, z0.d, z1.d, #1 +// CHECK-INST: xar z0.d, z0.d, z1.d, #1 +// CHECK-ENCODING: [0x20,0x34,0xff,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: 20 34 ff 04 + +xar z31.d, z31.d, z30.d, #64 +// CHECK-INST: xar z31.d, z31.d, z30.d, #64 +// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 37 a0 04 + + +// --------------------------------------------------------------------------// +// Test compatibility with MOVPRFX instruction. + +movprfx z31, z7 +// CHECK-INST: movprfx z31, z7 +// CHECK-ENCODING: [0xff,0xbc,0x20,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff bc 20 04 + +xar z31.d, z31.d, z30.d, #64 +// CHECK-INST: xar z31.d, z31.d, z30.d, #64 +// CHECK-ENCODING: [0xdf,0x37,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve2 +// CHECK-UNKNOWN: df 37 a0 04 Index: unittests/Support/TargetParserTest.cpp =================================================================== --- unittests/Support/TargetParserTest.cpp +++ unittests/Support/TargetParserTest.cpp @@ -1014,8 +1014,8 @@ AArch64::AEK_FP16 | AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_SVE | - AArch64::AEK_DOTPROD | AArch64::AEK_RCPC | - AArch64::AEK_FP16FML; + AArch64::AEK_SVE2 | AArch64::AEK_DOTPROD | + AArch64::AEK_RCPC | AArch64::AEK_FP16FML; for (unsigned i = 0; i <= Extensions; i++) EXPECT_TRUE(i == 0 ? !AArch64::getExtensionFeatures(i, Features) @@ -1043,6 +1043,14 @@ {"lse", "nolse", "+lse", "-lse"}, {"rdm", "nordm", "+rdm", "-rdm"}, {"sve", "nosve", "+sve", "-sve"}, + {"sve2", "nosve2", "+sve2", "-sve2"}, + {"sve2-aes", "nosve2-aes", "+sve2-aes", + "-sve2-aes"}, + {"sve2-sm4", "nosve2-sm4", "+sve2-sm4", + "-sve2-sm4"}, + {"sve2-sha3", "nosve2-sha3", "+sve2-sha3", + "-sve2-sha3"}, + {"bitperm", "nobitperm", "+bitperm", "-bitperm"}, {"dotprod", "nodotprod", "+dotprod", "-dotprod"}, {"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rng", "norng", "+rand", "-rand"},