Index: include/llvm/Target/TargetLowering.h =================================================================== --- include/llvm/Target/TargetLowering.h +++ include/llvm/Target/TargetLowering.h @@ -137,10 +137,10 @@ llvm_unreachable("Invalid content kind"); } - /// NOTE: The constructor takes ownership of TLOF. + /// NOTE: The TargetMachine owns TLOF. explicit TargetLoweringBase(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF); - virtual ~TargetLoweringBase(); + virtual ~TargetLoweringBase() {} protected: /// \brief Initialize all of the actions to default values. Index: include/llvm/Target/TargetMachine.h =================================================================== --- include/llvm/Target/TargetMachine.h +++ include/llvm/Target/TargetMachine.h @@ -44,6 +44,7 @@ class VectorTargetTransformInfo; class formatted_raw_ostream; class raw_ostream; +class TargetLoweringObjectFile; // The old pass manager infrastructure is hidden in a legacy namespace now. namespace legacy { @@ -102,6 +103,9 @@ virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const { return getSubtargetImpl(); } + virtual TargetLoweringObjectFile *getObjFileLowering() const { + return nullptr; + } /// getSubtarget - This method returns a pointer to the specified type of /// TargetSubtargetInfo. In debug builds, it verifies that the object being Index: lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- lib/CodeGen/TargetLoweringBase.cpp +++ lib/CodeGen/TargetLoweringBase.cpp @@ -737,10 +737,6 @@ InitLibcallCallingConvs(LibcallCallingConvs); } -TargetLoweringBase::~TargetLoweringBase() { - delete &TLOF; -} - void TargetLoweringBase::initActions() { // All operations default to being supported. memset(OpActions, 0, sizeof(OpActions)); Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -66,18 +66,8 @@ cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false)); -//===----------------------------------------------------------------------===// -// AArch64 Lowering public interface. -//===----------------------------------------------------------------------===// -static TargetLoweringObjectFile *createTLOF(const Triple &TT) { - if (TT.isOSBinFormatMachO()) - return new AArch64_MachoTargetObjectFile(); - - return new AArch64_ELFTargetObjectFile(); -} - AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM) - : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) { + : TargetLowering(TM, TM.getObjFileLowering()) { Subtarget = &TM.getSubtarget(); // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so @@ -2060,7 +2050,7 @@ continue; } - + if (VA.isRegLoc()) { // Arguments stored in registers. EVT RegVT = VA.getLocVT(); @@ -4755,7 +4745,7 @@ // The index of an EXT is the first element if it is not UNDEF. // Watch out for the beginning UNDEFs. The EXT index should be the expected - // value of the first element. E.g. + // value of the first element. E.g. // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>. // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>. // ExpectedElt is the last mask index plus 1. Index: lib/Target/AArch64/AArch64TargetMachine.h =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.h +++ lib/Target/AArch64/AArch64TargetMachine.h @@ -23,6 +23,7 @@ class AArch64TargetMachine : public LLVMTargetMachine { protected: + std::unique_ptr TLOF; AArch64Subtarget Subtarget; mutable StringMap> SubtargetMap; @@ -43,6 +44,10 @@ /// \brief Register AArch64 analysis passes with a pass manager. void addAnalysisPasses(PassManagerBase &PM) override; + TargetLoweringObjectFile* getObjFileLowering() const override { + return TLOF.get(); + } + private: bool isLittle; }; Index: lib/Target/AArch64/AArch64TargetMachine.cpp =================================================================== --- lib/Target/AArch64/AArch64TargetMachine.cpp +++ lib/Target/AArch64/AArch64TargetMachine.cpp @@ -12,6 +12,7 @@ #include "AArch64.h" #include "AArch64TargetMachine.h" +#include "AArch64TargetObjectFile.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/IR/Function.h" @@ -87,6 +88,16 @@ RegisterTargetMachine Z(TheARM64Target); } +//===----------------------------------------------------------------------===// +// AArch64 Lowering public interface. +//===----------------------------------------------------------------------===// +static std::unique_ptr createTLOF(const Triple &TT) { + if (TT.isOSBinFormatMachO()) + return make_unique(); + + return make_unique(); +} + /// TargetMachine ctor - Create an AArch64 architecture model. /// AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT, @@ -96,6 +107,7 @@ CodeGenOpt::Level OL, bool LittleEndian) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(createTLOF(Triple(getTargetTriple()))), Subtarget(TT, CPU, FS, *this, LittleEndian), isLittle(LittleEndian) { initAsmInfo(); } Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -156,16 +156,8 @@ addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); } -static TargetLoweringObjectFile *createTLOF(const Triple &TT) { - if (TT.isOSBinFormatMachO()) - return new TargetLoweringObjectFileMachO(); - if (TT.isOSWindows()) - return new TargetLoweringObjectFileCOFF(); - return new ARMElfTargetObjectFile(); -} - ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM) - : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) { + : TargetLowering(TM, TM.getObjFileLowering()) { Subtarget = &TM.getSubtarget(); RegInfo = TM.getSubtargetImpl()->getRegisterInfo(); Itins = TM.getSubtargetImpl()->getInstrItineraryData(); @@ -7970,7 +7962,7 @@ // Get widened type and narrowed type. MVT widenType; unsigned numElem = VT.getVectorNumElements(); - + EVT inputLaneType = Vec.getValueType().getVectorElementType(); switch (inputLaneType.getSimpleVT().SimpleTy) { case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; Index: lib/Target/ARM/ARMTargetMachine.h =================================================================== --- lib/Target/ARM/ARMTargetMachine.h +++ lib/Target/ARM/ARMTargetMachine.h @@ -23,6 +23,7 @@ class ARMBaseTargetMachine : public LLVMTargetMachine { protected: + std::unique_ptr TLOF; ARMSubtarget Subtarget; bool isLittle; mutable StringMap> SubtargetMap; @@ -43,6 +44,10 @@ // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// ARMTargetMachine - ARM target machine. Index: lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- lib/Target/ARM/ARMTargetMachine.cpp +++ lib/Target/ARM/ARMTargetMachine.cpp @@ -13,6 +13,7 @@ #include "ARM.h" #include "ARMTargetMachine.h" #include "ARMFrameLowering.h" +#include "ARMTargetObjectFile.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCAsmInfo.h" @@ -43,6 +44,14 @@ RegisterTargetMachine B(TheThumbBETarget); } +static std::unique_ptr createTLOF(const Triple &TT) { + if (TT.isOSBinFormatMachO()) + return make_unique(); + if (TT.isOSWindows()) + return make_unique(); + return make_unique(); +} + /// TargetMachine ctor - Create an ARM architecture model. /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, @@ -51,6 +60,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(createTLOF(Triple(getTargetTriple()))), Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { // Default to triple-appropriate float ABI Index: lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonISelLowering.cpp +++ lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1043,7 +1043,7 @@ //===----------------------------------------------------------------------===// HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine) - : TargetLowering(targetmachine, new HexagonTargetObjectFile()), + : TargetLowering(targetmachine, targetmachine.getObjFileLowering()), TM(targetmachine) { const HexagonSubtarget &Subtarget = TM.getSubtarget(); Index: lib/Target/Hexagon/HexagonTargetMachine.h =================================================================== --- lib/Target/Hexagon/HexagonTargetMachine.h +++ lib/Target/Hexagon/HexagonTargetMachine.h @@ -23,6 +23,7 @@ class Module; class HexagonTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; HexagonSubtarget Subtarget; public: @@ -37,6 +38,10 @@ static unsigned getModuleMatchQuality(const Module &M); TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; extern bool flag_aligned_memcpy; Index: lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- lib/Target/Hexagon/HexagonTargetMachine.cpp +++ lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -70,6 +70,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } Index: lib/Target/MSP430/MSP430ISelLowering.cpp =================================================================== --- lib/Target/MSP430/MSP430ISelLowering.cpp +++ lib/Target/MSP430/MSP430ISelLowering.cpp @@ -58,7 +58,7 @@ clEnumValEnd)); MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) - : TargetLowering(TM, new TargetLoweringObjectFileELF()) { + : TargetLowering(TM, TM.getObjFileLowering()) { // Set up the register classes. addRegisterClass(MVT::i8, &MSP430::GR8RegClass); Index: lib/Target/MSP430/MSP430TargetMachine.h =================================================================== --- lib/Target/MSP430/MSP430TargetMachine.h +++ lib/Target/MSP430/MSP430TargetMachine.h @@ -24,6 +24,7 @@ /// MSP430TargetMachine /// class MSP430TargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; MSP430Subtarget Subtarget; public: @@ -36,6 +37,10 @@ return &Subtarget; } TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; // MSP430TargetMachine. } // end namespace llvm Index: lib/Target/MSP430/MSP430TargetMachine.cpp =================================================================== --- lib/Target/MSP430/MSP430TargetMachine.cpp +++ lib/Target/MSP430/MSP430TargetMachine.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "MSP430TargetMachine.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "MSP430.h" #include "llvm/CodeGen/Passes.h" #include "llvm/MC/MCAsmInfo.h" @@ -30,6 +31,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -320,7 +320,7 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI) - : TargetLowering(TM, new MipsTargetObjectFile()), Subtarget(STI) { + : TargetLowering(TM, TM.getObjFileLowering()), Subtarget(STI) { // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). setBooleanContents(ZeroOrOneBooleanContent); Index: lib/Target/Mips/MipsTargetMachine.h =================================================================== --- lib/Target/Mips/MipsTargetMachine.h +++ lib/Target/Mips/MipsTargetMachine.h @@ -26,6 +26,7 @@ class MipsTargetMachine : public LLVMTargetMachine { bool isLittle; + std::unique_ptr TLOF; MipsSubtarget *Subtarget; MipsSubtarget DefaultSubtarget; MipsSubtarget NoMips16Subtarget; @@ -38,8 +39,6 @@ const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); - virtual ~MipsTargetMachine() {} - void addAnalysisPasses(PassManagerBase &PM) override; const MipsSubtarget *getSubtargetImpl() const override { @@ -55,6 +54,10 @@ // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// MipsebTargetMachine - Mips32/64 big endian target machine. Index: lib/Target/Mips/MipsTargetMachine.cpp =================================================================== --- lib/Target/Mips/MipsTargetMachine.cpp +++ lib/Target/Mips/MipsTargetMachine.cpp @@ -26,6 +26,7 @@ #include "MipsSEISelDAGToDAG.h" #include "MipsSEISelLowering.h" #include "MipsSEInstrInfo.h" +#include "MipsTargetObjectFile.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/PassManager.h" @@ -56,7 +57,9 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - isLittle(isLittle), Subtarget(nullptr), + isLittle(isLittle), + TLOF(make_unique()), + Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, this), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, this), Index: lib/Target/NVPTX/NVPTXISelLowering.cpp =================================================================== --- lib/Target/NVPTX/NVPTXISelLowering.cpp +++ lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -107,7 +107,7 @@ // NVPTXTargetLowering Constructor. NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM) - : TargetLowering(TM, new NVPTXTargetObjectFile()), nvTM(&TM), + : TargetLowering(TM, TM.getObjFileLowering()), nvTM(&TM), nvptxSubtarget(TM.getSubtarget()) { // always lower memset, memcpy, and memmove intrinsics to load/store @@ -2143,7 +2143,7 @@ partVT.getTypeForEVT(F->getContext())); SDValue p; if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) { - ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? + ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, MachinePointerInfo(srcValue), partVT, false, @@ -2270,7 +2270,7 @@ ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM)); SDValue p; if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) { - ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? + ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue), ObjectVT, false, false, Index: lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.h +++ lib/Target/NVPTX/NVPTXTargetMachine.h @@ -25,6 +25,7 @@ /// NVPTXTargetMachine /// class NVPTXTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; NVPTXSubtarget Subtarget; // Hold Strings that can be free'd all together with NVPTXTargetMachine @@ -48,6 +49,9 @@ bool = true) override { return true; } + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; // NVPTXTargetMachine. Index: lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -16,6 +16,7 @@ #include "NVPTX.h" #include "NVPTXAllocaHoisting.h" #include "NVPTXLowerAggrCopies.h" +#include "NVPTXTargetObjectFile.h" #include "llvm/Analysis/Passes.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" @@ -74,6 +75,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -55,17 +55,8 @@ // FIXME: Remove this once the bug has been fixed! extern cl::opt ANDIGlueBug; -static TargetLoweringObjectFile *createTLOF(const Triple &TT) { - // If it isn't a Mach-O file then it's going to be a linux ELF - // object file. - if (TT.isOSDarwin()) - return new TargetLoweringObjectFileMachO(); - - return new PPC64LinuxTargetObjectFile(); -} - PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM) - : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))), + : TargetLowering(TM, TM.getObjFileLowering()), Subtarget(*TM.getSubtargetImpl()) { setPow2SDivIsCheap(); @@ -109,7 +100,7 @@ AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32); setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); - AddPromotedToType (ISD::UINT_TO_FP, MVT::i1, + AddPromotedToType (ISD::UINT_TO_FP, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32); } else { setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); @@ -942,7 +933,7 @@ /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes). -/// The ShuffleKind distinguishes between big-endian merges with two +/// The ShuffleKind distinguishes between big-endian merges with two /// different inputs (0), either-endian merges with two identical inputs (1), /// and little-endian merges with two different inputs (2). For the latter, /// the input operands are swapped (see PPCInstrAltivec.td). @@ -967,7 +958,7 @@ /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes). -/// The ShuffleKind distinguishes between big-endian merges with two +/// The ShuffleKind distinguishes between big-endian merges with two /// different inputs (0), either-endian merges with two identical inputs (1), /// and little-endian merges with two different inputs (2). For the latter, /// the input operands are swapped (see PPCInstrAltivec.td). @@ -993,7 +984,7 @@ /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. -/// The ShuffleKind distinguishes between big-endian operations with two +/// The ShuffleKind distinguishes between big-endian operations with two /// different inputs (0), either-endian operations with two identical inputs /// (1), and little-endian operations with two different inputs (2). For the /// latter, the input operands are swapped (see PPCInstrAltivec.td). @@ -2131,7 +2122,7 @@ #include "PPCGenCallingConv.inc" -// Function whose sole purpose is to kill compiler warnings +// Function whose sole purpose is to kill compiler warnings // stemming from unused functions included from PPCGenCallingConv.inc. CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const { return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS; @@ -6492,7 +6483,7 @@ EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0)); SDVTList VTs = DAG.getVTList(SVT, MVT::Other); SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0), - N->getOperand(1)); + N->getOperand(1)); Results.push_back(NewInt); Results.push_back(NewInt.getValue(1)); @@ -7654,7 +7645,7 @@ for (SmallSet::iterator I = LoadRoots.begin(), IE = LoadRoots.end(); I != IE; ++I) { Queue.push_back(*I); - + while (!Queue.empty()) { SDNode *LoadRoot = Queue.pop_back_val(); if (!Visited.insert(LoadRoot)) @@ -7782,7 +7773,7 @@ } // Visit all inputs, collect all binary operations (and, or, xor and - // select) that are all fed by extensions. + // select) that are all fed by extensions. while (!BinOps.empty()) { SDValue BinOp = BinOps.back(); BinOps.pop_back(); @@ -7804,7 +7795,7 @@ BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) && BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || isa(BinOp.getOperand(i))) { - Inputs.push_back(BinOp.getOperand(i)); + Inputs.push_back(BinOp.getOperand(i)); } else if (BinOp.getOperand(i).getOpcode() == ISD::AND || BinOp.getOperand(i).getOpcode() == ISD::OR || BinOp.getOperand(i).getOpcode() == ISD::XOR || @@ -7884,7 +7875,7 @@ if (isa(Inputs[i])) continue; else - DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0)); + DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0)); } // Replace all operations (these are all the same, but have a different @@ -7996,7 +7987,7 @@ SmallPtrSet Visited; // Visit all inputs, collect all binary operations (and, or, xor and - // select) that are all fed by truncations. + // select) that are all fed by truncations. while (!BinOps.empty()) { SDValue BinOp = BinOps.back(); BinOps.pop_back(); @@ -8015,7 +8006,7 @@ if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE || isa(BinOp.getOperand(i))) { - Inputs.push_back(BinOp.getOperand(i)); + Inputs.push_back(BinOp.getOperand(i)); } else if (BinOp.getOperand(i).getOpcode() == ISD::AND || BinOp.getOperand(i).getOpcode() == ISD::OR || BinOp.getOperand(i).getOpcode() == ISD::XOR || @@ -8199,7 +8190,7 @@ EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0)); SDValue ShiftCst = DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy); - return DAG.getNode(ISD::SRA, dl, N->getValueType(0), + return DAG.getNode(ISD::SRA, dl, N->getValueType(0), DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst), ShiftCst); } @@ -8232,7 +8223,7 @@ break; case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: - case ISD::ANY_EXTEND: + case ISD::ANY_EXTEND: return DAGCombineExtBoolTrunc(N, DCI); case ISD::TRUNCATE: case ISD::SETCC: @@ -8566,7 +8557,7 @@ case ISD::BRCOND: { SDValue Cond = N->getOperand(1); SDValue Target = N->getOperand(2); - + if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN && cast(Cond.getOperand(1))->getZExtValue() == Intrinsic::ppc_is_decremented_ctr_nonzero) { Index: lib/Target/PowerPC/PPCTargetMachine.h =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.h +++ lib/Target/PowerPC/PPCTargetMachine.h @@ -24,6 +24,7 @@ /// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets. /// class PPCTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; PPCSubtarget Subtarget; mutable StringMap> SubtargetMap; @@ -42,6 +43,9 @@ /// \brief Register PPC analysis passes with a pass manager. void addAnalysisPasses(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// PPC32TargetMachine - PowerPC 32-bit target machine. Index: lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.cpp +++ lib/Target/PowerPC/PPCTargetMachine.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "PPCTargetMachine.h" +#include "PPCTargetObjectFile.h" #include "PPC.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" @@ -60,6 +61,15 @@ return FullFS; } +static std::unique_ptr createTLOF(const Triple &TT) { + // If it isn't a Mach-O file then it's going to be a linux ELF + // object file. + if (TT.isOSDarwin()) + return make_unique(); + + return make_unique(); +} + // The FeatureString here is a little subtle. We are modifying the feature string // with what are (currently) non-function specific overrides as it goes into the // LLVMTargetMachine constructor and then using the stored value in the @@ -70,6 +80,7 @@ CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM, CM, OL), + TLOF(createTLOF(Triple(getTargetTriple()))), Subtarget(TT, CPU, TargetFS, *this) { initAsmInfo(); } @@ -214,4 +225,3 @@ PM.add(createBasicTargetTransformInfoPass(this)); PM.add(createPPCTargetTransformInfoPass(this)); } - Index: lib/Target/R600/AMDGPUISelLowering.cpp =================================================================== --- lib/Target/R600/AMDGPUISelLowering.cpp +++ lib/Target/R600/AMDGPUISelLowering.cpp @@ -103,7 +103,7 @@ } AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : - TargetLowering(TM, new TargetLoweringObjectFileELF()) { + TargetLowering(TM, TM.getObjFileLowering()) { Subtarget = &TM.getSubtarget(); Index: lib/Target/R600/AMDGPUTargetMachine.h =================================================================== --- lib/Target/R600/AMDGPUTargetMachine.h +++ lib/Target/R600/AMDGPUTargetMachine.h @@ -25,6 +25,7 @@ namespace llvm { class AMDGPUTargetMachine : public LLVMTargetMachine { + TargetLoweringObjectFile *TLOF; AMDGPUSubtarget Subtarget; AMDGPUIntrinsicInfo IntrinsicInfo; @@ -43,6 +44,9 @@ /// \brief Register R600 analysis passes with a pass manager. void addAnalysisPasses(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF; + } }; } // End namespace llvm Index: lib/Target/R600/AMDGPUTargetMachine.cpp =================================================================== --- lib/Target/R600/AMDGPUTargetMachine.cpp +++ lib/Target/R600/AMDGPUTargetMachine.cpp @@ -22,6 +22,7 @@ #include "SIInstrInfo.h" #include "llvm/Analysis/Passes.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Verifier.h" @@ -54,12 +55,14 @@ CodeModel::Model CM, CodeGenOpt::Level OptLevel) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel), + TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this), IntrinsicInfo() { setRequiresStructuredCFG(true); initAsmInfo(); } AMDGPUTargetMachine::~AMDGPUTargetMachine() { + delete TLOF; } namespace { Index: lib/Target/Sparc/SparcISelLowering.cpp =================================================================== --- lib/Target/Sparc/SparcISelLowering.cpp +++ lib/Target/Sparc/SparcISelLowering.cpp @@ -1366,7 +1366,7 @@ } SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM, new SparcELFTargetObjectFile()) { + : TargetLowering(TM, TM.getObjFileLowering()) { Subtarget = &TM.getSubtarget(); // Set up the register classes. Index: lib/Target/Sparc/SparcTargetMachine.h =================================================================== --- lib/Target/Sparc/SparcTargetMachine.h +++ lib/Target/Sparc/SparcTargetMachine.h @@ -21,6 +21,7 @@ namespace llvm { class SparcTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; SparcSubtarget Subtarget; public: SparcTargetMachine(const Target &T, StringRef TT, @@ -32,6 +33,9 @@ // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// SparcV8TargetMachine - Sparc 32-bit target machine Index: lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- lib/Target/Sparc/SparcTargetMachine.cpp +++ lib/Target/Sparc/SparcTargetMachine.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "SparcTargetMachine.h" +#include "SparcTargetObjectFile.h" #include "Sparc.h" #include "llvm/CodeGen/Passes.h" #include "llvm/PassManager.h" @@ -32,6 +33,7 @@ CodeGenOpt::Level OL, bool is64bit) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } Index: lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.cpp +++ lib/Target/SystemZ/SystemZISelLowering.cpp @@ -81,7 +81,7 @@ } SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm) - : TargetLowering(tm, new TargetLoweringObjectFileELF()), + : TargetLowering(tm, tm.getObjFileLowering()), Subtarget(tm.getSubtarget()) { MVT PtrVT = getPointerTy(); Index: lib/Target/SystemZ/SystemZTargetMachine.h =================================================================== --- lib/Target/SystemZ/SystemZTargetMachine.h +++ lib/Target/SystemZ/SystemZTargetMachine.h @@ -23,6 +23,7 @@ class TargetFrameLowering; class SystemZTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; SystemZSubtarget Subtarget; public: @@ -37,6 +38,9 @@ } // Override LLVMTargetMachine TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; } // end namespace llvm Index: lib/Target/SystemZ/SystemZTargetMachine.cpp =================================================================== --- lib/Target/SystemZ/SystemZTargetMachine.cpp +++ lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -11,6 +11,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Transforms/Scalar.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" using namespace llvm; @@ -25,6 +26,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -193,28 +193,11 @@ return Insert256BitVector(V, V2, NumElems/2, DAG, dl); } -static TargetLoweringObjectFile *createTLOF(const Triple &TT) { - if (TT.isOSBinFormatMachO()) { - if (TT.getArch() == Triple::x86_64) - return new X86_64MachoTargetObjectFile(); - return new TargetLoweringObjectFileMachO(); - } - if (TT.isOSLinux()) - return new X86LinuxTargetObjectFile(); - if (TT.isOSBinFormatELF()) - return new TargetLoweringObjectFileELF(); - if (TT.isKnownWindowsMSVCEnvironment()) - return new X86WindowsTargetObjectFile(); - if (TT.isOSBinFormatCOFF()) - return new TargetLoweringObjectFileCOFF(); - llvm_unreachable("unknown subtarget type"); -} - // FIXME: This should stop caching the target machine as soon as // we can remove resetOperationActions et al. X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM) - : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) { + : TargetLowering(TM, TM.getObjFileLowering()) { Subtarget = &TM.getSubtarget(); X86ScalarSSEf64 = Subtarget->hasSSE2(); X86ScalarSSEf32 = Subtarget->hasSSE1(); @@ -2008,7 +1991,7 @@ ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy); assert(VA.getLocInfo() != CCValAssign::FPExt && - "Unexpected FP-extend for return value."); + "Unexpected FP-extend for return value."); // If this is x86-64, and we disabled SSE, we can't return FP values, // or SSE or MMX vectors. @@ -6324,7 +6307,7 @@ MVT::getIntegerVT(VT.getSizeInBits())); DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm); } - else + else DstVec = DAG.getUNDEF(VT); return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, Op.getOperand(NonConstIdx), @@ -6347,7 +6330,7 @@ /// \brief Return true if \p N implements a horizontal binop and return the /// operands for the horizontal binop into V0 and V1. -/// +/// /// This is a helper function of PerformBUILD_VECTORCombine. /// This function checks that the build_vector \p N in input implements a /// horizontal operation. Parameter \p Opcode defines the kind of horizontal @@ -6368,7 +6351,7 @@ assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!"); assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx && "Invalid Vector in input!"); - + bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD); bool CanFold = true; unsigned ExpectedVExtractIdx = BaseIdx; @@ -6437,13 +6420,13 @@ } /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by -/// a concat_vector. +/// a concat_vector. /// /// This is a helper function of PerformBUILD_VECTORCombine. /// This function expects two 256-bit vectors called V0 and V1. /// At first, each vector is split into two separate 128-bit vectors. /// Then, the resulting 128-bit vectors are used to implement two -/// horizontal binary operations. +/// horizontal binary operations. /// /// The kind of horizontal binary operation is defined by \p X86Opcode. /// @@ -6637,18 +6620,18 @@ // Try to match an SSE3 float HADD/HSUB. if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1)) return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1); - + if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1)) return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1); } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) { // Try to match an SSSE3 integer HADD/HSUB. if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1)) return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1); - + if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1)) return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1); } - + if (!Subtarget->hasAVX()) return SDValue(); @@ -6699,7 +6682,7 @@ // Do this only if the target has AVX2. if (Subtarget->hasAVX2()) return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1); - + // Do not try to expand this build_vector into a pair of horizontal // add/sub if we can emit a pair of scalar add/sub. if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half) @@ -7453,9 +7436,9 @@ /// does not check for the availability of PALIGNR-based lowerings, only the /// applicability of this strategy to the given mask. This matches shuffle /// vectors that look like: -/// +/// /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2] -/// +/// /// Essentially it concatenates V1 and V2, shifts right by some number of /// elements, and takes the low elements as the result. Note that while this is /// specified as a *right shift* because x86 is little-endian, it is a *left @@ -12355,7 +12338,7 @@ /// Insert one bit to mask vector, like v16i1 or v8i1. /// AVX-512 feature. -SDValue +SDValue X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); SDValue Vec = Op.getOperand(0); @@ -12368,7 +12351,7 @@ // insert element and then truncate the result. MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32); MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32); - SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, + SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec), DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx); return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); @@ -13639,7 +13622,7 @@ In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); InVT = ExtVT; } - + SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType()); const Constant *C = (dyn_cast(Cst))->getConstantIntValue(); SDValue CP = DAG.getConstantPool(C, getPointerTy()); @@ -13833,7 +13816,7 @@ EltVT = VT.getVectorElementType(); NumElts = VT.getVectorNumElements(); } - + unsigned EltBits = EltVT.getSizeInBits(); LLVMContext *Context = DAG.getContext(); // For FABS, mask is 0x7f...; for FNEG, mask is 0x80... @@ -13860,7 +13843,7 @@ return DAG.getNode(ISD::BITCAST, dl, VT, DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted)); } - + // If not vector, then scalar. unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR; SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0; @@ -14317,12 +14300,12 @@ if (Op0.getValueType() == MVT::i1) llvm_unreachable("Unexpected comparison operation for MVT::i1 operands"); } - + if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { - // Do the comparison at i32 if it's smaller, besides the Atom case. - // This avoids subregister aliasing issues. Keep the smaller reference - // if we're optimizing for size, however, as that'll allow better folding + // Do the comparison at i32 if it's smaller, besides the Atom case. + // This avoids subregister aliasing issues. Keep the smaller reference + // if we're optimizing for size, however, as that'll allow better folding // of memory operations. if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 && !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute( @@ -14380,7 +14363,7 @@ return SDValue(); EVT VT = Op.getValueType(); - + // SSE1 has rsqrtss and rsqrtps. // TODO: Add support for AVX512 (v16f32). // It is likely not profitable to do this for f64 because a double-precision @@ -15200,11 +15183,11 @@ ((Subtarget->hasDQI() && Subtarget->hasVLX() && VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) || - + ((Subtarget->hasDQI() && VT.is512BitVector() && VTElt.getSizeInBits() >= 32)))) return DAG.getNode(X86ISD::VSEXT, dl, VT, In); - + unsigned int NumElts = VT.getVectorNumElements(); if (NumElts != 8 && NumElts != 16) @@ -16852,7 +16835,7 @@ switch(IntrData->Type) { default: llvm_unreachable("Unknown Intrinsic Type"); - break; + break; case RDSEED: case RDRAND: { // Emit the node with the right value type. @@ -17962,7 +17945,7 @@ // If possible, lower this packed shift into a vector multiply instead of // expanding it into a sequence of scalar shifts. // Do this only if the vector shift count is a constant build_vector. - if (Op.getOpcode() == ISD::SHL && + if (Op.getOpcode() == ISD::SHL && (VT == MVT::v8i16 || VT == MVT::v4i32 || (Subtarget->hasInt256() && VT == MVT::v16i16)) && ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) { @@ -18054,15 +18037,15 @@ CanBeSimplified = Amt2 == Amt->getOperand(j); } } - + if (CanBeSimplified && isa(Amt1) && isa(Amt2)) { // Replace this node with two shifts followed by a MOVSS/MOVSD. EVT CastVT = MVT::v4i32; - SDValue Splat1 = + SDValue Splat1 = DAG.getConstant(cast(Amt1)->getAPIntValue(), VT); SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1); - SDValue Splat2 = + SDValue Splat2 = DAG.getConstant(cast(Amt2)->getAPIntValue(), VT); SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2); if (TargetOpcode == X86ISD::MOVSD) @@ -20436,7 +20419,7 @@ // Replace 213-type (isel default) FMA3 instructions with 231-type for // accumulator loops. Writing back to the accumulator allows the coalescer -// to remove extra copies in the loop. +// to remove extra copies in the loop. MachineBasicBlock * X86TargetLowering::emitFMA3Instr(MachineInstr *MI, MachineBasicBlock *MBB) const { @@ -21700,7 +21683,7 @@ EVT SVT = BC0.getValueType(); unsigned Opcode = BC0.getOpcode(); unsigned NumElts = VT.getVectorNumElements(); - + if (BC0.hasOneUse() && SVT.isVector() && SVT.getVectorNumElements() * 2 == NumElts && TLI.isOperationLegal(Opcode, VT)) { @@ -22541,7 +22524,7 @@ unsigned NumElems = Cond.getNumOperands(); SDValue A = LHS; SDValue B = RHS; - + if (isZero(Cond.getOperand(0))) { CanFold = true; @@ -23019,7 +23002,7 @@ // fold (blend A, B, allOnes) -> B if (ISD::isBuildVectorAllOnes(Mask.getNode())) return Op1; - + // Simplify the case where the mask is a constant i32 value. if (ConstantSDNode *C = dyn_cast(Mask)) { if (C->isNullValue()) @@ -25686,7 +25669,7 @@ // "load" ports instead of the dedicated "store" port. // E.g., on Haswell: // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3. - // vmovaps %ymm1, (%r8) can use port 2, 3, or 7. + // vmovaps %ymm1, (%r8) can use port 2, 3, or 7. if (isLegalAddressingMode(AM, Ty)) // Scale represents reg2 * scale, thus account for 1 // as soon as we use a second register. Index: lib/Target/X86/X86TargetMachine.h =================================================================== --- lib/Target/X86/X86TargetMachine.h +++ lib/Target/X86/X86TargetMachine.h @@ -24,6 +24,7 @@ class X86TargetMachine final : public LLVMTargetMachine { virtual void anchor(); + std::unique_ptr TLOF; X86Subtarget Subtarget; mutable StringMap> SubtargetMap; @@ -41,6 +42,9 @@ // Set up the pass pipeline. TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; } // End llvm namespace Index: lib/Target/X86/X86TargetMachine.cpp =================================================================== --- lib/Target/X86/X86TargetMachine.cpp +++ lib/Target/X86/X86TargetMachine.cpp @@ -13,6 +13,7 @@ #include "X86TargetMachine.h" #include "X86.h" +#include "X86TargetObjectFile.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/PassManager.h" @@ -30,6 +31,24 @@ void X86TargetMachine::anchor() { } +static std::unique_ptr createTLOF(const Triple &TT) { + if (TT.isOSBinFormatMachO()) { + if (TT.getArch() == Triple::x86_64) + return make_unique(); + return make_unique(); + } + + if (TT.isOSLinux()) + return make_unique(); + if (TT.isOSBinFormatELF()) + return make_unique(); + if (TT.isKnownWindowsMSVCEnvironment()) + return make_unique(); + if (TT.isOSBinFormatCOFF()) + return make_unique(); + llvm_unreachable("unknown subtarget type"); +} + /// X86TargetMachine ctor - Create an X86 target. /// X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, @@ -37,6 +56,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(createTLOF(Triple(getTargetTriple()))), Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { // default to hard float ABI if (Options.FloatABIType == FloatABI::Default) Index: lib/Target/XCore/XCoreISelLowering.cpp =================================================================== --- lib/Target/XCore/XCoreISelLowering.cpp +++ lib/Target/XCore/XCoreISelLowering.cpp @@ -69,7 +69,7 @@ } XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM) - : TargetLowering(TM, new XCoreTargetObjectFile()), TM(TM), + : TargetLowering(TM, TM.getObjFileLowering()), TM(TM), Subtarget(TM.getSubtarget()) { // Set up the register classes. Index: lib/Target/XCore/XCoreTargetMachine.h =================================================================== --- lib/Target/XCore/XCoreTargetMachine.h +++ lib/Target/XCore/XCoreTargetMachine.h @@ -20,6 +20,7 @@ namespace llvm { class XCoreTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; XCoreSubtarget Subtarget; public: XCoreTargetMachine(const Target &T, StringRef TT, @@ -33,6 +34,9 @@ TargetPassConfig *createPassConfig(PassManagerBase &PM) override; void addAnalysisPasses(PassManagerBase &PM) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; } // end namespace llvm Index: lib/Target/XCore/XCoreTargetMachine.cpp =================================================================== --- lib/Target/XCore/XCoreTargetMachine.cpp +++ lib/Target/XCore/XCoreTargetMachine.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "XCoreTargetMachine.h" +#include "XCoreTargetObjectFile.h" #include "XCore.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/Module.h" @@ -26,6 +27,7 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); }