Index: lib/Target/Hexagon/CMakeLists.txt =================================================================== --- lib/Target/Hexagon/CMakeLists.txt +++ lib/Target/Hexagon/CMakeLists.txt @@ -1,5 +1,6 @@ set(LLVM_TARGET_DEFINITIONS Hexagon.td) +tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter) @@ -41,4 +42,5 @@ add_subdirectory(TargetInfo) add_subdirectory(InstPrinter) add_subdirectory(MCTargetDesc) +add_subdirectory(Disassembler) Index: lib/Target/Hexagon/Disassembler/CMakeLists.txt =================================================================== --- lib/Target/Hexagon/Disassembler/CMakeLists.txt +++ lib/Target/Hexagon/Disassembler/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMHexagonDisassembler + HexagonDisassembler.cpp + ) Index: lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp =================================================================== --- lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -0,0 +1,131 @@ +//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/HexagonBaseInfo.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" + +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/LEB128.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/Endian.h" + +#include +#include + +using namespace llvm; + +#define DEBUG_TYPE "hexagon-disassembler" + +using DecodeStatus = MCDisassembler::DecodeStatus; + +namespace { +/// \brief Hexagon disassembler for all Hexagon platforms. +class HexagonDisassembler : public MCDisassembler { +public: + HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) + : MCDisassembler(STI, Ctx) {} + + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + MemoryObject const ®ion, uint64_t address, + raw_ostream &vStream, raw_ostream &cStream) const override; +}; +} + +static const uint16_t IntRegDecoderTable[] = { + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, + Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, + Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, + Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, + Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, + Hexagon::R30, Hexagon::R31}; + +static const uint16_t DoubleRegDecoderTable[] = { + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, + Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, + Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; + +static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, + Hexagon::P2, Hexagon::P3}; + +static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + + unsigned Register = IntRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 15) + return MCDisassembler::Fail; + + unsigned Register = DoubleRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + void const *Decoder) { + if (RegNo > 3) + return MCDisassembler::Fail; + + unsigned Register = PredRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + +#include "HexagonGenDisassemblerTables.inc" + +static MCDisassembler *createHexagonDisassembler(Target const &T, + MCSubtargetInfo const &STI, + MCContext &Ctx) { + return new HexagonDisassembler(STI, Ctx); +} + +extern "C" void LLVMInitializeHexagonDisassembler() { + TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, + createHexagonDisassembler); +} + +DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + MemoryObject const &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + std::array Bytes; + Size = 4; + if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) { + return MCDisassembler::Fail; + } + uint32_t insn = + llvm::support::endian::read(Bytes.data()); + + // Remove parse bits. + insn &= ~static_cast(HexagonII::InstParseBits::INST_PARSE_MASK); + return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); +} Index: lib/Target/Hexagon/Disassembler/LLVMBuild.txt =================================================================== --- lib/Target/Hexagon/Disassembler/LLVMBuild.txt +++ lib/Target/Hexagon/Disassembler/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===-- ./lib/Target/Hexagon/Disassembler/LLVMBuild.txt ---------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = HexagonDisassembler +parent = Hexagon +required_libraries = HexagonDesc MCDisassembler HexagonInfo Support +add_to_library_groups = Hexagon Index: lib/Target/Hexagon/Disassembler/Makefile =================================================================== --- lib/Target/Hexagon/Disassembler/Makefile +++ lib/Target/Hexagon/Disassembler/Makefile @@ -0,0 +1,16 @@ +##===-- lib/Target/Hexagon/Disassembler/Makefile -----------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMHexagonDisassembler + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common Index: lib/Target/Hexagon/HexagonInstrFormats.td =================================================================== --- lib/Target/Hexagon/HexagonInstrFormats.td +++ lib/Target/Hexagon/HexagonInstrFormats.td @@ -95,6 +95,12 @@ let Itinerary = itin; let Size = 4; + // SoftFail is a field the disassembler can use to provide a way for + // instructions to not match without killing the whole decode process. It is + // mainly used for ARM, but Tablegen expects this field to exist or it fails + // to build the decode table. + field bits<32> SoftFail = 0; + // *** Must match MCTargetDesc/HexagonBaseInfo.h *** // Instruction type according to the ISA. Index: lib/Target/Hexagon/LLVMBuild.txt =================================================================== --- lib/Target/Hexagon/LLVMBuild.txt +++ lib/Target/Hexagon/LLVMBuild.txt @@ -16,7 +16,7 @@ ;===------------------------------------------------------------------------===; [common] -subdirectories = InstPrinter MCTargetDesc TargetInfo +subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo [component_0] type = TargetGroup Index: lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -20,6 +20,8 @@ #include "HexagonMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" +#include + namespace llvm { /// HexagonII - This namespace holds all of the target specific flags that @@ -189,6 +191,15 @@ MO_GPREL }; + enum class InstParseBits : uint32_t { + INST_PARSE_MASK = 0x0000c000, + INST_PARSE_PACKET_END = 0x0000c000, + INST_PARSE_LOOP_END = 0x00008000, + INST_PARSE_NOT_END = 0x00004000, + INST_PARSE_DUPLEX = 0x00000000, + INST_PARSE_EXTENDER = 0x00000000 + }; + } // End namespace HexagonII. } // End namespace llvm. Index: lib/Target/Hexagon/Makefile =================================================================== --- lib/Target/Hexagon/Makefile +++ lib/Target/Hexagon/Makefile @@ -17,8 +17,9 @@ HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \ HexagonGenCallingConv.inc \ HexagonGenDFAPacketizer.inc \ - HexagonGenMCCodeEmitter.inc + HexagonGenMCCodeEmitter.inc \ + HexagonGenDisassemblerTables.inc -DIRS = InstPrinter TargetInfo MCTargetDesc +DIRS = InstPrinter TargetInfo MCTargetDesc Disassembler include $(LEVEL)/Makefile.common