Extend "idempotent" atomicrmw optimizations to floating point

[reames]

Summary

Caution: I am assuming the values used on ConstantExpr::getBinOpIdentity are correct. If someone with floating point knowledge can confirm, that'd be great.

Extend the integer transform in the obvious way. I decided not to cast to integer type to be conservative for the moment. Happy to reverse that if desired.

[jfb]

lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

33 ↗

(On Diff #186907)

@scanon for comment.

90 ↗

(On Diff #186907)

I think you want to canonicalize to integer or with zero a well, and have casts. It's still just a load at the end of the day.

[reames]

lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

33 ↗

(On Diff #186907)

@scanon ping on the FP question only

90 ↗

(On Diff #186907)

Can do so, but do you mind if I do that in a separate change just for risk reduction?

[jfb]

lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

90 ↗

(On Diff #186907)

Totally fine by me.

[reames]

Given no response from @scanon, and the constants appear elsewhere in LLVM fp transforms, I'd like to go ahead and land this. JF, how does that sound to you?

[jfb]

In D58251#1414587, @reames wrote:

Given no response from @scanon, and the constants appear elsewhere in LLVM fp transforms, I'd like to go ahead and land this. JF, how does that sound to you?

SGTM

llvm/trunk/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

 
 namespace {
 /// Return true if and only if the given instruction does not modify the memory
 /// location referenced.  Note that an idemptent atomicrmw may still have
 /// ordering effects on nearby instructions, or be volatile.
 /// TODO: Common w/ the version in AtomicExpandPass, and change the term used.
 /// Idemptotent is confusing in this context.
 bool isIdempotentRMW(AtomicRMWInst& RMWI) {
+  if (auto CF = dyn_cast<ConstantFP>(RMWI.getValOperand()))
+    switch(RMWI.getOperation()) {
+    case AtomicRMWInst::FAdd: // -0.0
+      return CF->isZero() && CF->isNegative();
+    case AtomicRMWInst::FSub: // +0.0
+      return CF->isZero() && !CF->isNegative();
+    default:
+      return false;
+    };
+  
   auto C = dyn_cast<ConstantInt>(RMWI.getValOperand());
   if(!C)
-    // TODO: Handle fadd, fsub?
     return false;
 
   switch(RMWI.getOperation()) {
     case AtomicRMWInst::Add:
     case AtomicRMWInst::Sub:
     case AtomicRMWInst::Or:
     case AtomicRMWInst::Xor:
       return C->isZero();
if (RMWI.getOperation() == AtomicRMWInst::Xchg &&
     return eraseInstFromFunction(RMWI);
   }
   
   if (!isIdempotentRMW(RMWI))
     return nullptr;
 
   // We chose to canonicalize all idempotent operations to an single
   // operation code and constant.  This makes it easier for the rest of the
-  // optimizer to match easily.  The choice of or w/zero is arbitrary.
+  // optimizer to match easily.  The choices of or w/0 and fadd w/-0.0 are
+  // arbitrary. 
   if (RMWI.getType()->isIntegerTy() &&
       RMWI.getOperation() != AtomicRMWInst::Or) {
     RMWI.setOperation(AtomicRMWInst::Or);
     RMWI.setOperand(1, ConstantInt::get(RMWI.getType(), 0));
     return &RMWI;
+  } else if (RMWI.getType()->isFloatingPointTy() &&
+             RMWI.getOperation() != AtomicRMWInst::FAdd) {
+    RMWI.setOperation(AtomicRMWInst::FAdd);
+    RMWI.setOperand(1, ConstantFP::getNegativeZero(RMWI.getType()));
+    return &RMWI;
   }
 
   // Check if the required ordering is compatible with an atomic load.
   if (Ordering != AtomicOrdering::Acquire &&
       Ordering != AtomicOrdering::Monotonic)
     return nullptr;
   
   LoadInst *Load = new LoadInst(RMWI.getType(), RMWI.getPointerOperand());
   Load->setAtomic(Ordering, RMWI.getSyncScopeID());
   Load->setAlignment(DL.getABITypeAlignment(RMWI.getType()));
   return Load;
 }

llvm/trunk/test/Transforms/InstCombine/atomicrmw.ll

 ; CHECK-LABEL: atomic_max_smin_char
 ; CHECK-NEXT: %res = load atomic i8, i8* %addr monotonic, align 1
 ; CHECK-NEXT: ret i8 %res
 define i8 @atomic_max_smin_char(i8* %addr) {
   %res = atomicrmw max i8* %addr, i8 -128 monotonic
   ret i8 %res
 }
 
+; CHECK-LABEL: atomic_fsub
+; CHECK-NEXT: %res = load atomic float, float* %addr monotonic, align 4
+; CHECK-NEXT: ret float %res
+define float @atomic_fsub_zero(float* %addr) {
+  %res = atomicrmw fsub float* %addr, float 0.0 monotonic
+  ret float %res
+}
+
+; CHECK-LABEL: atomic_fadd
+; CHECK-NEXT: %res = load atomic float, float* %addr monotonic, align 4
+; CHECK-NEXT: ret float %res
+define float @atomic_fadd_zero(float* %addr) {
+  %res = atomicrmw fadd float* %addr, float -0.0 monotonic
+  ret float %res
+}
+
+; CHECK-LABEL: atomic_fsub_canon
+; CHECK-NEXT: %res = atomicrmw fadd float* %addr, float -0.000000e+00 release
+; CHECK-NEXT: ret float %res
+define float @atomic_fsub_canon(float* %addr) {
+  %res = atomicrmw fsub float* %addr, float 0.0 release
+  ret float %res
+}
 
 ; Can't replace a volatile w/a load; this would eliminate a volatile store.
 ; CHECK-LABEL: atomic_sub_zero_volatile
 ; CHECK-NEXT: %res = atomicrmw volatile sub i64* %addr, i64 0 acquire
 ; CHECK-NEXT: ret i64 %res
 define i64 @atomic_sub_zero_volatile(i64* %addr) {
   %res = atomicrmw volatile sub i64* %addr, i64 0 acquire
   ret i64 %res