Index: lib/Target/R600/SIRegisterInfo.td
===================================================================
--- lib/Target/R600/SIRegisterInfo.td
+++ lib/Target/R600/SIRegisterInfo.td
@@ -170,11 +170,23 @@
 //===----------------------------------------------------------------------===//
 
 // Special register classes for predicates and the M0 register
-def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
+def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
+  let CopyCost = -1;
+  let isAllocatable = 0;
+}
+
+// XXX - Should this be isAllocatable = 0?
 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
-def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
+
+def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)> {
+  let isAllocatable = 0;
+}
+
+// XXX - Seems like this should be isAllocatable = 0, but that seems
+// to break tests.
 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
 
+
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
   (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)