[RFC] [CFE] Allocatable Global Register Variables for ARM

[carwil]

Summary

Provides the frontend support for using r5-r11 as globally scoped register variables.
LLVM patch: https://reviews.llvm.org/D56005

[javed.absar]

lib/Basic/Targets/ARM.h

150

The implementation of the function probably belongs to Targets/ARM.cpp. Also, this can be written more compactly as :

SmallVector<StringRef, 8> Regs = {"r4", "r5", ... "sp" };
if (std::any_of(Regs.begin(), Regs.end(), 
         [RegName](StringRef r) { return RegName.equals(r); })) {
     HasSizeMismatch = false;
     return true;
}

[carwil]

• Re-implementation using subtarget features over metadata.
• Reduction of register range to R5-R11.
• Additional checks to fix issues with spilling registers for stack alignment.
• Added clang errors for conflicting options with reserved registers.

[carwil]

Added some regression tests for invalid -ffixed-reg combinations and the declaration of (un)supported variables.

[carwil]

Added cfe-commits.

[carwil]

More tests, and better handling of argument combination errors.

[carwil]

Removed the complicated frame pointer/ffixed combination errors in favour of an always on warning (in a new group, so it can be silenced).

[carwil]

Superseded by https://reviews.llvm.org/D68862.

docs/ClangCommandLineReference.rst

 AMDGPU
 ------
 .. option:: -mxnack, -mno-xnack
 
 Enable XNACK (AMDGPU only)
 
 ARM
 ---
+.. option:: -ffixed-r5
+
+Reserve the r5 register (ARM only)
+
+.. option:: -ffixed-r6
+
+Reserve the r6 register (ARM only)
+
+.. option:: -ffixed-r7
+
+Reserve the r7 register (ARM only)
+
+.. option:: -ffixed-r8
+
+Reserve the r8 register (ARM only)
+
 .. option:: -ffixed-r9
 
 Reserve the r9 register (ARM only)
 
+.. option:: -ffixed-r10
+
+Reserve the r10 register (ARM only)
+
+.. option:: -ffixed-r11
+
+Reserve the r11 register (ARM only)
+
 .. option:: -mexecute-only, -mno-execute-only, -mpure-code
 
 Disallow generation of data access to code sections (ARM only)
 
 .. option:: -mno-movt
 
 Disallow use of movt/movw pairs (ARM only)
 

include/clang/Basic/DiagnosticDriverKinds.td

 def warn_drv_msp430_hwmult_mismatch : Warning<"the given MCU supports %0 "
   "hardware multiply, but -mhwmult is set to %1.">,
    InGroup<InvalidCommandLineArgument>;
 def warn_drv_msp430_hwmult_no_device : Warning<"no MCU device specified, but "
   "'-mhwmult' is set to 'auto', assuming no hardware multiply. Use -mmcu to "
   "specify a MSP430 device, or -mhwmult to set hardware multiply type "
   "explicitly.">, InGroup<InvalidCommandLineArgument>;
 
+// Frame pointer reservation.
+def warn_reserved_frame_pointer : Warning<
+  "'%0' has been specified but '%1' may still be used as a frame pointer">,
+  InGroup<FixedRegs>;
+
 }

include/clang/Basic/DiagnosticGroups.td

 def FunctionMultiVersioning : DiagGroup<"function-multiversion">;
 
 def NoDeref : DiagGroup<"noderef">;
 
 // A group for cross translation unit static analysis related warnings.
 def CrossTU : DiagGroup<"ctu">;
 
 def CTADMaybeUnsupported : DiagGroup<"ctad-maybe-unsupported">;
+
+// Register reservation.
+def FixedRegs : DiagGroup<"fixed-registers">;
 No newline at end of file

include/clang/Driver/Options.td

 def mstrict_align : Flag<["-"], "mstrict-align">, Alias<mno_unaligned_access>, Flags<[CC1Option,HelpHidden]>,
   HelpText<"Force all memory accesses to be aligned (same as mno-unaligned-access)">;
 def mno_thumb : Flag<["-"], "mno-thumb">, Group<m_arm_Features_Group>;
 def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Disallow generation of deprecated IT blocks for ARMv8. It is on by default for ARMv8 Thumb mode.">;
 def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Allow generation of deprecated IT blocks for ARMv8. It is off by default for ARMv8 Thumb mode">;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
-def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
-  HelpText<"Reserve the r9 register (ARM only)">;
+foreach i = {5-11} in
+  def ffixed_r#i : Flag<["-"], "ffixed-r"#i>, Group<m_arm_Features_Group>,
+    HelpText<"Reserve the r"#i#" register (ARM only)">;
 def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of movt/movw pairs (ARM only)">;
 def mcrc : Flag<["-"], "mcrc">, Group<m_Group>,
   HelpText<"Allow use of CRC instructions (ARM/Mips only)">;
 def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
   HelpText<"Disallow use of CRC instructions (ARM only)">;
 def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_Group>,
   HelpText<"Disallow converting instructions with negative immediates to their negation or inversion.">;

lib/Basic/Targets/ARM.h

public:
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   bool isCLZForZeroUndef() const override;
   BuiltinVaListKind getBuiltinVaListKind() const override;
 
   ArrayRef<const char *> getGCCRegNames() const override;
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
+  bool validateGlobalRegisterVariable(StringRef RegName,
+                                      unsigned RegSize,
+                                      bool &HasSizeMismatch) const override;
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
   std::string convertConstraint(const char *&Constraint) const override;
   bool
   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
                              std::string &SuggestedModifier) const override;
   const char *getClobbers() const override;
 

lib/Basic/Targets/ARM.cpp

const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
     // The S, D and Q registers overlap, but aren't really aliases; we
     // don't want to substitute one of these for a different-sized one.
 };
 
 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool ARMTargetInfo::validateGlobalRegisterVariable(
+    StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {
+  if (RegName.equals("r5") ||
+      RegName.equals("r6") ||
+      RegName.equals("r7") ||
+      RegName.equals("r8") ||
+      RegName.equals("r9") ||
+      RegName.equals("r10") ||
+      RegName.equals("r11") ||
+      RegName.equals("sp")) {
+    HasSizeMismatch = false;
+    return true;
+  }
+  return false;
+}
+
 bool ARMTargetInfo::validateAsmConstraint(
     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
   switch (*Name) {
   default:
     break;
   case 'l': // r0-r7
   case 'h': // r8-r15
   case 't': // VFP Floating point register single precision

lib/Driver/ToolChains/Arch/ARM.cpp

if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
         Features.push_back("+strict-align");
     } else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
       if (VersionNum < 7)
         Features.push_back("+strict-align");
     } else
       Features.push_back("+strict-align");
   }
 
-  // llvm does not support reserving registers in general. There is support
-  // for reserving r9 on ARM though (defined as a platform-specific register
-  // in ARM EABI).
-  if (Args.hasArg(options::OPT_ffixed_r9))
-    Features.push_back("+reserve-r9");
+  // Do not allow r9 reservation with -frwpi.
+  if (Args.hasArg(options::OPT_ffixed_r9) && Args.hasArg(options::OPT_frwpi)) {
+    Arg *A = Args.getLastArg(options::OPT_ffixed_r9);
+    Arg *B = Args.getLastArg(options::OPT_frwpi);
+    D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
+  }
+
+  // The compiler can still use a FP in certain circumstances,
+  // even when frame pointer elimination is enabled. Thus we should
+  // give a warning when trying to reserve a target's FP register.
+  const llvm::opt::OptSpecifier RestrictFPOpt =
+      (Triple.isOSDarwin() || (!Triple.isOSWindows() && Triple.isThumb()))
+          ? options::OPT_ffixed_r7
+          : options::OPT_ffixed_r11;
+  if (Args.hasArg(RestrictFPOpt)) {
+    const std::string OptStr = Args.getLastArg(RestrictFPOpt)->getAsString(Args);
+    const unsigned int SubStrIndex = strlen("ffixed-r");
+    D.Diag(diag::warn_reserved_frame_pointer) << OptStr << OptStr.substr(SubStrIndex);
+  }
+
+// Reservation of general purpose registers.
+#define HANDLE_FFIXED_R(n) \
+  if (Args.hasArg(options::OPT_ffixed_r##n)) \
+    Features.push_back("+reserve-r" #n)
+  HANDLE_FFIXED_R(5);
+  HANDLE_FFIXED_R(6);
+  HANDLE_FFIXED_R(7);
+  HANDLE_FFIXED_R(8);
+  HANDLE_FFIXED_R(9);
+  HANDLE_FFIXED_R(10);
+  HANDLE_FFIXED_R(11);
 
   // The kext linker doesn't know how to deal with movw/movt.
   if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
     Features.push_back("+no-movt");
 
   if (Args.hasArg(options::OPT_mno_neg_immediates))
     Features.push_back("+no-neg-immediates");
 }

test/Driver/arm-reserved-reg-options.c

+// ## FP ARM + Thumb
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R11 %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r11 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -mthumb -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R7 %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r7 -mthumb -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R7 %s
+// RUN: %clang -target thumbv6m-none-eabi -### -ffixed-r7 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// ## FP Darwin (R7)
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R7 %s
+// RUN: %clang -target armv6-apple-darwin9 -### -ffixed-r7 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R7 %s
+// RUN: %clang -target armv6-apple-ios3 -### -ffixed-r7 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r7 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R7 %s
+// RUN: %clang -target armv7s-apple-darwin10 -### -ffixed-r7 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// ## FP Windows (R11)
+// RUN: %clang -target armv7-windows -### -ffixed-r11 -c %s 2>&1 | FileCheck -check-prefix=CHECK-WARNING-R11 %s
+// RUN: %clang -target armv7-windows -### -ffixed-r11 -Wno-fixed-registers -c %s 2>&1 | FileCheck -check-prefix=CHECK-NO-WARNING %s
+
+// ## FRWPI (R9)
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-CONFLICT %s
+// RUN: %clang -target arm-arm-none-eabi -### -ffixed-r9 -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s
+// RUN: %clang -target arm-arm-none-eabi -### -frwpi -c %s 2>&1 | FileCheck -check-prefix=CHECK-RESERVED-FRWPI-VALID %s
+
+// CHECK-WARNING-R11: warning: '-ffixed-r11' has been specified but 'r11' may still be used as a frame pointer [-Wfixed-registers]
+// CHECK-WARNING-R7: warning: '-ffixed-r7' has been specified but 'r7' may still be used as a frame pointer [-Wfixed-registers]
+// CHECK-NO-WARNING-NOT: may still be used as a frame pointer [-Wfixed-registers]
+
+// CHECK-RESERVED-FRWPI-CONFLICT: option '-ffixed-r9' cannot be specified with '-frwpi'
+// CHECK-RESERVED-FRWPI-VALID-NOT: option '-ffixed-r9' cannot be specified with '-frwpi'
 No newline at end of file

test/Sema/arm-global-regs.c

+// RUN: %clang_cc1 -ffreestanding -fsyntax-only -verify -triple arm %s
+
+// Check a small subset of valid and invalid global register variable declarations.
+
+register unsigned arm_r3 __asm("r3");   //expected-error {{register 'r3' unsuitable for global register variables on this target}}
+
+register unsigned arm_r12 __asm("r12"); //expected-error {{register 'r12' unsuitable for global register variables on this target}}
+
+register unsigned arm_r5 __asm("r5");
+
+register unsigned arm_r9 __asm("r9");
+
+register unsigned arm_sp __asm("sp");
 No newline at end of file