Add basic conditional branches in mips fast-isel

[rkotler]

Summary

Implement the most basic form of conditional branches in Mips fast-isel.

[dsanders]

LGTM with a couple extra comments

lib/Target/Mips/MipsFastISel.cpp

345

This confused me for a moment. Could you make it a bit clearer that we're working on the else case at this point?

test/CodeGen/Mips/Fast-ISel/br1.ll

24

It's not necessary for this patch but this instruction is redundant and should be trivial to eliminate. Could you add a FIXME comment to this test?

[rkotler]

1. Add comment making clear the how the code for the basic branch is working. This particular part was copied from the PPC port but we will expand this soon to do more cases by porting the AARCH64 version of this routine.

2. Add a FIXME to try and eliminate some unneeded code. This frequently happens in fast-isel because it's a simple one pass compiler.

[rkotler]

1. Added comment about true and false targets of the conditional expression.
2. Added FIXME to the test case for a redundant instruction that we are generating.

lib/Target/Mips/MipsFastISel.cpp

public:
 
   bool ComputeAddress(const Value *Obj, Address &Addr);
 
 private:
   bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
                 unsigned Alignment = 0);
   bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
                  unsigned Alignment = 0);
+  bool EmitCmp(unsigned DestReg, const CmpInst *CI);
   bool SelectLoad(const Instruction *I);
+  bool SelectBranch(const Instruction *I);
   bool SelectRet(const Instruction *I);
   bool SelectStore(const Instruction *I);
   bool SelectIntExt(const Instruction *I);
   bool SelectTrunc(const Instruction *I);
   bool SelectFPExt(const Instruction *I);
   bool SelectFPTrunc(const Instruction *I);
   bool SelectFPToI(const Instruction *I, bool IsSigned);
   bool SelectCmp(const Instruction *I);
bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
   return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
 }
 
 bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
                                unsigned DestReg) {
   switch (SrcVT.SimpleTy) {
   default:
     return false;
   case MVT::i1:
     EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
     break;
   case MVT::i8:
     EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
     break;
   case MVT::i16:
     EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
     break;
   }
   return true;
 }
 
+//
+// This can cause a redundant sltiu to be generated.
+// FIXME: try and eliminate this in a future patch.
+//
+bool MipsFastISel::SelectBranch(const Instruction *I) {
+  const BranchInst *BI = cast<BranchInst>(I);
+  MachineBasicBlock *BrBB = FuncInfo.MBB;
+  //
+  // TBB is the basic block for the case where the comparison is true.
+  // FBB is the basic block for the case where the comparison is false.
+  // if (cond) goto TBB
+  // goto FBB
+  // TBB:
+  //
+  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
+  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
+  BI->getCondition();
+  // For now, just try the simplest case where it's fed by a compare.
+  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
+    unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
+    if (!EmitCmp(CondReg, CI))
+      return false;
+    BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
+        .addReg(CondReg)
+        .addMBB(TBB);
+    fastEmitBranch(FBB, DbgLoc);
+    FuncInfo.MBB->addSuccessor(TBB);
+    return true;
+  }
+  return false;
+}
+
 bool MipsFastISel::SelectLoad(const Instruction *I) {
   // Atomic loads need special handling.
   if (cast<LoadInst>(I)->isAtomic())
     return false;
 
   // Verify we have a legal type before going any further.
   MVT VT;
   if (!isLoadTypeLegal(I->getType(), VT))
bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
   // Generate the convert.
   EmitInst(Opc, TempReg).addReg(SrcReg);
 
   EmitInst(Mips::MFC1, DestReg).addReg(TempReg);
 
   updateValueMap(I, DestReg);
   return true;
 }
-
 //
-// Because of how SelectCmp is called with fast-isel, you can
+// Because of how EmitCmp is called with fast-isel, you can
 // end up with redundant "andi" instructions after the sequences emitted below.
 // We should try and solve this issue in the future.
 //
-bool MipsFastISel::SelectCmp(const Instruction *I) {
-  const CmpInst *CI = cast<CmpInst>(I);
+bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
+  const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
   bool IsUnsigned = CI->isUnsigned();
-  const Value *Left = I->getOperand(0), *Right = I->getOperand(1);
-
   unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
   if (LeftReg == 0)
     return false;
   unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
   if (RightReg == 0)
     return false;
-  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
   CmpInst::Predicate P = CI->getPredicate();
+
   switch (P) {
   default:
     return false;
   case CmpInst::ICMP_EQ: {
     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
     EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
     EmitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
     break;
case CmpInst::FCMP_OGE: {
     MachineInstrBuilder MI = EmitInst(CondMovOpc, ResultReg)
                                  .addReg(RegWithOne)
                                  .addReg(Mips::FCC0)
                                  .addReg(RegWithZero, RegState::Implicit);
     MI->tieOperands(0, 3);
     break;
   }
   }
+  return true;
+}
+
+bool MipsFastISel::SelectCmp(const Instruction *I) {
+  const CmpInst *CI = cast<CmpInst>(I);
+  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+  if (!EmitCmp(ResultReg, CI))
+    return false;
   updateValueMap(I, ResultReg);
   return true;
 }
 
 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
   switch (I->getOpcode()) {
   default:
     break;
   case Instruction::Load:
     return SelectLoad(I);
   case Instruction::Store:
     return SelectStore(I);
+  case Instruction::Br:
+    return SelectBranch(I);
   case Instruction::Ret:
     return SelectRet(I);
   case Instruction::Trunc:
     return SelectTrunc(I);
   case Instruction::ZExt:
   case Instruction::SExt:
     return SelectIntExt(I);
   case Instruction::FPTrunc:

test/CodeGen/Mips/Fast-ISel/br1.ll

+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
+
+@b = global i32 1, align 4
+@i = global i32 0, align 4
+@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @br() #0 {
+entry:
+  %0 = load i32* @b, align 4
+  %tobool = icmp eq i32 %0, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  store i32 6754, i32* @i, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  ret void
+; FIXME: This instruction is redundant.
+; CHECK:  xor  $[[REG1:[0-9]+]], ${{[0-9]+}}, $zero
+; CHECK:  sltiu  $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK:  bgtz  $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]]
+; CHECK:  nop
+; CHECK:  addiu  ${{[0-9]+}}, $zero, 6754
+; CHECK:  sw  ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK: $BB[[BL]]:
+
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }