Index: lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- lib/Target/Mips/MipsFastISel.cpp
+++ lib/Target/Mips/MipsFastISel.cpp
@@ -83,6 +83,7 @@
   bool SelectFPExt(const Instruction *I);
   bool SelectFPTrunc(const Instruction *I);
   bool SelectFPToI(const Instruction *I, bool IsSigned);
+  bool SelectCmp(const Instruction *I);
 
   bool isTypeLegal(Type *Ty, MVT &VT);
   bool isLoadTypeLegal(Type *Ty, MVT &VT);
@@ -527,6 +528,107 @@
   return true;
 }
 
+bool MipsFastISel::SelectCmp(const Instruction *I) {
+  const CmpInst *CI = cast<CmpInst>(I);
+  const Value *Left = I->getOperand(0), *Right = I->getOperand(1);
+  unsigned LeftReg = getRegForValue(Left);
+  if (LeftReg == 0)
+    return false;
+  MVT LMVT = TLI.getValueType(Left->getType(), true).getSimpleVT();
+  if ((LMVT == MVT::i8) || (LMVT == MVT::i16)) {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    if (!EmitIntExt(LMVT, LeftReg, MVT::i32, TempReg, CI->isUnsigned()))
+      return false;
+    LeftReg = TempReg;
+  }
+  unsigned RightReg = getRegForValue(Right);
+  if (RightReg == 0)
+    return false;
+  MVT RMVT = TLI.getValueType(Right->getType(), true).getSimpleVT();
+  if ((RMVT == MVT::i8) || (RMVT == MVT::i16)) {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    if (!EmitIntExt(LMVT, RightReg, MVT::i32, TempReg, CI->isUnsigned()))
+      return false;
+    RightReg = TempReg;
+  }
+  unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
+  switch (CI->getPredicate()) {
+  default:
+    return false;
+  case CmpInst::ICMP_EQ: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+    EmitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
+    break;
+  }
+  case CmpInst::ICMP_NE: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+    EmitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
+    break;
+  }
+  case CmpInst::ICMP_UGT: {
+    EmitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
+    break;
+  }
+  case CmpInst::ICMP_ULT: {
+    EmitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
+    break;
+  }
+  case CmpInst::ICMP_UGE: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
+    EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+    break;
+  }
+  case CmpInst::ICMP_ULE: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
+    EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+    break;
+  }
+  case CmpInst::ICMP_SGT: {
+    EmitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
+    break;
+  }
+  case CmpInst::ICMP_SLT: {
+    EmitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
+    break;
+  }
+  case CmpInst::ICMP_SGE: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
+    EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+    break;
+  }
+  case CmpInst::ICMP_SLE: {
+    unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
+    EmitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
+    EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+    break;
+  }
+
+  case CmpInst::FCMP_OEQ:
+  case CmpInst::FCMP_ONE:
+  case CmpInst::FCMP_OGT:
+  case CmpInst::FCMP_OLT:
+  case CmpInst::FCMP_OLE:
+  case CmpInst::FCMP_UEQ:
+  case CmpInst::FCMP_UNE:
+  case CmpInst::FCMP_UGT:
+  case CmpInst::FCMP_ULT:
+  case CmpInst::FCMP_UGE:
+  case CmpInst::FCMP_ULE:
+  case CmpInst::FCMP_ORD:
+  case CmpInst::FCMP_UNO:
+  case CmpInst::FCMP_TRUE:
+  case CmpInst::FCMP_FALSE:
+    return false;
+  }
+  updateValueMap(I, ResultReg);
+  return true;
+}
+
 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
   if (!TargetSupported)
     return false;
@@ -552,6 +654,9 @@
     return SelectFPToI(I, /*isSigned*/ true);
   case Instruction::FPToUI:
     return SelectFPToI(I, /*isSigned*/ false);
+  case Instruction::ICmp:
+  case Instruction::FCmp:
+    return SelectCmp(I);
   }
   return false;
 }
Index: test/CodeGen/Mips/Fast-ISel/icmpa.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/Fast-ISel/icmpa.ll
@@ -0,0 +1,162 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
+
+@c = global i32 4, align 4
+@d = global i32 9, align 4
+@uc = global i32 4, align 4
+@ud = global i32 9, align 4
+@b1 = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @eq()  {
+entry:
+; CHECK-LABEL:  .ent  eq
+
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp eq i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  xor  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  sltiu  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @ne()  {
+entry:
+; CHECK-LABEL:  .ent  ne
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp ne i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  xor  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  sltu  ${{[0-9]+}}, $zero, ${{[0-9]+}}
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @ugt()  {
+entry:
+; CHECK-LABEL:  .ent  ugt
+  %0 = load i32* @uc, align 4
+  %1 = load i32* @ud, align 4
+  %cmp = icmp ugt i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @ult()  {
+entry:
+; CHECK-LABEL:  .ent  ult
+  %0 = load i32* @uc, align 4
+  %1 = load i32* @ud, align 4
+  %cmp = icmp ult i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @uge()  {
+entry:
+; CHECK-LABEL:  .ent  uge
+  %0 = load i32* @uc, align 4
+  %1 = load i32* @ud, align 4
+  %cmp = icmp uge i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  xori  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @ule()  {
+entry:
+; CHECK-LABEL:  .ent  ule
+  %0 = load i32* @uc, align 4
+  %1 = load i32* @ud, align 4
+  %cmp = icmp ule i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  sltu  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  xori  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @sgt()  {
+entry:
+; CHECK-LABEL:  .ent sgt
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp sgt i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  slt  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @slt()  {
+entry:
+; CHECK-LABEL:  .ent slt
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp slt i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:  slt  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @sge()  {
+entry:
+; CHECK-LABEL:  .ent sge
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp sge i32 %0, %1
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @b1, align 4
+; CHECK:  slt  ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:  xori  ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:  andi  ${{[0-9]+}}, ${{[0-9]+}}, 1
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @sle()  {
+entry:
+; CHECK-LABEL:  .ent sle
+  %0 = load i32* @c, align 4
+  %1 = load i32* @d, align 4
+  %cmp = icmp sle i32 %0, %1
+  %conv = zext i1 %cmp to i32
+; CHECK:        slt     ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK:        xori    ${{[0-9]+}}, ${{[0-9]+}}, 1
+; CHECK:        andi    ${{[0-9]+}}, ${{[0-9]+}}, 1
+  store i32 %conv, i32* @b1, align 4
+  ret void
+}
+
+