Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -5445,59 +5445,35 @@
           (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
 
 // Vector shift sxtl aliases
-def : InstAlias<"sxtl.8h $dst, $src1",
+def : InstAlias<"sxtl{ $dst.8h, $src1.8b|.8h $dst, $src1}",
                 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.8h, $src1.8b",
-                (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl.4s $dst, $src1",
-                (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.4s, $src1.4h",
+def : InstAlias<"sxtl{ $dst.4s, $src1.4h|.4s $dst, $src1}",
                 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl.2d $dst, $src1",
-                (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.2d, $src1.2s",
+def : InstAlias<"sxtl{ $dst.2d, $src1.2s|.2d $dst, $src1}",
                 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
 
 // Vector shift sxtl2 aliases
-def : InstAlias<"sxtl2.8h $dst, $src1",
+def : InstAlias<"sxtl2{ $dst.8h, $src1.16b|.8h $dst, $src1}",
                 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
-                (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2.4s $dst, $src1",
-                (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
+def : InstAlias<"sxtl2{ $dst.4s, $src1.8h|.4s $dst, $src1}",
                 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2.2d $dst, $src1",
-                (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
+def : InstAlias<"sxtl2{ $dst.2d, $src1.4s|.2d $dst, $src1}",
                 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 
 // Vector shift uxtl aliases
-def : InstAlias<"uxtl.8h $dst, $src1",
+def : InstAlias<"uxtl{ $dst.8h, $src1.8b|.8h $dst, $src1}",
                 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.8h, $src1.8b",
-                (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl.4s $dst, $src1",
-                (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.4s, $src1.4h",
+def : InstAlias<"uxtl{ $dst.4s, $src1.4h|.4s $dst, $src1}",
                 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl.2d $dst, $src1",
-                (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.2d, $src1.2s",
+def : InstAlias<"uxtl{ $dst.2d, $src1.2s|.2d $dst, $src1}",
                 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
 
 // Vector shift uxtl2 aliases
-def : InstAlias<"uxtl2.8h $dst, $src1",
+def : InstAlias<"uxtl2{ $dst.8h, $src1.16b|.8h $dst, $src1}",
                 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
-                (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2.4s $dst, $src1",
-                (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
+def : InstAlias<"uxtl2{ $dst.4s, $src1.8h|.4s $dst, $src1}",
                 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2.2d $dst, $src1",
-                (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
+def : InstAlias<"uxtl2{ $dst.2d, $src1.4s|.2d $dst, $src1}",
                 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 
 // If an integer is about to be converted to a floating point value,
Index: test/CodeGen/AArch64/arm64-extend-int-to-fp.ll
===================================================================
--- test/CodeGen/AArch64/arm64-extend-int-to-fp.ll
+++ test/CodeGen/AArch64/arm64-extend-int-to-fp.ll
@@ -2,7 +2,7 @@
 
 define <4 x float> @foo(<4 x i16> %a) nounwind {
 ; CHECK-LABEL: foo:
-; CHECK: ushll.4s	v0, v0, #0
+; CHECK: uxtl.4s	v0, v0
 ; CHECK-NEXT: ucvtf.4s	v0, v0
 ; CHECK-NEXT: ret
   %vcvt.i = uitofp <4 x i16> %a to <4 x float>
@@ -11,7 +11,7 @@
 
 define <4 x float> @bar(<4 x i16> %a) nounwind {
 ; CHECK-LABEL: bar:
-; CHECK: sshll.4s	v0, v0, #0
+; CHECK: sxtl.4s	v0, v0
 ; CHECK-NEXT: scvtf.4s	v0, v0
 ; CHECK-NEXT: ret
   %vcvt.i = sitofp <4 x i16> %a to <4 x float>
Index: test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll
===================================================================
--- test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll
+++ test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll
@@ -12,7 +12,7 @@
 
 define <2 x double> @test_sitofp(<2 x i32> %in) {
 ; CHECK-LABEL: test_sitofp:
-; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
+; CHECK: sxtl.2d [[EXT:v[0-9]+]], v0
 ; CHECK: scvtf.2d v0, [[EXT]]
 
   %res = sitofp <2 x i32> %in to <2 x double>
Index: test/CodeGen/AArch64/arm64-ld1.ll
===================================================================
--- test/CodeGen/AArch64/arm64-ld1.ll
+++ test/CodeGen/AArch64/arm64-ld1.ll
@@ -915,8 +915,8 @@
 ; CHECK: ld1r_2s_from_dup
 ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
 ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
-; CHECK-NEXT: ushll.8h [[ARG1]], [[ARG1]], #0
-; CHECK-NEXT: ushll.8h [[ARG2]], [[ARG2]], #0
+; CHECK-NEXT: uxtl.8h [[ARG1]], [[ARG1]]
+; CHECK-NEXT: uxtl.8h [[ARG2]], [[ARG2]]
 ; CHECK-NEXT: sub.4h v[[RESREGNUM:[0-9]+]], [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: str d[[RESREGNUM]], [x2]
 ; CHECK-NEXT: ret
Index: test/CodeGen/AArch64/arm64-scvt.ll
===================================================================
--- test/CodeGen/AArch64/arm64-scvt.ll
+++ test/CodeGen/AArch64/arm64-scvt.ll
@@ -406,8 +406,8 @@
 define float @sfct1(i8* nocapture %sp0) {
 ; CHECK-LABEL: sfct1:
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct1:
@@ -425,7 +425,7 @@
 define float @sfct2(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct2:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
@@ -467,8 +467,8 @@
 define float @sfct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct5:
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct5:
@@ -486,7 +486,7 @@
 define float @sfct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct6:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
@@ -541,8 +541,8 @@
 define double @sfct10(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct10:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct10:
@@ -560,7 +560,7 @@
 define double @sfct11(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct11:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
@@ -601,8 +601,8 @@
 define double @sfct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct14:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct14:
@@ -620,7 +620,7 @@
 define double @sfct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct15:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
@@ -649,8 +649,8 @@
 entry:
 ; CHECK-LABEL: sfct17:
 ; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct17:
@@ -669,7 +669,7 @@
 define float @sfct18(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct18:
 ; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
   %bitcast = ptrtoint i16* %sp0 to i64
@@ -730,8 +730,8 @@
 define double @sfct22(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct22:
 ; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct22:
@@ -750,7 +750,7 @@
 define double @sfct23(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct23:
 ; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   %bitcast = ptrtoint i32* %sp0 to i64
Index: test/CodeGen/AArch64/arm64-subvector-extend.ll
===================================================================
--- test/CodeGen/AArch64/arm64-subvector-extend.ll
+++ test/CodeGen/AArch64/arm64-subvector-extend.ll
@@ -8,7 +8,7 @@
 ;-----
 define <8 x i16> @func1(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: func1:
-; CHECK-NEXT: ushll.8h  v0, v0, #0
+; CHECK-NEXT: uxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i8> %v0 to <8 x i16>
   ret <8 x i16> %r
@@ -16,7 +16,7 @@
 
 define <8 x i16> @func2(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: func2:
-; CHECK-NEXT: sshll.8h  v0, v0, #0
+; CHECK-NEXT: sxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i8> %v0 to <8 x i16>
   ret <8 x i16> %r
@@ -24,8 +24,8 @@
 
 define <16 x i16> @func3(<16 x i8> %v0) nounwind {
 ; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll2.8h  v1, v0, #0
-; CHECK-NEXT: ushll.8h  v0, v0, #0
+; CHECK-NEXT: uxtl2.8h  v1, v0
+; CHECK-NEXT: uxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <16 x i8> %v0 to <16 x i16>
   ret <16 x i16> %r
@@ -33,8 +33,8 @@
 
 define <16 x i16> @func4(<16 x i8> %v0) nounwind {
 ; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll2.8h  v1, v0, #0
-; CHECK-NEXT: sshll.8h  v0, v0, #0
+; CHECK-NEXT: sxtl2.8h  v1, v0
+; CHECK-NEXT: sxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <16 x i8> %v0 to <16 x i16>
   ret <16 x i16> %r
@@ -46,7 +46,7 @@
 
 define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc1:
-; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: uxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i16> %v0 to <4 x i32>
   ret <4 x i32> %r
@@ -54,7 +54,7 @@
 
 define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc2:
-; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: sxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i16> %v0 to <4 x i32>
   ret <4 x i32> %r
@@ -62,8 +62,8 @@
 
 define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc3:
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: uxtl2.4s v1, v0
+; CHECK-NEXT: uxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i16> %v0 to <8 x i32>
   ret <8 x i32> %r
@@ -71,8 +71,8 @@
 
 define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc4:
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: sxtl2.4s v1, v0
+; CHECK-NEXT: sxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i16> %v0 to <8 x i32>
   ret <8 x i32> %r
@@ -80,9 +80,9 @@
 
 define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: bfunc1:
-; CHECK-NEXT: ushll.8h  v0, v0, #0
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s  v0, v0, #0
+; CHECK-NEXT: uxtl.8h  v0, v0
+; CHECK-NEXT: uxtl2.4s v1, v0
+; CHECK-NEXT: uxtl.4s  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i8> %v0 to <8 x i32>
   ret <8 x i32> %r
@@ -90,9 +90,9 @@
 
 define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: bfunc2:
-; CHECK-NEXT: sshll.8h  v0, v0, #0
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s  v0, v0, #0
+; CHECK-NEXT: sxtl.8h  v0, v0
+; CHECK-NEXT: sxtl2.4s v1, v0
+; CHECK-NEXT: sxtl.4s  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i8> %v0 to <8 x i32>
   ret <8 x i32> %r
@@ -104,8 +104,8 @@
 
 define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
 ; CHECK-LABEL: zfunc1:
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
+; CHECK-NEXT: uxtl2.2d v1, v0
+; CHECK-NEXT: uxtl.2d v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i32> %v0 to <4 x i64>
   ret <4 x i64> %r
@@ -113,8 +113,8 @@
 
 define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
 ; CHECK-LABEL: zfunc2:
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d v0, v0, #0
+; CHECK-NEXT: sxtl2.2d v1, v0
+; CHECK-NEXT: sxtl.2d v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i32> %v0 to <4 x i64>
   ret <4 x i64> %r
@@ -122,9 +122,9 @@
 
 define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll.4s  v0, v0, #0
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d  v0, v0, #0
+; CHECK-NEXT: uxtl.4s  v0, v0
+; CHECK-NEXT: uxtl2.2d v1, v0
+; CHECK-NEXT: uxtl.2d  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i16> %v0 to <4 x i64>
   ret <4 x i64> %r
@@ -132,9 +132,9 @@
 
 define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll.4s  v0, v0, #0
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d  v0, v0, #0
+; CHECK-NEXT: sxtl.4s  v0, v0
+; CHECK-NEXT: sxtl2.2d v1, v0
+; CHECK-NEXT: sxtl.2d  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i16> %v0 to <4 x i64>
   ret <4 x i64> %r
Index: test/CodeGen/AArch64/arm64-vbitwise.ll
===================================================================
--- test/CodeGen/AArch64/arm64-vbitwise.ll
+++ test/CodeGen/AArch64/arm64-vbitwise.ll
@@ -21,7 +21,7 @@
 
 define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sxtl8h:
-;CHECK: sshll.8h
+;CHECK: sxtl.8h
 	%tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
@@ -29,7 +29,7 @@
 
 define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uxtl8h:
-;CHECK: ushll.8h
+;CHECK: uxtl.8h
 	%tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
@@ -37,7 +37,7 @@
 
 define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sxtl4s:
-;CHECK: sshll.4s
+;CHECK: sxtl.4s
 	%tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
@@ -45,7 +45,7 @@
 
 define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: uxtl4s:
-;CHECK: ushll.4s
+;CHECK: uxtl.4s
 	%tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
@@ -53,7 +53,7 @@
 
 define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sxtl2d:
-;CHECK: sshll.2d
+;CHECK: sxtl.2d
 	%tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
@@ -61,7 +61,7 @@
 
 define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: uxtl2d:
-;CHECK: ushll.2d
+;CHECK: uxtl.2d
 	%tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
Index: test/CodeGen/AArch64/arm64-vector-ext.ll
===================================================================
--- test/CodeGen/AArch64/arm64-vector-ext.ll
+++ test/CodeGen/AArch64/arm64-vector-ext.ll
@@ -3,7 +3,7 @@
 ;CHECK: @func30
 ;CHECK: movi.4h v1, #1
 ;CHECK: and.8b v0, v0, v1
-;CHECK: ushll.4s  v0, v0, #0
+;CHECK: uxtl.4s  v0, v0
 ;CHECK: str  q0, [x0]
 ;CHECK: ret
 
Index: test/CodeGen/AArch64/complex-int-to-fp.ll
===================================================================
--- test/CodeGen/AArch64/complex-int-to-fp.ll
+++ test/CodeGen/AArch64/complex-int-to-fp.ll
@@ -12,7 +12,7 @@
 
 define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v2i32_to_v2f64:
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], v0
 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
 ; CHECK-NEXT: ret
   %conv = sitofp <2 x i32> %v to <2 x double>
@@ -21,7 +21,7 @@
 
 define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], v0
 ; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
 ; CHECK-NEXT: ret
   %conv = uitofp <2 x i32> %v to <2 x double>
@@ -32,7 +32,7 @@
 ; CHECK-LABEL: test_signed_v2i16_to_v2f64:
 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: scvtf.2d v0, [[VAL64]]
 
   %conv = sitofp <2 x i16> %v to <2 x double>
@@ -42,7 +42,7 @@
 ; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: ucvtf.2d v0, [[VAL64]]
 
   %conv = uitofp <2 x i16> %v to <2 x double>
@@ -53,7 +53,7 @@
 ; CHECK-LABEL: test_signed_v2i8_to_v2f64:
 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: scvtf.2d v0, [[VAL64]]
 
   %conv = sitofp <2 x i8> %v to <2 x double>
@@ -63,7 +63,7 @@
 ; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: ucvtf.2d v0, [[VAL64]]
 
   %conv = uitofp <2 x i8> %v to <2 x double>
@@ -127,7 +127,7 @@
 
 define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v4i16_to_v4f32:
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: sxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: scvtf.4s v0, [[VAL32]]
 
   %conv = sitofp <4 x i16> %v to <4 x float>
@@ -136,7 +136,7 @@
 
 define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: uxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: ucvtf.4s v0, [[VAL32]]
 
   %conv = uitofp <4 x i16> %v to <4 x float>
@@ -147,7 +147,7 @@
 ; CHECK-LABEL: test_signed_v4i8_to_v4f32:
 ; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
+; CHECK: sxtl.4s [[VAL32:v[0-9]+]], [[VAL16]]
 ; CHECK: scvtf.4s v0, [[VAL32]]
 
   %conv = sitofp <4 x i8> %v to <4 x float>
@@ -156,7 +156,7 @@
 define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
 ; CHECK: bic.4h v0, #255, lsl #8
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: uxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: ucvtf.4s v0, [[VAL32]]
 
   %conv = uitofp <4 x i8> %v to <4 x float>
Index: test/CodeGen/AArch64/fast-isel-cmp-vec.ll
===================================================================
--- test/CodeGen/AArch64/fast-isel-cmp-vec.ll
+++ test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -44,7 +44,7 @@
 ; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
-; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
+; CHECK-NEXT:  uxtl.4s v0, [[ZEXT]]
 ; CHECK-NEXT:  ret
   %c = icmp eq <4 x i32> %a, zeroinitializer
   br label %bb2
@@ -60,7 +60,7 @@
 ; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
-; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
+; CHECK-NEXT:  uxtl.4s v0, [[ZEXT]]
 ; CHECK-NEXT:  ret
   %1 = icmp eq <4 x i32> %a, %a
   br label %bb2
Index: test/CodeGen/AArch64/fdiv_combine.ll
===================================================================
--- test/CodeGen/AArch64/fdiv_combine.ll
+++ test/CodeGen/AArch64/fdiv_combine.ll
@@ -72,7 +72,7 @@
 
 ; Test unsigned i16 to float
 ; CHECK-LABEL: @test7
-; CHECK: ushll.4s  v0, v0, #0
+; CHECK: uxtl.4s  v0, v0
 ; CHECK: ucvtf.4s  v0, v0, #1
 ; CHECK: ret
 define <4 x float> @test7(<4 x i16> %in) {
@@ -83,7 +83,7 @@
 
 ; Test signed i16 to float
 ; CHECK-LABEL: @test8
-; CHECK: sshll.4s v0, v0, #0
+; CHECK: sxtl.4s v0, v0
 ; CHECK: scvtf.4s v0, v0, #2
 ; CHECK: ret
 define <4 x float> @test8(<4 x i16> %in) {
Index: test/CodeGen/AArch64/fp16-v4-instructions.ll
===================================================================
--- test/CodeGen/AArch64/fp16-v4-instructions.ll
+++ test/CodeGen/AArch64/fp16-v4-instructions.ll
@@ -156,7 +156,7 @@
 ; CHECK-COMMON-LABEL: sitofp_i8:
 ; CHECK-COMMON-NEXT:  shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
 ; CHECK-COMMON-NEXT:  sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
-; CHECK-COMMON-NEXT:  sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
+; CHECK-COMMON-NEXT:  sxtl [[OP3:v[0-9]+\.4s]], [[OP2]]
 ; CHECK-COMMON-NEXT:  scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP4]]
 ; CHECK-COMMON-NEXT:  ret
@@ -167,7 +167,7 @@
 
 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
 ; CHECK-COMMON-LABEL: sitofp_i16:
-; CHECK-COMMON-NEXT:  sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  sxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
@@ -201,7 +201,7 @@
 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
 ; CHECK-COMMON-LABEL: uitofp_i8:
 ; CHECK-COMMON-NEXT:  bic v0.4h, #255, lsl #8
-; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  uxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
@@ -212,7 +212,7 @@
 
 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
 ; CHECK-COMMON-LABEL: uitofp_i16:
-; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  uxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
Index: test/CodeGen/AArch64/fp16-v8-instructions.ll
===================================================================
--- test/CodeGen/AArch64/fp16-v8-instructions.ll
+++ test/CodeGen/AArch64/fp16-v8-instructions.ll
@@ -280,9 +280,9 @@
 
 define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-LABEL: sitofp_i8:
-; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-NEXT: sxtl v[[REG1:[0-9]+]].8h, v0.8b
+; CHECK-NEXT: sxtl2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h
+; CHECK-NEXT: sxtl  [[HI:v[0-9]+\.4s]], v[[REG1]].4h
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
@@ -295,8 +295,8 @@
 
 define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: sitofp_i16:
-; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: sxtl2 [[LO:v[0-9]+\.4s]], v0.8h
+; CHECK-NEXT: sxtl  [[HI:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
@@ -332,9 +332,9 @@
 
 define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-LABEL: uitofp_i8:
-; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-NEXT: uxtl v[[REG1:[0-9]+]].8h, v0.8b
+; CHECK-NEXT: uxtl2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h
+; CHECK-NEXT: uxtl  [[HI:v[0-9]+\.4s]], v[[REG1]].4h
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
@@ -347,8 +347,8 @@
 
 define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: uitofp_i16:
-; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: uxtl2 [[LO:v[0-9]+\.4s]], v0.8h
+; CHECK-NEXT: uxtl  [[HI:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
Index: test/CodeGen/AArch64/neon-shift-left-long.ll
===================================================================
--- test/CodeGen/AArch64/neon-shift-left-long.ll
+++ test/CodeGen/AArch64/neon-shift-left-long.ll
@@ -104,49 +104,49 @@
 
 define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) {
 ; CHECK: test_sshll_shl0_v8i8:
-; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK: sxtl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %tmp = sext <8 x i8> %a to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) {
 ; CHECK: test_sshll_shl0_v4i16:
-; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK: sxtl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
   %tmp = sext <4 x i16> %a to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) {
 ; CHECK: test_sshll_shl0_v2i32:
-; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK: sxtl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
   %tmp = sext <2 x i32> %a to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) {
 ; CHECK: test_ushll_shl0_v8i8:
-; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK: uxtl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %tmp = zext <8 x i8> %a to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) {
 ; CHECK: test_ushll_shl0_v4i16:
-; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK: uxtl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
   %tmp = zext <4 x i16> %a to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) {
 ; CHECK: test_ushll_shl0_v2i32:
-; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK: uxtl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
   %tmp = zext <2 x i32> %a to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) {
 ; CHECK: test_sshll2_shl0_v16i8:
-; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK: sxtl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
   %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %tmp = sext <8 x i8> %1 to <8 x i16>
   ret <8 x i16> %tmp
@@ -154,7 +154,7 @@
 
 define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) {
 ; CHECK: test_sshll2_shl0_v8i16:
-; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK: sxtl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
   %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp = sext <4 x i16> %1 to <4 x i32>
   ret <4 x i32> %tmp
@@ -162,7 +162,7 @@
 
 define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) {
 ; CHECK: test_sshll2_shl0_v4i32:
-; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK: sxtl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
   %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp = sext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %tmp
@@ -170,7 +170,7 @@
 
 define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) {
 ; CHECK: test_ushll2_shl0_v16i8:
-; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK: uxtl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
   %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %tmp = zext <8 x i8> %1 to <8 x i16>
   ret <8 x i16> %tmp
@@ -178,7 +178,7 @@
 
 define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) {
 ; CHECK: test_ushll2_shl0_v8i16:
-; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK: uxtl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
   %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp = zext <4 x i16> %1 to <4 x i32>
   ret <4 x i32> %tmp
@@ -186,7 +186,7 @@
 
 define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {
 ; CHECK: test_ushll2_shl0_v4i32:
-; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK: uxtl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
   %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp = zext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %tmp
@@ -195,7 +195,7 @@
 define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
 ; CHECK: test_ushll_cmp:
 ; CHECK: cmeq	{{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: ushll	{{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK-NEXT: uxtl	{{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %cmp.i = icmp eq <8 x i8> %a, %b
   %vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
   %vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>
Index: test/CodeGen/AArch64/sitofp-fixed-legal.ll
===================================================================
--- test/CodeGen/AArch64/sitofp-fixed-legal.ll
+++ test/CodeGen/AArch64/sitofp-fixed-legal.ll
@@ -4,14 +4,14 @@
 ; CHECK-LABEL: test_sitofp_fixed:
 
   ; First, extend each i32 to i64
-; CHECK-DAG: sshll2.2d [[BLOCK0_HI:v[0-9]+]], v0, #0
-; CHECK-DAG: sshll2.2d [[BLOCK1_HI:v[0-9]+]], v1, #0
-; CHECK-DAG: sshll2.2d [[BLOCK2_HI:v[0-9]+]], v2, #0
-; CHECK-DAG: sshll2.2d [[BLOCK3_HI:v[0-9]+]], v3, #0
-; CHECK-DAG: sshll.2d [[BLOCK0_LO:v[0-9]+]], v0, #0
-; CHECK-DAG: sshll.2d [[BLOCK1_LO:v[0-9]+]], v1, #0
-; CHECK-DAG: sshll.2d [[BLOCK2_LO:v[0-9]+]], v2, #0
-; CHECK-DAG: sshll.2d [[BLOCK3_LO:v[0-9]+]], v3, #0
+; CHECK-DAG: sxtl2.2d [[BLOCK0_HI:v[0-9]+]], v0
+; CHECK-DAG: sxtl2.2d [[BLOCK1_HI:v[0-9]+]], v1
+; CHECK-DAG: sxtl2.2d [[BLOCK2_HI:v[0-9]+]], v2
+; CHECK-DAG: sxtl2.2d [[BLOCK3_HI:v[0-9]+]], v3
+; CHECK-DAG: sxtl.2d [[BLOCK0_LO:v[0-9]+]], v0
+; CHECK-DAG: sxtl.2d [[BLOCK1_LO:v[0-9]+]], v1
+; CHECK-DAG: sxtl.2d [[BLOCK2_LO:v[0-9]+]], v2
+; CHECK-DAG: sxtl.2d [[BLOCK3_LO:v[0-9]+]], v3
 
   ; Next, convert each to double.
 ; CHECK-DAG: scvtf.2d v0, [[BLOCK0_LO]]
Index: test/MC/AArch64/arm64-aliases.s
===================================================================
--- test/MC/AArch64/arm64-aliases.s
+++ test/MC/AArch64/arm64-aliases.s
@@ -758,64 +758,64 @@
 ; 5.8.14 Vector Shift (immediate)
 ;-----------------------------------------------------------------------------
   sxtl v1.8h, v2.8b
-; CHECK: sshll.8h v1, v2, #0
+; CHECK: sxtl.8h v1, v2
   sxtl.8h v1, v2
-; CHECK: sshll.8h v1, v2, #0
+; CHECK: sxtl.8h v1, v2
 
   sxtl v1.4s, v2.4h
-; CHECK: sshll.4s v1, v2, #0
+; CHECK: sxtl.4s v1, v2
   sxtl.4s v1, v2
-; CHECK: sshll.4s v1, v2, #0
+; CHECK: sxtl.4s v1, v2
 
   sxtl v1.2d, v2.2s
-; CHECK: sshll.2d v1, v2, #0
+; CHECK: sxtl.2d v1, v2
   sxtl.2d v1, v2
-; CHECK: sshll.2d v1, v2, #0
+; CHECK: sxtl.2d v1, v2
 
   sxtl2 v1.8h, v2.16b
-; CHECK: sshll2.8h v1, v2, #0
+; CHECK: sxtl2.8h v1, v2
   sxtl2.8h v1, v2
-; CHECK: sshll2.8h v1, v2, #0
+; CHECK: sxtl2.8h v1, v2
 
   sxtl2 v1.4s, v2.8h
-; CHECK: sshll2.4s v1, v2, #0
+; CHECK: sxtl2.4s v1, v2
   sxtl2.4s v1, v2
-; CHECK: sshll2.4s v1, v2, #0
+; CHECK: sxtl2.4s v1, v2
 
   sxtl2 v1.2d, v2.4s
-; CHECK: sshll2.2d v1, v2, #0
+; CHECK: sxtl2.2d v1, v2
   sxtl2.2d v1, v2
-; CHECK: sshll2.2d v1, v2, #0
+; CHECK: sxtl2.2d v1, v2
 
   uxtl v1.8h, v2.8b
-; CHECK: ushll.8h v1, v2, #0
+; CHECK: uxtl.8h v1, v2
   uxtl.8h v1, v2
-; CHECK: ushll.8h v1, v2, #0
+; CHECK: uxtl.8h v1, v2
 
   uxtl v1.4s, v2.4h
-; CHECK: ushll.4s v1, v2, #0
+; CHECK: uxtl.4s v1, v2
   uxtl.4s v1, v2
-; CHECK: ushll.4s v1, v2, #0
+; CHECK: uxtl.4s v1, v2
 
   uxtl v1.2d, v2.2s
-; CHECK: ushll.2d v1, v2, #0
+; CHECK: uxtl.2d v1, v2
   uxtl.2d v1, v2
-; CHECK: ushll.2d v1, v2, #0
+; CHECK: uxtl.2d v1, v2
 
   uxtl2 v1.8h, v2.16b
-; CHECK: ushll2.8h v1, v2, #0
+; CHECK: uxtl2.8h v1, v2
   uxtl2.8h v1, v2
-; CHECK: ushll2.8h v1, v2, #0
+; CHECK: uxtl2.8h v1, v2
 
   uxtl2 v1.4s, v2.8h
-; CHECK: ushll2.4s v1, v2, #0
+; CHECK: uxtl2.4s v1, v2
   uxtl2.4s v1, v2
-; CHECK: ushll2.4s v1, v2, #0
+; CHECK: uxtl2.4s v1, v2
 
   uxtl2 v1.2d, v2.4s
-; CHECK: ushll2.2d v1, v2, #0
+; CHECK: uxtl2.2d v1, v2
   uxtl2.2d v1, v2
-; CHECK: ushll2.2d v1, v2, #0
+; CHECK: uxtl2.2d v1, v2
 
 
 ;-----------------------------------------------------------------------------
Index: test/MC/AArch64/neon-sxtl.s
===================================================================
--- test/MC/AArch64/neon-sxtl.s
+++ test/MC/AArch64/neon-sxtl.s
@@ -9,9 +9,9 @@
         sxtl v0.4s, v1.4h
         sxtl v0.2d, v1.2s
 
-// CHECK: sshll v0.8h, v1.8b, #0        // encoding: [0x20,0xa4,0x08,0x0f]
-// CHECK: sshll v0.4s, v1.4h, #0        // encoding: [0x20,0xa4,0x10,0x0f]
-// CHECK: sshll v0.2d, v1.2s, #0        // encoding: [0x20,0xa4,0x20,0x0f]
+// CHECK: sxtl v0.8h, v1.8b        // encoding: [0x20,0xa4,0x08,0x0f]
+// CHECK: sxtl v0.4s, v1.4h        // encoding: [0x20,0xa4,0x10,0x0f]
+// CHECK: sxtl v0.2d, v1.2s        // encoding: [0x20,0xa4,0x20,0x0f]
 
 //------------------------------------------------------------------------------
 // Signed integer lengthen (vector, second part)
@@ -21,6 +21,6 @@
         sxtl2 v0.4s, v1.8h
         sxtl2 v0.2d, v1.4s
 
-// CHECK: sshll2 v0.8h, v1.16b, #0        // encoding: [0x20,0xa4,0x08,0x4f]
-// CHECK: sshll2 v0.4s, v1.8h, #0        // encoding: [0x20,0xa4,0x10,0x4f]
-// CHECK: sshll2 v0.2d, v1.4s, #0        // encoding: [0x20,0xa4,0x20,0x4f]
+// CHECK: sxtl2 v0.8h, v1.16b       // encoding: [0x20,0xa4,0x08,0x4f]
+// CHECK: sxtl2 v0.4s, v1.8h        // encoding: [0x20,0xa4,0x10,0x4f]
+// CHECK: sxtl2 v0.2d, v1.4s        // encoding: [0x20,0xa4,0x20,0x4f]
Index: test/MC/AArch64/neon-uxtl.s
===================================================================
--- test/MC/AArch64/neon-uxtl.s
+++ test/MC/AArch64/neon-uxtl.s
@@ -9,9 +9,9 @@
         uxtl v0.4s, v1.4h
         uxtl v0.2d, v1.2s
 
-// CHECK: ushll v0.8h, v1.8b, #0        // encoding: [0x20,0xa4,0x08,0x2f]
-// CHECK: ushll v0.4s, v1.4h, #0        // encoding: [0x20,0xa4,0x10,0x2f]
-// CHECK: ushll v0.2d, v1.2s, #0        // encoding: [0x20,0xa4,0x20,0x2f]
+// CHECK: uxtl v0.8h, v1.8b        // encoding: [0x20,0xa4,0x08,0x2f]
+// CHECK: uxtl v0.4s, v1.4h        // encoding: [0x20,0xa4,0x10,0x2f]
+// CHECK: uxtl v0.2d, v1.2s        // encoding: [0x20,0xa4,0x20,0x2f]
 
 //------------------------------------------------------------------------------
 // Unsigned integer lengthen (vector, second part)
@@ -21,6 +21,6 @@
         uxtl2 v0.4s, v1.8h
         uxtl2 v0.2d, v1.4s
 
-// CHECK: ushll2 v0.8h, v1.16b, #0       // encoding: [0x20,0xa4,0x08,0x6f]
-// CHECK: ushll2 v0.4s, v1.8h, #0        // encoding: [0x20,0xa4,0x10,0x6f]
-// CHECK: ushll2 v0.2d, v1.4s, #0        // encoding: [0x20,0xa4,0x20,0x6f]
+// CHECK: uxtl2 v0.8h, v1.16b       // encoding: [0x20,0xa4,0x08,0x6f]
+// CHECK: uxtl2 v0.4s, v1.8h        // encoding: [0x20,0xa4,0x10,0x6f]
+// CHECK: uxtl2 v0.2d, v1.4s        // encoding: [0x20,0xa4,0x20,0x6f]