[AArch64] Fix disassembly of SXTL and UXTL aliases

[olista01]

Summary

These instructions are aliases of SSHLL and USHLL, and should be
preferred for disassembly.

We did already have aliases for these in the tablegen, but they were
not being used. The problem was that we actually had two aliases for
each, one each for the "generic" and "apple-neon" syntaxes. This made
the disassembly ambiguous, so tablegen was not emitting either of them.
The fix was to use one alias with both syntaxes in the string, so that
the correct one can be picked by the disassembler.

This fixes https://bugs.llvm.org/show_bug.cgi?id=39721

[rengolin]

I'm not sure what's the supposed behaviour on Apple syntax, but the tests show both apple and eabi syntax changing to the recommended encoding, so this LGTM.

Adding Tim to confirm the behaviour on Apple mode.

[olista01]

Ping

[rengolin]

@t.p.northover Is this the correct behaviour for Apple's syntax?

lib/Target/AArch64/AArch64InstrInfo.td

 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
           (USHLLv4i32_shift V128:$Rn, (i32 0))>;
 def : Pat<(v2i64 (zext   (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
           (USHLLv4i32_shift V128:$Rn, (i32 0))>;
 def : Pat<(v2i64 (sext   (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
           (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
 
 // Vector shift sxtl aliases
-def : InstAlias<"sxtl.8h $dst, $src1",
+def : InstAlias<"sxtl{ $dst.8h, $src1.8b|.8h $dst, $src1}",
                 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.8h, $src1.8b",
-                (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl.4s $dst, $src1",
-                (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.4s, $src1.4h",
+def : InstAlias<"sxtl{ $dst.4s, $src1.4h|.4s $dst, $src1}",
                 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl.2d $dst, $src1",
-                (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"sxtl $dst.2d, $src1.2s",
+def : InstAlias<"sxtl{ $dst.2d, $src1.2s|.2d $dst, $src1}",
                 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
 
 // Vector shift sxtl2 aliases
-def : InstAlias<"sxtl2.8h $dst, $src1",
+def : InstAlias<"sxtl2{ $dst.8h, $src1.16b|.8h $dst, $src1}",
                 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
-                (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2.4s $dst, $src1",
-                (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
+def : InstAlias<"sxtl2{ $dst.4s, $src1.8h|.4s $dst, $src1}",
                 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2.2d $dst, $src1",
-                (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
+def : InstAlias<"sxtl2{ $dst.2d, $src1.4s|.2d $dst, $src1}",
                 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 
 // Vector shift uxtl aliases
-def : InstAlias<"uxtl.8h $dst, $src1",
+def : InstAlias<"uxtl{ $dst.8h, $src1.8b|.8h $dst, $src1}",
                 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.8h, $src1.8b",
-                (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl.4s $dst, $src1",
-                (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.4s, $src1.4h",
+def : InstAlias<"uxtl{ $dst.4s, $src1.4h|.4s $dst, $src1}",
                 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl.2d $dst, $src1",
-                (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
-def : InstAlias<"uxtl $dst.2d, $src1.2s",
+def : InstAlias<"uxtl{ $dst.2d, $src1.2s|.2d $dst, $src1}",
                 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
 
 // Vector shift uxtl2 aliases
-def : InstAlias<"uxtl2.8h $dst, $src1",
+def : InstAlias<"uxtl2{ $dst.8h, $src1.16b|.8h $dst, $src1}",
                 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
-                (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2.4s $dst, $src1",
-                (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
+def : InstAlias<"uxtl2{ $dst.4s, $src1.8h|.4s $dst, $src1}",
                 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2.2d $dst, $src1",
-                (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
-def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
+def : InstAlias<"uxtl2{ $dst.2d, $src1.4s|.2d $dst, $src1}",
                 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
 
 // If an integer is about to be converted to a floating point value,
 // just load it on the floating point unit.
 // These patterns are more complex because floating point loads do not
 // support sign extension.
 // The sign extension has to be explicitly added and is only supported for
 // one step: byte-to-half, half-to-word, word-to-doubleword.

test/CodeGen/AArch64/arm64-extend-int-to-fp.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 define <4 x float> @foo(<4 x i16> %a) nounwind {
 ; CHECK-LABEL: foo:
-; CHECK: ushll.4s v0, v0, #0
+; CHECK: uxtl.4s  v0, v0
 ; CHECK-NEXT: ucvtf.4s  v0, v0
 ; CHECK-NEXT: ret
   %vcvt.i = uitofp <4 x i16> %a to <4 x float>
   ret <4 x float> %vcvt.i
 }
 
 define <4 x float> @bar(<4 x i16> %a) nounwind {
 ; CHECK-LABEL: bar:
-; CHECK: sshll.4s v0, v0, #0
+; CHECK: sxtl.4s  v0, v0
 ; CHECK-NEXT: scvtf.4s  v0, v0
 ; CHECK-NEXT: ret
   %vcvt.i = sitofp <4 x i16> %a to <4 x float>
   ret <4 x float> %vcvt.i
 }

test/CodeGen/AArch64/arm64-fast-isel-noconvert.ll

 ; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=aarch64-apple-ios < %s | FileCheck %s
 
 ; Fast-isel can't do vector conversions yet, but it was emitting some highly
 ; suspect UCVTFUWDri MachineInstrs.
 define <4 x float> @test_uitofp(<4 x i32> %in) {
 ; CHECK-LABEL: test_uitofp:
 ; CHECK: ucvtf.4s v0, v0
 
   %res = uitofp <4 x i32> %in to <4 x float>
   ret <4 x float> %res
 }
 
 define <2 x double> @test_sitofp(<2 x i32> %in) {
 ; CHECK-LABEL: test_sitofp:
-; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
+; CHECK: sxtl.2d [[EXT:v[0-9]+]], v0
 ; CHECK: scvtf.2d v0, [[EXT]]
 
   %res = sitofp <2 x i32> %in to <2 x double>
   ret <2 x double> %res
 }
 
 define <2 x i32> @test_fptoui(<2 x float> %in) {
 ; CHECK-LABEL: test_fptoui:

test/CodeGen/AArch64/arm64-ld1.ll

 
 
 ; Add rdar://13098923 test case: vld1_dup_u32 doesn't generate ld1r.2s
 define void @ld1r_2s_from_dup(i8* nocapture %a, i8* nocapture %b, i16* nocapture %diff) nounwind ssp {
 entry:
 ; CHECK: ld1r_2s_from_dup
 ; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
 ; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
-; CHECK-NEXT: ushll.8h [[ARG1]], [[ARG1]], #0
-; CHECK-NEXT: ushll.8h [[ARG2]], [[ARG2]], #0
+; CHECK-NEXT: uxtl.8h [[ARG1]], [[ARG1]]
+; CHECK-NEXT: uxtl.8h [[ARG2]], [[ARG2]]
 ; CHECK-NEXT: sub.4h v[[RESREGNUM:[0-9]+]], [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: str d[[RESREGNUM]], [x2]
 ; CHECK-NEXT: ret
   %tmp = bitcast i8* %a to i32*
   %tmp1 = load i32, i32* %tmp, align 4
   %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
   %lane = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
   %tmp3 = bitcast <2 x i32> %lane to <8 x i8>

test/CodeGen/AArch64/arm64-scvt.ll

; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   ret double %vmull.i
 
 }
 
 ; ********* 1s. load with scaled imm to float. *********
 define float @sfct1(i8* nocapture %sp0) {
 ; CHECK-LABEL: sfct1:
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct1:
 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 1
   %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
 }
 
 define float @sfct2(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct2:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
entry:
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
 }
 
 ; ********* 2s. load with scaled register to float. *********
 define float @sfct5(i8* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct5:
 ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct5:
 ; CHECK-A57: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i8, i8* %sp0, i64 %offset
   %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
 }
 
 define float @sfct6(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct6:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
entry:
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct10(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct10:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct10:
 ; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, #2]
 ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 1
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct11(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct11:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 1
   %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
entry:
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct14(i16* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct14:
 ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct14:
 ; CHECK-A57: ldrsh w[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
 ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i16, i16* %sp0, i64 %offset
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct15(i32* nocapture %sp0, i64 %offset) {
 ; CHECK-LABEL: sfct15:
 ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 entry:
   %addr = getelementptr i32, i32* %sp0, i64 %offset
   %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
entry:
   ret double %vmull.i
 }
 
 ; ********* 5s. load with unscaled imm to float. *********
 define float @sfct17(i8* nocapture %sp0) {
 entry:
 ; CHECK-LABEL: sfct17:
 ; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct17:
 ; CHECK-A57: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
 ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]]
   %bitcast = ptrtoint i8* %sp0 to i64
   %add = add i64 %bitcast, -1
   %addr = inttoptr i64 %add to i8*
   %pix_sp0.0.copyload = load i8, i8* %addr, align 1
   %val = sitofp i8 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
   ret float %vmull.i
 }
 
 define float @sfct18(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct18:
 ; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
 ; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to float
   %vmull.i = fmul float %val, %val
; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   %val = sitofp i8 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct22(i16* nocapture %sp0) {
 ; CHECK-LABEL: sfct22:
 ; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
+; CHECK-NEXT: sxtl.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]]
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
 ; CHECK-A57-LABEL: sfct22:
 ; CHECK-A57: ldursh w[[REGNUM:[0-9]+]], [x0, #1]
 ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
 ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]]
   %bitcast = ptrtoint i16* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i16*
   %pix_sp0.0.copyload = load i16, i16* %addr, align 1
   %val = sitofp i16 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val
   ret double %vmull.i
 }
 
 define double @sfct23(i32* nocapture %sp0) {
 ; CHECK-LABEL: sfct23:
 ; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
+; CHECK-NEXT: sxtl.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]]
 ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
 ; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
   %bitcast = ptrtoint i32* %sp0 to i64
   %add = add i64 %bitcast, 1
   %addr = inttoptr i64 %add to i32*
   %pix_sp0.0.copyload = load i32, i32* %addr, align 1
   %val = sitofp i32 %pix_sp0.0.copyload to double
   %vmull.i = fmul double %val, %val

test/CodeGen/AArch64/arm64-subvector-extend.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
 
 ; Test efficient codegen of vector extends up from legal type to 128 bit
 ; and 256 bit vector types.
 
 ;-----
 ; Vectors of i16.
 ;-----
 define <8 x i16> @func1(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: func1:
-; CHECK-NEXT: ushll.8h  v0, v0, #0
+; CHECK-NEXT: uxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i8> %v0 to <8 x i16>
   ret <8 x i16> %r
 }
 
 define <8 x i16> @func2(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: func2:
-; CHECK-NEXT: sshll.8h  v0, v0, #0
+; CHECK-NEXT: sxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i8> %v0 to <8 x i16>
   ret <8 x i16> %r
 }
 
 define <16 x i16> @func3(<16 x i8> %v0) nounwind {
 ; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll2.8h  v1, v0, #0
-; CHECK-NEXT: ushll.8h  v0, v0, #0
+; CHECK-NEXT: uxtl2.8h  v1, v0
+; CHECK-NEXT: uxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <16 x i8> %v0 to <16 x i16>
   ret <16 x i16> %r
 }
 
 define <16 x i16> @func4(<16 x i8> %v0) nounwind {
 ; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll2.8h  v1, v0, #0
-; CHECK-NEXT: sshll.8h  v0, v0, #0
+; CHECK-NEXT: sxtl2.8h  v1, v0
+; CHECK-NEXT: sxtl.8h  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <16 x i8> %v0 to <16 x i16>
   ret <16 x i16> %r
 }
 
 ;-----
 ; Vectors of i32.
 ;-----
 
 define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc1:
-; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: uxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i16> %v0 to <4 x i32>
   ret <4 x i32> %r
 }
 
 define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc2:
-; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: sxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i16> %v0 to <4 x i32>
   ret <4 x i32> %r
 }
 
 define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc3:
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: uxtl2.4s v1, v0
+; CHECK-NEXT: uxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i16> %v0 to <8 x i32>
   ret <8 x i32> %r
 }
 
 define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
 ; CHECK-LABEL: afunc4:
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s v0, v0, #0
+; CHECK-NEXT: sxtl2.4s v1, v0
+; CHECK-NEXT: sxtl.4s v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i16> %v0 to <8 x i32>
   ret <8 x i32> %r
 }
 
 define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: bfunc1:
-; CHECK-NEXT: ushll.8h  v0, v0, #0
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s  v0, v0, #0
+; CHECK-NEXT: uxtl.8h  v0, v0
+; CHECK-NEXT: uxtl2.4s v1, v0
+; CHECK-NEXT: uxtl.4s  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <8 x i8> %v0 to <8 x i32>
   ret <8 x i32> %r
 }
 
 define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
 ; CHECK-LABEL: bfunc2:
-; CHECK-NEXT: sshll.8h  v0, v0, #0
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s  v0, v0, #0
+; CHECK-NEXT: sxtl.8h  v0, v0
+; CHECK-NEXT: sxtl2.4s v1, v0
+; CHECK-NEXT: sxtl.4s  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <8 x i8> %v0 to <8 x i32>
   ret <8 x i32> %r
 }
 
 ;-----
 ; Vectors of i64.
 ;-----
 
 define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
 ; CHECK-LABEL: zfunc1:
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
+; CHECK-NEXT: uxtl2.2d v1, v0
+; CHECK-NEXT: uxtl.2d v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i32> %v0 to <4 x i64>
   ret <4 x i64> %r
 }
 
 define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
 ; CHECK-LABEL: zfunc2:
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d v0, v0, #0
+; CHECK-NEXT: sxtl2.2d v1, v0
+; CHECK-NEXT: sxtl.2d v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i32> %v0 to <4 x i64>
   ret <4 x i64> %r
 }
 
 define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll.4s  v0, v0, #0
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d  v0, v0, #0
+; CHECK-NEXT: uxtl.4s  v0, v0
+; CHECK-NEXT: uxtl2.2d v1, v0
+; CHECK-NEXT: uxtl.2d  v0, v0
 ; CHECK-NEXT: ret
   %r = zext <4 x i16> %v0 to <4 x i64>
   ret <4 x i64> %r
 }
 
 define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
 ; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll.4s  v0, v0, #0
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d  v0, v0, #0
+; CHECK-NEXT: sxtl.4s  v0, v0
+; CHECK-NEXT: sxtl2.2d v1, v0
+; CHECK-NEXT: sxtl.2d  v0, v0
 ; CHECK-NEXT: ret
   %r = sext <4 x i16> %v0 to <4 x i64>
   ret <4 x i64> %r
 }

test/CodeGen/AArch64/arm64-vbitwise.ll

;CHECK: rbit.16b
   ret <16 x i8> %tmp3
 }
 
 declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
 
 define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: sxtl8h:
-;CHECK: sshll.8h
+;CHECK: sxtl.8h
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
 }
 
 define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
 ;CHECK-LABEL: uxtl8h:
-;CHECK: ushll.8h
+;CHECK: uxtl.8h
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
   ret <8 x i16> %tmp2
 }
 
 define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: sxtl4s:
-;CHECK: sshll.4s
+;CHECK: sxtl.4s
   %tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
 }
 
 define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
 ;CHECK-LABEL: uxtl4s:
-;CHECK: ushll.4s
+;CHECK: uxtl.4s
   %tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
   ret <4 x i32> %tmp2
 }
 
 define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: sxtl2d:
-;CHECK: sshll.2d
+;CHECK: sxtl.2d
   %tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
 }
 
 define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
 ;CHECK-LABEL: uxtl2d:
-;CHECK: ushll.2d
+;CHECK: uxtl.2d
   %tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
   ret <2 x i64> %tmp2
 }
 
 ; Check for incorrect use of vector bic.
 ; rdar://11553859
 define void @test_vsliq(i8* nocapture %src, i8* nocapture %dest) nounwind noinline ssp {

test/CodeGen/AArch64/arm64-vector-ext.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ;CHECK: @func30
 ;CHECK: movi.4h v1, #1
 ;CHECK: and.8b v0, v0, v1
-;CHECK: ushll.4s  v0, v0, #0
+;CHECK: uxtl.4s  v0, v0
 ;CHECK: str  q0, [x0]
 ;CHECK: ret
 
 %T0_30 = type <4 x i1>
 %T1_30 = type <4 x i32>
 define void @func30(%T0_30 %v0, %T1_30* %p1) {
   %r = zext %T0_30 %v0 to %T1_30
   store %T1_30 %r, %T1_30* %p1

test/CodeGen/AArch64/complex-int-to-fp.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ; CHECK: autogen_SD19655
 ; CHECK: scvtf
 ; CHECK: ret
 define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) {
   %T = load <2 x i64>, <2 x i64>* %addr
   %F = sitofp <2 x i64> %T to <2 x float>
   store <2 x float> %F, <2 x float>* %addrfloat
   ret void
 }
 
 define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v2i32_to_v2f64:
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], v0
 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
 ; CHECK-NEXT: ret
   %conv = sitofp <2 x i32> %v to <2 x double>
   ret <2 x double> %conv
 }
 
 define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], v0
 ; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
 ; CHECK-NEXT: ret
   %conv = uitofp <2 x i32> %v to <2 x double>
   ret <2 x double> %conv
 }
 
 define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v2i16_to_v2f64:
 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: scvtf.2d v0, [[VAL64]]
 
   %conv = sitofp <2 x i16> %v to <2 x double>
   ret <2 x double> %conv
 }
 define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: ucvtf.2d v0, [[VAL64]]
 
   %conv = uitofp <2 x i16> %v to <2 x double>
   ret <2 x double> %conv
 }
 
 define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v2i8_to_v2f64:
 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
-; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: sxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: scvtf.2d v0, [[VAL64]]
 
   %conv = sitofp <2 x i8> %v to <2 x double>
   ret <2 x double> %conv
 }
 define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
-; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
+; CHECK: uxtl.2d [[VAL64:v[0-9]+]], [[VAL32]]
 ; CHECK: ucvtf.2d v0, [[VAL64]]
 
   %conv = uitofp <2 x i8> %v to <2 x double>
   ret <2 x double> %conv
 }
 
 define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v2i64_to_v2f32:

 ; CHECK: ucvtf.2s v0, [[VAL32]]
 
   %conv = uitofp <2 x i8> %v to <2 x float>
   ret <2 x float> %conv
 }
 
 define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v4i16_to_v4f32:
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: sxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: scvtf.4s v0, [[VAL32]]
 
   %conv = sitofp <4 x i16> %v to <4 x float>
   ret <4 x float> %conv
 }
 
 define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: uxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: ucvtf.4s v0, [[VAL32]]
 
   %conv = uitofp <4 x i16> %v to <4 x float>
   ret <4 x float> %conv
 }
 
 define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: test_signed_v4i8_to_v4f32:
 ; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
-; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
+; CHECK: sxtl.4s [[VAL32:v[0-9]+]], [[VAL16]]
 ; CHECK: scvtf.4s v0, [[VAL32]]
 
   %conv = sitofp <4 x i8> %v to <4 x float>
   ret <4 x float> %conv
 }
 define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
 ; CHECK: bic.4h v0, #255, lsl #8
-; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
+; CHECK: uxtl.4s [[VAL32:v[0-9]+]], v0
 ; CHECK: ucvtf.4s v0, [[VAL32]]
 
   %conv = uitofp <4 x i8> %v to <4 x float>
   ret <4 x float> %conv
 }

test/CodeGen/AArch64/fast-isel-cmp-vec.ll

 define <4 x i32> @icmp_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_v4i32:
 ; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  cmeq.4s [[CMP:v[0-9]+]], v0, #0
 ; CHECK-NEXT:  xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]]
 ; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
-; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
+; CHECK-NEXT:  uxtl.4s v0, [[ZEXT]]
 ; CHECK-NEXT:  ret
   %c = icmp eq <4 x i32> %a, zeroinitializer
   br label %bb2
 bb2:
   %z = zext <4 x i1> %c to <4 x i32>
   ret <4 x i32> %z
 }
 
 define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v4i32:
 ; CHECK:      ; %bb.0:
 ; CHECK-NEXT:  movi.2d v[[CMP:[0-9]+]], #0xffffffffffffffff
 ; CHECK-NEXT: ; %bb.1:
 ; CHECK-NEXT:  movi.4h [[MASK:v[0-9]+]], #1
 ; CHECK-NEXT:  and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
-; CHECK-NEXT:  ushll.4s v0, [[ZEXT]], #0
+; CHECK-NEXT:  uxtl.4s v0, [[ZEXT]]
 ; CHECK-NEXT:  ret
   %1 = icmp eq <4 x i32> %a, %a
   br label %bb2
 bb2:
   %2 = zext <4 x i1> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 

test/CodeGen/AArch64/fdiv_combine.ll

 entry:
   %vcvt.i = sitofp <4 x i32> %in to <4 x float>
   %div.i = fdiv <4 x float> %vcvt.i, <float 4.0, float 4.0, float 4.0, float 4.0>
   ret <4 x float> %div.i
 }
 
 ; Test unsigned i16 to float
 ; CHECK-LABEL: @test7
-; CHECK: ushll.4s  v0, v0, #0
+; CHECK: uxtl.4s  v0, v0
 ; CHECK: ucvtf.4s  v0, v0, #1
 ; CHECK: ret
 define <4 x float> @test7(<4 x i16> %in) {
   %conv = uitofp <4 x i16> %in to <4 x float>
   %shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
   ret <4 x float> %shift
 }
 
 ; Test signed i16 to float
 ; CHECK-LABEL: @test8
-; CHECK: sshll.4s v0, v0, #0
+; CHECK: sxtl.4s v0, v0
 ; CHECK: scvtf.4s v0, v0, #2
 ; CHECK: ret
 define <4 x float> @test8(<4 x i16> %in) {
   %conv = sitofp <4 x i16> %in to <4 x float>
   %shift = fdiv <4 x float> %conv, <float 4.0, float 4.0, float 4.0, float 4.0>
   ret <4 x float> %shift
 }
 

test/CodeGen/AArch64/fp16-v4-instructions.ll

; CHECK-COMMON-NEXT:  ret
   %2 = bitcast <4 x half> %a to <4 x i16>
   ret <4 x i16> %2
 }
 
 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
 ; CHECK-COMMON-LABEL: sitofp_i8:
 ; CHECK-COMMON-NEXT:  shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
 ; CHECK-COMMON-NEXT:  sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
-; CHECK-COMMON-NEXT:  sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
+; CHECK-COMMON-NEXT:  sxtl [[OP3:v[0-9]+\.4s]], [[OP2]]
 ; CHECK-COMMON-NEXT:  scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP4]]
 ; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i8> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
 ; CHECK-COMMON-LABEL: sitofp_i16:
-; CHECK-COMMON-NEXT:  sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  sxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i16> %a to <4 x half>
   ret <4 x half> %1
 }
 
 

 ; CHECK-COMMON-NEXT:  ret
   %1 = sitofp <4 x i64> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
 ; CHECK-COMMON-LABEL: uitofp_i8:
 ; CHECK-COMMON-NEXT:  bic v0.4h, #255, lsl #8
-; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  uxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i8> %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
 ; CHECK-COMMON-LABEL: uitofp_i16:
-; CHECK-COMMON-NEXT:  ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-COMMON-NEXT:  uxtl [[OP1:v[0-9]+\.4s]], v0.4h
 ; CHECK-COMMON-NEXT:  ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
 ; CHECK-COMMON-NEXT:  fcvtn v0.4h, [[OP2]]
 ; CHECK-COMMON-NEXT:  ret
   %1 = uitofp <4 x i16> %a to <4 x half>
   ret <4 x half> %1
 }
 
 

test/CodeGen/AArch64/fp16-v8-instructions.ll

 ; CHECK: mov v0.16b, v1.16b
   %2 = bitcast <8 x half> %a to <8 x i16>
   ret <8 x i16> %2
 }
 
 
 define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-LABEL: sitofp_i8:
-; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-NEXT: sxtl v[[REG1:[0-9]+]].8h, v0.8b
+; CHECK-NEXT: sxtl2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h
+; CHECK-NEXT: sxtl  [[HI:v[0-9]+\.4s]], v[[REG1]].4h
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: sitofp_i16:
-; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-NEXT: sshll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: sxtl2 [[LO:v[0-9]+\.4s]], v0.8h
+; CHECK-NEXT: sxtl  [[HI:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = sitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }

 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
 ; CHECK: fcvtn v0.4h, [[OP3]].4s
   %1 = sitofp <8 x i64> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-LABEL: uitofp_i8:
-; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
-; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
-; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
+; CHECK-NEXT: uxtl v[[REG1:[0-9]+]].8h, v0.8b
+; CHECK-NEXT: uxtl2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h
+; CHECK-NEXT: uxtl  [[HI:v[0-9]+\.4s]], v[[REG1]].4h
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-LABEL: uitofp_i16:
-; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
-; CHECK-NEXT: ushll  [[HI:v[0-9]+\.4s]], v0.4h, #0
+; CHECK-NEXT: uxtl2 [[LO:v[0-9]+\.4s]], v0.8h
+; CHECK-NEXT: uxtl  [[HI:v[0-9]+\.4s]], v0.4h
 ; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
 ; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
 ; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
 ; CHECK-DAG: fcvtn v0.4h, [[HIF]]
 ; CHECK: mov v0.d[1], v[[LOREG]].d[0]
   %1 = uitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }

test/CodeGen/AArch64/neon-shift-left-long.ll

; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
   %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %2 = zext <2 x i32> %1 to <2 x i64>
   %tmp = shl <2 x i64> %2, <i64 19, i64 19>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) {
 ; CHECK: test_sshll_shl0_v8i8:
-; CHECK: sshll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK: sxtl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %tmp = sext <8 x i8> %a to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) {
 ; CHECK: test_sshll_shl0_v4i16:
-; CHECK: sshll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK: sxtl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
   %tmp = sext <4 x i16> %a to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) {
 ; CHECK: test_sshll_shl0_v2i32:
-; CHECK: sshll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK: sxtl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
   %tmp = sext <2 x i32> %a to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) {
 ; CHECK: test_ushll_shl0_v8i8:
-; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK: uxtl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %tmp = zext <8 x i8> %a to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) {
 ; CHECK: test_ushll_shl0_v4i16:
-; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
+; CHECK: uxtl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
   %tmp = zext <4 x i16> %a to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) {
 ; CHECK: test_ushll_shl0_v2i32:
-; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
+; CHECK: uxtl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
   %tmp = zext <2 x i32> %a to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) {
 ; CHECK: test_sshll2_shl0_v16i8:
-; CHECK: sshll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK: sxtl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
   %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %tmp = sext <8 x i8> %1 to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) {
 ; CHECK: test_sshll2_shl0_v8i16:
-; CHECK: sshll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK: sxtl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
   %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp = sext <4 x i16> %1 to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) {
 ; CHECK: test_sshll2_shl0_v4i32:
-; CHECK: sshll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK: sxtl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
   %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp = sext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) {
 ; CHECK: test_ushll2_shl0_v16i8:
-; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
+; CHECK: uxtl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
   %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %tmp = zext <8 x i8> %1 to <8 x i16>
   ret <8 x i16> %tmp
 }
 
 define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) {
 ; CHECK: test_ushll2_shl0_v8i16:
-; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
+; CHECK: uxtl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
   %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %tmp = zext <4 x i16> %1 to <4 x i32>
   ret <4 x i32> %tmp
 }
 
 define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {
 ; CHECK: test_ushll2_shl0_v4i32:
-; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
+; CHECK: uxtl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
   %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %tmp = zext <2 x i32> %1 to <2 x i64>
   ret <2 x i64> %tmp
 }
 
 define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {
 ; CHECK: test_ushll_cmp:
 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
+; CHECK-NEXT: uxtl  {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
   %cmp.i = icmp eq <8 x i8> %a, %b
   %vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>
   %vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>
   ret <8 x i16> %vmovl.i.i.i
 }

test/CodeGen/AArch64/sitofp-fixed-legal.ll

 ; RUN: llc -mtriple=aarch64-apple-ios %s -o - | FileCheck %s
 
 define <16 x double> @test_sitofp_fixed(<16 x i32> %in) {
 ; CHECK-LABEL: test_sitofp_fixed:
 
   ; First, extend each i32 to i64
-; CHECK-DAG: sshll2.2d [[BLOCK0_HI:v[0-9]+]], v0, #0
-; CHECK-DAG: sshll2.2d [[BLOCK1_HI:v[0-9]+]], v1, #0
-; CHECK-DAG: sshll2.2d [[BLOCK2_HI:v[0-9]+]], v2, #0
-; CHECK-DAG: sshll2.2d [[BLOCK3_HI:v[0-9]+]], v3, #0
-; CHECK-DAG: sshll.2d [[BLOCK0_LO:v[0-9]+]], v0, #0
-; CHECK-DAG: sshll.2d [[BLOCK1_LO:v[0-9]+]], v1, #0
-; CHECK-DAG: sshll.2d [[BLOCK2_LO:v[0-9]+]], v2, #0
-; CHECK-DAG: sshll.2d [[BLOCK3_LO:v[0-9]+]], v3, #0
+; CHECK-DAG: sxtl2.2d [[BLOCK0_HI:v[0-9]+]], v0
+; CHECK-DAG: sxtl2.2d [[BLOCK1_HI:v[0-9]+]], v1
+; CHECK-DAG: sxtl2.2d [[BLOCK2_HI:v[0-9]+]], v2
+; CHECK-DAG: sxtl2.2d [[BLOCK3_HI:v[0-9]+]], v3
+; CHECK-DAG: sxtl.2d [[BLOCK0_LO:v[0-9]+]], v0
+; CHECK-DAG: sxtl.2d [[BLOCK1_LO:v[0-9]+]], v1
+; CHECK-DAG: sxtl.2d [[BLOCK2_LO:v[0-9]+]], v2
+; CHECK-DAG: sxtl.2d [[BLOCK3_LO:v[0-9]+]], v3
 
   ; Next, convert each to double.
 ; CHECK-DAG: scvtf.2d v0, [[BLOCK0_LO]]
 ; CHECK-DAG: scvtf.2d v1, [[BLOCK0_HI]]
 ; CHECK-DAG: scvtf.2d v2, [[BLOCK1_LO]]
 ; CHECK-DAG: scvtf.2d v3, [[BLOCK1_HI]]
 ; CHECK-DAG: scvtf.2d v4, [[BLOCK2_LO]]
 ; CHECK-DAG: scvtf.2d v5, [[BLOCK2_HI]]

test/MC/AArch64/arm64-aliases.s

; CHECK: facge d0, d1, d2
   faclt d0, d2, d1
 ; CHECK: facgt s0, s1, s2
 ; CHECK: facgt d0, d1, d2
 
 ;-----------------------------------------------------------------------------
 ; 5.8.14 Vector Shift (immediate)
 ;-----------------------------------------------------------------------------
   sxtl v1.8h, v2.8b
-; CHECK: sshll.8h v1, v2, #0
+; CHECK: sxtl.8h v1, v2
   sxtl.8h v1, v2
-; CHECK: sshll.8h v1, v2, #0
+; CHECK: sxtl.8h v1, v2
 
   sxtl v1.4s, v2.4h
-; CHECK: sshll.4s v1, v2, #0
+; CHECK: sxtl.4s v1, v2
   sxtl.4s v1, v2
-; CHECK: sshll.4s v1, v2, #0
+; CHECK: sxtl.4s v1, v2
 
   sxtl v1.2d, v2.2s
-; CHECK: sshll.2d v1, v2, #0
+; CHECK: sxtl.2d v1, v2
   sxtl.2d v1, v2
-; CHECK: sshll.2d v1, v2, #0
+; CHECK: sxtl.2d v1, v2
 
   sxtl2 v1.8h, v2.16b
-; CHECK: sshll2.8h v1, v2, #0
+; CHECK: sxtl2.8h v1, v2
   sxtl2.8h v1, v2
-; CHECK: sshll2.8h v1, v2, #0
+; CHECK: sxtl2.8h v1, v2
 
   sxtl2 v1.4s, v2.8h
-; CHECK: sshll2.4s v1, v2, #0
+; CHECK: sxtl2.4s v1, v2
   sxtl2.4s v1, v2
-; CHECK: sshll2.4s v1, v2, #0
+; CHECK: sxtl2.4s v1, v2
 
   sxtl2 v1.2d, v2.4s
-; CHECK: sshll2.2d v1, v2, #0
+; CHECK: sxtl2.2d v1, v2
   sxtl2.2d v1, v2
-; CHECK: sshll2.2d v1, v2, #0
+; CHECK: sxtl2.2d v1, v2
 
   uxtl v1.8h, v2.8b
-; CHECK: ushll.8h v1, v2, #0
+; CHECK: uxtl.8h v1, v2
   uxtl.8h v1, v2
-; CHECK: ushll.8h v1, v2, #0
+; CHECK: uxtl.8h v1, v2
 
   uxtl v1.4s, v2.4h
-; CHECK: ushll.4s v1, v2, #0
+; CHECK: uxtl.4s v1, v2
   uxtl.4s v1, v2
-; CHECK: ushll.4s v1, v2, #0
+; CHECK: uxtl.4s v1, v2
 
   uxtl v1.2d, v2.2s
-; CHECK: ushll.2d v1, v2, #0
+; CHECK: uxtl.2d v1, v2
   uxtl.2d v1, v2
-; CHECK: ushll.2d v1, v2, #0
+; CHECK: uxtl.2d v1, v2
 
   uxtl2 v1.8h, v2.16b
-; CHECK: ushll2.8h v1, v2, #0
+; CHECK: uxtl2.8h v1, v2
   uxtl2.8h v1, v2
-; CHECK: ushll2.8h v1, v2, #0
+; CHECK: uxtl2.8h v1, v2
 
   uxtl2 v1.4s, v2.8h
-; CHECK: ushll2.4s v1, v2, #0
+; CHECK: uxtl2.4s v1, v2
   uxtl2.4s v1, v2
-; CHECK: ushll2.4s v1, v2, #0
+; CHECK: uxtl2.4s v1, v2
 
   uxtl2 v1.2d, v2.4s
-; CHECK: ushll2.2d v1, v2, #0
+; CHECK: uxtl2.2d v1, v2
   uxtl2.2d v1, v2
-; CHECK: ushll2.2d v1, v2, #0
+; CHECK: uxtl2.2d v1, v2
 
 
 ;-----------------------------------------------------------------------------
 ; MOVI verbose syntax with shift operand omitted.
 ;-----------------------------------------------------------------------------
   movi v4.16b, #0x00
   movi v4.16B, #0x01
   movi v4.8b, #0x02

test/MC/AArch64/neon-sxtl.s

 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
 
 // Check that the assembler can handle the documented syntax for AArch64
 
 //------------------------------------------------------------------------------
 // Signed integer lengthen (vector)
 //------------------------------------------------------------------------------
         sxtl v0.8h, v1.8b
         sxtl v0.4s, v1.4h
         sxtl v0.2d, v1.2s
 
-// CHECK: sshll v0.8h, v1.8b, #0        // encoding: [0x20,0xa4,0x08,0x0f]
-// CHECK: sshll v0.4s, v1.4h, #0        // encoding: [0x20,0xa4,0x10,0x0f]
-// CHECK: sshll v0.2d, v1.2s, #0        // encoding: [0x20,0xa4,0x20,0x0f]
+// CHECK: sxtl v0.8h, v1.8b        // encoding: [0x20,0xa4,0x08,0x0f]
+// CHECK: sxtl v0.4s, v1.4h        // encoding: [0x20,0xa4,0x10,0x0f]
+// CHECK: sxtl v0.2d, v1.2s        // encoding: [0x20,0xa4,0x20,0x0f]
 
 //------------------------------------------------------------------------------
 // Signed integer lengthen (vector, second part)
 //------------------------------------------------------------------------------
 
         sxtl2 v0.8h, v1.16b
         sxtl2 v0.4s, v1.8h
         sxtl2 v0.2d, v1.4s
 
-// CHECK: sshll2 v0.8h, v1.16b, #0        // encoding: [0x20,0xa4,0x08,0x4f]
-// CHECK: sshll2 v0.4s, v1.8h, #0        // encoding: [0x20,0xa4,0x10,0x4f]
-// CHECK: sshll2 v0.2d, v1.4s, #0        // encoding: [0x20,0xa4,0x20,0x4f]
+// CHECK: sxtl2 v0.8h, v1.16b       // encoding: [0x20,0xa4,0x08,0x4f]
+// CHECK: sxtl2 v0.4s, v1.8h        // encoding: [0x20,0xa4,0x10,0x4f]
+// CHECK: sxtl2 v0.2d, v1.4s        // encoding: [0x20,0xa4,0x20,0x4f]

test/MC/AArch64/neon-uxtl.s

 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
 
 // Check that the assembler can handle the documented syntax for AArch64
 
 //------------------------------------------------------------------------------
 // Unsigned integer lengthen (vector)
 //------------------------------------------------------------------------------
         uxtl v0.8h, v1.8b
         uxtl v0.4s, v1.4h
         uxtl v0.2d, v1.2s
 
-// CHECK: ushll v0.8h, v1.8b, #0        // encoding: [0x20,0xa4,0x08,0x2f]
-// CHECK: ushll v0.4s, v1.4h, #0        // encoding: [0x20,0xa4,0x10,0x2f]
-// CHECK: ushll v0.2d, v1.2s, #0        // encoding: [0x20,0xa4,0x20,0x2f]
+// CHECK: uxtl v0.8h, v1.8b        // encoding: [0x20,0xa4,0x08,0x2f]
+// CHECK: uxtl v0.4s, v1.4h        // encoding: [0x20,0xa4,0x10,0x2f]
+// CHECK: uxtl v0.2d, v1.2s        // encoding: [0x20,0xa4,0x20,0x2f]
 
 //------------------------------------------------------------------------------
 // Unsigned integer lengthen (vector, second part)
 //------------------------------------------------------------------------------
 
         uxtl2 v0.8h, v1.16b
         uxtl2 v0.4s, v1.8h
         uxtl2 v0.2d, v1.4s
 
-// CHECK: ushll2 v0.8h, v1.16b, #0       // encoding: [0x20,0xa4,0x08,0x6f]
-// CHECK: ushll2 v0.4s, v1.8h, #0        // encoding: [0x20,0xa4,0x10,0x6f]
-// CHECK: ushll2 v0.2d, v1.4s, #0        // encoding: [0x20,0xa4,0x20,0x6f]
+// CHECK: uxtl2 v0.8h, v1.16b       // encoding: [0x20,0xa4,0x08,0x6f]
+// CHECK: uxtl2 v0.4s, v1.8h        // encoding: [0x20,0xa4,0x10,0x6f]
+// CHECK: uxtl2 v0.2d, v1.4s        // encoding: [0x20,0xa4,0x20,0x6f]