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[RISCV] Implement RV64D codegen

Authored by asb on Oct 12 2018, 6:42 PM.



Compared to RV64F, supporting RV64D is very straight-forward. This patch introduces the necessary instruction patterns.

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asb created this revision.Oct 12 2018, 6:42 PM
asb updated this revision to Diff 171083.Oct 25 2018, 6:45 AM

Rebase and improve testing for double<->int conversion.

asb updated this revision to Diff 174183.Nov 15 2018, 4:02 AM

Update to fix a typo in a comment and reflect changes in double-intrinsics.ll (which now exhaustively checks double intrinsics).

jrtc27 added a subscriber: jrtc27.Dec 7 2018, 8:42 AM
asb updated this revision to Diff 180082.Jan 3 2019, 8:17 AM

Refreshed patch.

Reviews would be much appreciated.

asb updated this revision to Diff 181464.Jan 12 2019, 11:35 PM
asb added a reviewer: efriedma.

Patch refresh, no changes. Ping?

efriedma accepted this revision.Jan 14 2019, 1:06 PM


211 ↗(On Diff #181464)

The seqz here shouldn't be necessary, I think. But that doesn't need to be fixed in this patch.

This revision is now accepted and ready to land.Jan 14 2019, 1:06 PM
asb updated this revision to Diff 182853.Jan 22 2019, 12:24 AM
asb edited the summary of this revision. (Show Details)

Rebased on the latest RV64F update. As @efriedma pointed out, fptosi/fptoui produce poison if the input won't fit in the target type. Just like the equivalent case in RV64F, fcvt.l[u].d can typically be used rather than fcvt.w[u].d because of this.

asb updated this revision to Diff 183621.Jan 25 2019, 2:23 PM

Patch refresh. No functional changes since last time. Just awaiting an LGTM on the dependent RV64F patch.

This revision was automatically updated to reflect the committed changes.
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