Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -58,6 +58,8 @@ "Enable Altivec instructions">; def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", "Enable SPE instructions">; +def FeatureSYNC : SubtargetFeature<"sync", "HasSYNC", "true", + "Enable the sync instruction">; def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", "Enable the MFOCRF instruction">; def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", @@ -193,50 +195,60 @@ // PowerPC processors supported. // -def : Processor<"generic", G3Itineraries, [Directive32]>; +def : Processor<"generic", G3Itineraries, [Directive32, FeatureSYNC]>; def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureBookE, DeprecatedMFTB]>; def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureBookE, DeprecatedMFTB]>; -def : Processor<"601", G3Itineraries, [Directive601]>; -def : Processor<"602", G3Itineraries, [Directive602]>; +def : Processor<"601", G3Itineraries, [Directive601, FeatureSYNC]>; +def : Processor<"602", G3Itineraries, [Directive602, FeatureSYNC]>; def : Processor<"603", G3Itineraries, [Directive603, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, FeatureSYNC]>; def : Processor<"603e", G3Itineraries, [Directive603, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, FeatureSYNC]>; def : Processor<"603ev", G3Itineraries, [Directive603, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"604", G3Itineraries, [Directive604, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"604e", G3Itineraries, [Directive604, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"620", G3Itineraries, [Directive620, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"750", G4Itineraries, [Directive750, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"g3", G3Itineraries, [Directive750, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, - FeatureFRES, FeatureFRSQRTE]>; + FeatureFRES, FeatureFRSQRTE, + FeatureSYNC]>; def : ProcessorModel<"970", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, - Feature64Bit /*, Feature64BitRegs */]>; + Feature64Bit /*, Feature64BitRegs */, FeatureSYNC]>; def : ProcessorModel<"g5", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureFRES, FeatureFRSQRTE, Feature64Bit /*, Feature64BitRegs */, - DeprecatedMFTB, DeprecatedDST]>; + DeprecatedMFTB, DeprecatedDST, FeatureSYNC]>; def : ProcessorModel<"e500mc", PPCE500mcModel, [DirectiveE500mc, FeatureMFOCRF, FeatureSTFIWX, FeatureBookE, FeatureISEL, @@ -251,35 +263,37 @@ FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, - FeaturePOPCNTD, FeatureLDBRX, Feature64Bit - /*, Feature64BitRegs */, DeprecatedMFTB]>; + FeaturePOPCNTD, FeatureLDBRX, Feature64Bit, + /* Feature64BitRegs, */ DeprecatedMFTB, FeatureSYNC]>; def : ProcessorModel<"a2q", PPCA2Model, [DirectiveA2, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, - FeaturePOPCNTD, FeatureLDBRX, Feature64Bit - /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>; + FeaturePOPCNTD, FeatureLDBRX, Feature64Bit, + FeatureSYNC, + /* Feature64BitRegs, */ FeatureQPX, DeprecatedMFTB]>; def : ProcessorModel<"pwr3", G5Model, [DirectivePwr3, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, - FeatureSTFIWX, Feature64Bit]>; + FeatureSTFIWX, Feature64Bit, FeatureSYNC]>; def : ProcessorModel<"pwr4", G5Model, [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, - FeatureSTFIWX, Feature64Bit]>; + FeatureSTFIWX, Feature64Bit, FeatureSYNC]>; def : ProcessorModel<"pwr5", G5Model, [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, - FeatureSTFIWX, Feature64Bit, + FeatureSTFIWX, Feature64Bit, FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr5x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, FeatureFPRND, Feature64Bit, + FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr6", G5Model, [DirectivePwr6, FeatureAltivec, @@ -287,13 +301,14 @@ FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, + FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr6x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, - FeatureFPRND, Feature64Bit, + FeatureFPRND, Feature64Bit, FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr7", P7Model, [DirectivePwr7, FeatureAltivec, @@ -303,6 +318,7 @@ FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, + FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */, [DirectivePwr8, FeatureAltivec, @@ -312,18 +328,19 @@ FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, + FeatureSYNC, DeprecatedMFTB, DeprecatedDST]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, - Feature64Bit /*, Feature64BitRegs */]>; + Feature64Bit /*, Feature64BitRegs */, FeatureSYNC]>; def : ProcessorModel<"ppc64le", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, - Feature64Bit /*, Feature64BitRegs */]>; + Feature64Bit /*, Feature64BitRegs */, FeatureSYNC]>; //===----------------------------------------------------------------------===// // Calling Conventions Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td +++ lib/Target/PowerPC/PPCInstrInfo.td @@ -665,6 +665,8 @@ def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">; def IsBookE : Predicate<"PPCSubTarget->isBookE()">; def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">; +def HasSYNC : Predicate<"PPCSubTarget->hasSYNC()">; +def HasNotSYNC : Predicate<"!PPCSubTarget->hasSYNC()">; def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">; def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">; def IsE500 : Predicate<"PPCSubTarget->isE500()">; @@ -1695,22 +1697,19 @@ "stmw $rS, $dst", IIC_LdStLMW, []>; def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), - "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>; + "sync $L", IIC_LdStSync, []>, Requires<[HasSYNC]>; let isCodeGenOnly = 1 in { def MSYNC : XForm_24_sync<31, 598, (outs), (ins), - "msync", IIC_LdStSync, []>, Requires<[IsBookE]> { + "msync", IIC_LdStSync, []>, Requires<[HasNotSYNC]> { let L = 0; } } -// FIXME: We should use a specific flag to check for the presence of the sync -// instruction instead of relying on IsBookE. -// For example, the PPC A2 supports SYNC despite being a BookE processor. -def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>; -def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[IsNotBookE]>; -def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>; -def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[IsBookE]>; +def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; +def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; +def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasNotSYNC]>; +def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasNotSYNC]>; //===----------------------------------------------------------------------===// // PPC32 Arithmetic Instructions. @@ -2550,8 +2549,8 @@ def : Pat<(f64 (fextend f32:$src)), (COPY_TO_REGCLASS $src, F8RC)>; -def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>; -def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>; +def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[HasSYNC]>; +def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasNotSYNC]>; // Additional FNMSUB patterns: -a*c + b == -(a*c - b) def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), @@ -3249,10 +3248,10 @@ def : InstAlias<"sc", (SC 0)>; -def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>; -def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>; -def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>; -def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>; +def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; +def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>; +def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; +def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; def : InstAlias<"wait", (WAIT 0)>; def : InstAlias<"waitrsv", (WAIT 1)>; Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -102,6 +102,7 @@ bool HasISEL; bool HasPOPCNTD; bool HasLDBRX; + bool HasSYNC; bool IsBookE; bool IsE500; bool IsPPC4xx; @@ -222,6 +223,7 @@ bool hasISEL() const { return HasISEL; } bool hasPOPCNTD() const { return HasPOPCNTD; } bool hasLDBRX() const { return HasLDBRX; } + bool hasSYNC() const { return HasSYNC; } bool isBookE() const { return IsBookE; } bool isPPC4xx() const { return IsPPC4xx; } bool isPPC6xx() const { return IsPPC6xx; } Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -109,6 +109,7 @@ HasISEL = false; HasPOPCNTD = false; HasLDBRX = false; + HasSYNC = false; IsBookE = false; IsPPC4xx = false; IsPPC6xx = false;