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[LV] Legalize SVML call instructions during vector code generation
Needs ReviewPublic

Authored by karthiksenthil on Oct 9 2018, 12:05 PM.

Details

Summary

This patch implements support to legalize SVML calls by
breaking down the illegal vector call instruction into multiple
legal vector call instructions during code generation.
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2018-June/124357.html)

Currently the vectorizer does not check legality of the
generated SVML (or any VECLIB) call instructions, and this
can lead to potential problems even during vector type
legalization. This patch addresses this issue by adding
a legality check during code generation and replaces the
illegal SVML call with corresponding legalized instructions.

For example, if the following SVML call is generated on AVX
target (256-bit vector register):

%1 = call <8 x double> @__svml_sin8(<8 x double> %0)

it is legalized and replaced with:

%shuffle = shufflevector <8 x double> %0, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%1 = call <4 x double> @__svml_sin4(<4 x double> %shuffle)
%shuffle9 = shufflevector <8 x double> %0, <8 x double> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%2 = call <4 x double> @__svml_sin4(<4 x double> %shuffle9)
%combined = shufflevector <4 x double> %1, <4 x double> %2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>

This patch also acts as an incentive to the VPlan framework
to model vector call instructions in a way that legalization
is done much before code generation in vectorizer.

Diff Detail

Event Timeline

karthiksenthil created this revision.Oct 9 2018, 12:05 PM

Hi all,

There has been a recent post on this RFC by Francesco here:
http://lists.llvm.org/pipermail/llvm-dev/2018-October/126830.html

Please consider the mechanisms described there along with this review.

Thanks,
Karthik

@karthiksenthil are there any plans to resurrect this diff, and rebase on latest?

@ayermolo I plan to rebase this diff to latest version of LV and update this review in the next few days.

Diff has been rebased to latest version of LV.

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ayermolo added inline comments.Sep 3 2020, 6:37 PM
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
4702

For my own education, how come there is a check for intrinsic? Won't something like log(..) be treated as intrinsic?

karthiksenthil added inline comments.Sep 17 2020, 5:13 PM
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
4702

This check is added to restrict the legalization feature to scalar math library calls that are translated to SVML calls upon vectorization. It does not work for standard C/C++ library intrinsics like llvm.sin.* or llvm.log*. Note that these intrinsics are also mapped to SVML variants in llvm/include/llvm/Analysis/VecFuncs.def. The relevant new LIT test in this patch that verifies this restriction is llvm/test/Transforms/LoopVectorize/X86/svml-legal-calls.ll.