Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1178,6 +1178,15 @@ if (Imm < -1 || Imm > 126) return Error(IDLoc, "immediate operand value out of range"); break; + case Mips::ADDIUR2_MM: + Opnd = Inst.getOperand(2); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (!(Imm == 1 || Imm == -1 || + ((Imm % 4 == 0) && Imm < 28 && Imm > 0))) + return Error(IDLoc, "immediate operand value out of range"); + break; } } Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -80,6 +80,10 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp // instruction immediate operand. unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -364,6 +364,20 @@ } unsigned MipsMCCodeEmitter:: +getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + int Value = MO.getImm(); + return Value >> 2; + } + + return 0; +} + +unsigned MipsMCCodeEmitter:: getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td @@ -81,6 +81,20 @@ let Inst{0} = funct; } +class ADDIUR2_FM_MM16 { + bits<3> rd; + bits<3> rs; + bits<3> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x1b; + let Inst{9-7} = rd; + let Inst{6-4} = rs; + let Inst{3-1} = imm; + let Inst{0} = 0; +} + class ADDIUS5_FM_MM16 { bits<5> rd; bits<4> imm; Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -19,6 +19,10 @@ let EncoderMethod = "getUImm3Mod8Encoding"; } +def simm3_lsa2 : Operand { + let EncoderMethod = "getSImm3Lsa2Value"; +} + def immZExt2Shift : ImmLeaf= 1 && Imm <= 8;}]>; def immLi16 : ImmLeaf= -1 && Imm <= 126;}]>; @@ -131,6 +135,13 @@ !strconcat(opstr, "\t$rd, $rt, $shamt"), [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], Itin, FrmR>; +class AddImmUR2 : + MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), + !strconcat(opstr, "\t$rd, $rs, $imm"), + [], NoItinerary, FrmR> { + let isCommutable = 1; +} + class AddImmUS5 : MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm), !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { @@ -245,6 +256,7 @@ immZExt2Shift, II_SLL>, SHIFT_FM_MM16<0>; def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, srl, immZExt2Shift, II_SRL>, SHIFT_FM_MM16<1>; +def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; Index: llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s +++ llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s @@ -19,6 +19,8 @@ # CHECK-EL: srl16 $4, $17, 6 # encoding: [0x1d,0x26] # CHECK-EL: li16 $3, -1 # encoding: [0xff,0xed] # CHECK-EL: li16 $3, 126 # encoding: [0xfe,0xed] +# CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f] +# CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f] # CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c] # CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f] # CHECK-EL: mfhi $9 # encoding: [0x09,0x46] @@ -45,6 +47,8 @@ # CHECK-EB: srl16 $4, $17, 6 # encoding: [0x26,0x1d] # CHECK-EB: li16 $3, -1 # encoding: [0xed,0xff] # CHECK-EB: li16 $3, 126 # encoding: [0xed,0xfe] +# CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] +# CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] # CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc] # CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9] # CHECK-EB: mfhi $9 # encoding: [0x46,0x09] @@ -69,6 +73,8 @@ srl16 $4, $17, 6 li16 $3, -1 li16 $3, 126 + addiur2 $6, $7, -1 + addiur2 $6, $7, 12 addius5 $7, -2 addiusp -16 mfhi $9 Index: llvm/trunk/test/MC/Mips/micromips-invalid.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips-invalid.s +++ llvm/trunk/test/MC/Mips/micromips-invalid.s @@ -15,3 +15,5 @@ srl16 $4, $5, 15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range li16 $8, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction li16 $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range