[Sparc] Give the option to use the OS reserved global registers

[dcederman]

Summary

The g5, g6, and g7 registers can be used as temporary registers in generic code if they are not reserved for a specific usage by the OS or system libraries. This can for example be the case when compiling for a bare metal system or when compiling the OS kernel. In GCC the corresponding option is called -fcall-used-g[5,6,7] and is used when compiling the Linux kernel.

The code is simplified by using markSuperRegs() that also reserves the corresponding covering register pairs when needed.

[jyknight]

I generally cringe at these sorts of register-use-changing-flags, but SPARC has basically explicitly defined all of G2-G7 as fixed-usage or scratch registers as the user/system desires. And these registers don't participate in the calling convention (not args or return values, and aren't saved)...so, it's not completely terrible. Only G7 is ever used for anything by the compiler, to implement TLS.

Some general comments:

1. G2-G4 should also be handled the same way, and the existing internal command-line-flag hack removed.
2. Should be careful of the usage of %g7 -- the TLS emission functions should error out when G7 is declared as a scratch register -- it doesn't make sense to try to use it as a thread register at the same time.
3. SparcAsmPrinter::EmitFunctionBodyStart should be updated to annotate usage of the registers appropriately.

lib/Target/Sparc/SparcSubtarget.h

46

I find this name unclear. I'd suggest having a set of fields named "ReserveRegG5" etc. (that is: with the opposite sense).

[dcederman]

Added attributes to prevent %g2-%g5 from being used as scratch register or to allow the use of %g5-%g7 as scratch registers. %g5 is reserved by default for 32-bit but not for 64-bit.

Renamed the field names to ReserveRegG*.

Added error messages if the TLS model or stack protector tries to use %g7 and it is not reserved.

EmitFunctionBodyStart now checks the list of actually reserved registers to output the correct register annotations.

[jyknight]

lib/Target/Sparc/Sparc.td

66

Having some use 'reserve', and some use 'use' seems unfortunate. If, instead, they're all spelled "reserve-reg-*", but the features for G5 (sometimes), G6, and G7 are enabled by default, I *think* it would then be possible to disable them with "target-features"="-reserve-reg-g5".

[dcederman]

lib/Target/Sparc/Sparc.td

66

Agreed. I did it like that to avoid having to add the features to each processor definition. But now I see on other targets that it is OK to extend the feature string in initializeSubtargetDependencies, so I'll take that approach.

[dcederman]

Removed the UseRegG* features and enabled the ReserveRegG6, ReserveRegG7, and ReserveRegG5 (on 32-bit) features by default.

[dcederman]

Any other comments @jyknight , or does it look ok?

lib/Target/Sparc/Sparc.td

: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
                      "Enable quad-word floating point instructions">;
 
 def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
                                "Use the popc (population count) instruction">;
 
 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
                               "Use software emulation for floating point">;
 
+def ReserveRegG2 : SubtargetFeature<"reserve-reg-g2", "ReserveRegG2", "true",
+                                    "Reserve use of register %g2">;
+
+def ReserveRegG3 : SubtargetFeature<"reserve-reg-g3", "ReserveRegG3", "true",
+                                    "Reserve use of register %g3">;
+
+def ReserveRegG4 : SubtargetFeature<"reserve-reg-g4", "ReserveRegG4", "true",
+                                    "Reserve use of register %g4">;
+
+def ReserveRegG5 : SubtargetFeature<"reserve-reg-g5", "ReserveRegG5", "true",
+                                    "Reserve use of register %g5">;
+
+def ReserveRegG6 : SubtargetFeature<"reserve-reg-g6", "ReserveRegG6", "true",
+                                    "Reserve use of register %g6">;
+
+def ReserveRegG7 : SubtargetFeature<"reserve-reg-g7", "ReserveRegG7", "true",
+                                    "Reserve use of register %g7">;
+
 //==== Features added predmoninantly for LEON subtarget support
 include "LeonFeatures.td"
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "SparcRegisterInfo.td"

lib/Target/Sparc/SparcAsmPrinter.cpp

void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI)
   } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
 }
 
 void SparcAsmPrinter::EmitFunctionBodyStart() {
   if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
     return;
 
   const MachineRegisterInfo &MRI = MF->getRegInfo();
+  const BitVector &Reserved = MRI.getReservedRegs();
   const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 };
   for (unsigned i = 0; globalRegs[i] != 0; ++i) {
     unsigned reg = globalRegs[i];
     if (MRI.use_empty(reg))
       continue;
 
-    if  (reg == SP::G6 || reg == SP::G7)
+    if (Reserved[reg])
       getTargetStreamer().emitSparcRegisterIgnore(reg);
     else
       getTargetStreamer().emitSparcRegisterScratch(reg);
   }
 }
 
 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
                                    raw_ostream &O) {

lib/Target/Sparc/SparcISelLowering.h

public:
 
     /// If a physical register, this returns the register that receives the
     /// exception typeid on entry to a landing pad.
     unsigned
     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
       return SP::I1;
     }
 
+    SDValue getThreadPointerRegister(SelectionDAG &DAG) const;
+
     /// Override to support customized stack guard loading.
     bool useLoadStackGuardNode() const override;
     void insertSSPDeclarations(Module &M) const override;
 
     /// getSetCCResultType - Return the ISD::SETCC ValueType
     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                            EVT VT) const override;
 

lib/Target/Sparc/SparcISelLowering.cpp

SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
   return makeAddress(Op, DAG);
 }
 
 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
                                                SelectionDAG &DAG) const {
   return makeAddress(Op, DAG);
 }
 
+SDValue SparcTargetLowering::getThreadPointerRegister(SelectionDAG &DAG) const {
+  const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
+  if (!TRI->getReservedRegs(DAG.getMachineFunction())[SP::G7])
+    report_fatal_error("The TLS model requires register %g7");
+
+  EVT PtrVT = getPointerTy(DAG.getDataLayout());
+  return DAG.getRegister(SP::G7, PtrVT);
+}
+
 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
                                                    SelectionDAG &DAG) const {
 
   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
   if (DAG.getTarget().useEmulatedTLS())
     return LowerToTLSEmulatedModel(GA, DAG);
 
   SDLoc DL(GA);
if (model == TLSModel::InitialExec) {
     SDValue TGA = makeHiLoPair(Op,
                                SparcMCExpr::VK_Sparc_TLS_IE_HI22,
                                SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
     SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
     SDValue Offset = DAG.getNode(SPISD::TLS_LD,
                                  DL, PtrVT, Ptr,
                                  withTargetFlags(Op, ldTF, DAG));
     return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
-                       DAG.getRegister(SP::G7, PtrVT), Offset,
+                       getThreadPointerRegister(DAG), Offset,
                        withTargetFlags(Op,
                                        SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
   }
 
   assert(model == TLSModel::LocalExec);
   SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
                   withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
   SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
                   withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
   SDValue Offset =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
 
   return DAG.getNode(ISD::ADD, DL, PtrVT,
-                     DAG.getRegister(SP::G7, PtrVT), Offset);
+                     getThreadPointerRegister(DAG), Offset);
 }
 
 SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
                                                   ArgListTy &Args, SDValue Arg,
                                                   const SDLoc &DL,
                                                   SelectionDAG &DAG) const {
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
   EVT ArgVT = Arg.getValueType();

 }
 
 SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
-  case Intrinsic::thread_pointer: {
-    EVT PtrVT = getPointerTy(DAG.getDataLayout());
-    return DAG.getRegister(SP::G7, PtrVT);
-  }
+  case Intrinsic::thread_pointer:
+    return getThreadPointerRegister(DAG);
   }
 }
 
 SDValue SparcTargetLowering::
 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 
   bool hasHardQuad = Subtarget->hasHardQuad();
   bool isV9        = Subtarget->isV9();

lib/Target/Sparc/SparcInstrInfo.cpp

unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
   return GlobalBaseReg;
 }
 
 bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case TargetOpcode::LOAD_STACK_GUARD: {
     assert(Subtarget.isTargetLinux() &&
            "Only Linux target is expected to contain LOAD_STACK_GUARD");
+    if (!Subtarget.reserveRegG7())
+      report_fatal_error("Stack protector requires register %g7");
     // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
     const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
     MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addReg(SP::G7)
         .addImm(Offset);
     return true;
   }
   }
   return false;
 }

lib/Target/Sparc/SparcRegisterInfo.cpp

 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
 #include "SparcGenRegisterInfo.inc"
 
-static cl::opt<bool>
-ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
-                    cl::desc("Reserve application registers (%g2-%g4)"));
-
 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
 
 const MCPhysReg*
 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   return CSR_SaveList;
 }
 
 const uint32_t *
 SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                         CallingConv::ID CC) const {
   return CSR_RegMask;
 }
 
 const uint32_t*
 SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
   return RTCSR_RegMask;
 }
 
 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
   // FIXME: G1 reserved for now for large imm generation by frame code.
-  Reserved.set(SP::G1);
+  markSuperRegs(Reserved, SP::G1);
 
-  // G1-G4 can be used in applications.
-  if (ReserveAppRegisters) {
-    Reserved.set(SP::G2);
-    Reserved.set(SP::G3);
-    Reserved.set(SP::G4);
-  }
-  // G5 is not reserved in 64 bit mode.
-  if (!Subtarget.is64Bit())
-    Reserved.set(SP::G5);
-
-  Reserved.set(SP::O6);
-  Reserved.set(SP::I6);
-  Reserved.set(SP::I7);
-  Reserved.set(SP::G0);
-  Reserved.set(SP::G6);
-  Reserved.set(SP::G7);
-
-  // Also reserve the register pair aliases covering the above
-  // registers, with the same conditions.
-  Reserved.set(SP::G0_G1);
-  if (ReserveAppRegisters)
-    Reserved.set(SP::G2_G3);
-  if (ReserveAppRegisters || !Subtarget.is64Bit())
-    Reserved.set(SP::G4_G5);
-
-  Reserved.set(SP::O6_O7);
-  Reserved.set(SP::I6_I7);
-  Reserved.set(SP::G6_G7);
+  if (Subtarget.reserveRegG2())
+    markSuperRegs(Reserved, SP::G2);
+  if (Subtarget.reserveRegG3())
+    markSuperRegs(Reserved, SP::G3);
+  if (Subtarget.reserveRegG4())
+    markSuperRegs(Reserved, SP::G4);
+  if (Subtarget.reserveRegG5())
+    markSuperRegs(Reserved, SP::G5);
+  if (Subtarget.reserveRegG6())
+    markSuperRegs(Reserved, SP::G6);
+  if (Subtarget.reserveRegG7())
+    markSuperRegs(Reserved, SP::G7);
+
+  markSuperRegs(Reserved, SP::O6);
+  markSuperRegs(Reserved, SP::I6);
+  markSuperRegs(Reserved, SP::I7);
+  markSuperRegs(Reserved, SP::G0);
 
   // Unaliased double registers are not available in non-V9 targets.
   if (!Subtarget.isV9()) {
     for (unsigned n = 0; n != 16; ++n) {
       for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
         Reserved.set(*AI);
     }
   }

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
   bool V8DeprecatedInsts;
   bool IsVIS, IsVIS2, IsVIS3;
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
   bool UseSoftFloat;
   bool HasNoFSMULD;
   bool HasNoFMULS;
+  bool ReserveRegG2;
+  bool ReserveRegG3;
+  bool ReserveRegG4;
+  bool ReserveRegG5;
+  bool ReserveRegG6;
+  bool ReserveRegG7;
 
   // LEON features
   bool HasUmacSmac;
   bool HasLeonCasa;
   bool HasPWRPSR;
   bool InsertNOPLoad;
   bool FixAllFDIVSQRT;
   bool DetectRoundChange;
public:
   bool isVIS2() const { return IsVIS2; }
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool hasNoFSMULD() const { return HasNoFSMULD; }
   bool hasNoFMULS() const { return HasNoFMULS; }
+  bool reserveRegG2() const { return ReserveRegG2; }
+  bool reserveRegG3() const { return ReserveRegG3; }
+  bool reserveRegG4() const { return ReserveRegG4; }
+  bool reserveRegG5() const { return ReserveRegG5; }
+  bool reserveRegG6() const { return ReserveRegG6; }
+  bool reserveRegG7() const { return ReserveRegG7; }
 
   // Leon options
   bool hasUmacSmac() const { return HasUmacSmac; }
   bool hasLeonCasa() const { return HasLeonCasa; }
   bool hasPWRPSR() const { return HasPWRPSR; }
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
   bool detectRoundChange() const { return DetectRoundChange; }

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   IsVIS2 = false;
   IsVIS3 = false;
   HasHardQuad = false;
   UsePopc = false;
   UseSoftFloat = false;
   HasNoFSMULD = false;
   HasNoFMULS = false;
 
+  ReserveRegG2 = false;
+  ReserveRegG3 = false;
+  ReserveRegG4 = false;
+  ReserveRegG5 = false;
+  ReserveRegG6 = false;
+  ReserveRegG7 = false;
+
   // Leon features
   HasLeonCasa = false;
   HasUmacSmac = false;
   HasPWRPSR = false;
   InsertNOPLoad = false;
   FixAllFDIVSQRT = false;
   DetectRoundChange = false;
   HasLeonCycleCounter = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
+  std::string FullFS = "+reserve-reg-g6,+reserve-reg-g7,";
+  if (!Is64Bit)
+    FullFS += "+reserve-reg-g5,";
+
+  FullFS += FS;
+
   // Parse features string.
-  ParseSubtargetFeatures(CPUName, FS);
+  ParseSubtargetFeatures(CPUName, FullFS);
 
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 

test/CodeGen/SPARC/64abi.ll

 ; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
 ; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
+; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc -mattr=use-reg-g6 | FileCheck %s --check-prefix=USEG6
 
 ; CHECK-LABEL: intarg:
 ; The save/restore frame is not strictly necessary here, but we would need to
 ; refer to %o registers instead.
 ; CHECK: save %sp, -128, %sp
 ; CHECK: ldx [%fp+2231], [[R2:%[gilo][0-7]]]
 ; CHECK: ld [%fp+2227], [[R1:%[gilo][0-7]]]
 ; CHECK: stb %i0, [%i4]

 }
 
 ; CHECK-LABEL: ret_nozext:
 ; CHECK-NOT: srl
 define signext i32 @ret_nozext(i32 signext %a0) {
   ret i32 %a0
 }
 
+@local_symbol = internal thread_local global i32 0
+
 ; CHECK-LABEL: test_register_directive:
 ; CHECK:       .register %g2, #scratch
 ; CHECK:       .register %g3, #scratch
-; CHECK:       add %i0, 2, %g2
-; CHECK:       add %i0, 3, %g3
+; CHECK:       .register %g7, #ignore
+; CHECK:       ld [%g7+%i0], %g3
+; CHECK:       add %g2, 3, %l1
+; USEG6-LABEL: test_register_directive:
+; USEG6:       .register %g6, #scratch
 define i32 @test_register_directive(i32 %i0) {
 entry:
   %0 = add nsw i32 %i0, 2
   %1 = add nsw i32 %i0, 3
-  tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7},~{g1},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1)
-  %2 = add nsw i32 %0, %1
-  ret i32 %2
+  %2 = add nsw i32 %i0, 4
+  %tls = load i32, i32* @local_symbol, align 4
+  tail call void asm sideeffect "", "r,r,~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7},~{g1},~{g4},~{g5},~{g7}"(i32 %0, i32 %1)
+  %3 = add nsw i32 %0, %1
+  %4 = add nsw i32 %3, %2
+  %5 = add nsw i32 %4, %tls
+  ret i32 %5
 }
 
 ; CHECK-LABEL: test_large_stack:
 
 ; CHECK:       sethi 16, %g1
 ; CHECK:       xor %g1, -176, %g1
 ; CHECK:       save %sp, %g1, %sp
 

test/CodeGen/SPARC/reserved-regs.ll

 ; RUN: llc -march=sparc -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -march=sparc -verify-machineinstrs -mattr=-reserve-reg-g5 < %s | FileCheck %s -check-prefix=USEG5
+; RUN: llc -march=sparc -verify-machineinstrs -mattr=-reserve-reg-g6 < %s | FileCheck %s -check-prefix=USEG6
+; RUN: not llc -march=sparc -verify-machineinstrs -mattr=-reserve-reg-g7 < %s 2>&1 | FileCheck %s -check-prefix=USEG7
+; RUN: llc -march=sparc -verify-machineinstrs -mattr=reserve-reg-g3 < %s | FileCheck %s -check-prefix=RESG3
 
 @g = common global [32 x i32] zeroinitializer, align 16
 @h = common global [16 x i64] zeroinitializer, align 16
 
 ;; Ensures that we don't use registers which are supposed to be reserved.
 
 ; CHECK-LABEL: use_all_i32_regs:
 ; CHECK: save %sp
 ; CHECK-NOT: %g0
 ; CHECK-NOT: %g1
 ; CHECK-NOT: %g5
 ; CHECK-NOT: %g6
 ; CHECK-NOT: %g7
 ; CHECK-NOT: %o6
 ; CHECK-NOT: %i6
 ; CHECK-NOT: %i7
+; USEG5: %g5
+; USEG6: %g6
+; USEG7: %g7
+; RESG3-NOT: %g3
 ; CHECK: ret
 define void @use_all_i32_regs() {
 entry:
   %0 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 0), align 16
   %1 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 1), align 4
   %2 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 2), align 8
   %3 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 3), align 4
   %4 = load volatile i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 4), align 16

 ; CHECK-NOT: %g4
 ; CHECK-NOT: %g5
 ; CHECK-NOT: %g6
 ; CHECK-NOT: %g7
 ; CHECK-NOT: %o6
 ; CHECK-NOT: %o7
 ; CHECK-NOT: %i6
 ; CHECK-NOT: %i7
+; USEG5: %g5
+; USEG6: %g6
+; USEG7: %g7
+; RESG3-NOT: %g3
 ; CHECK: ret
 define void @use_all_i64_regs() {
 entry:
   %0 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 0), align 16
   %1 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 1), align 4
   %2 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 2), align 8
   %3 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 3), align 4
   %4 = load volatile i64, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 4), align 16
entry:
   store volatile i64 %11, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 10), align 8
   store volatile i64 %12, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 11), align 4
   store volatile i64 %13, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 12), align 16
   store volatile i64 %14, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 13), align 4
   store volatile i64 %15, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 14), align 8
   store volatile i64 %0, i64* getelementptr inbounds ([16 x i64], [16 x i64]* @h, i64 0, i64 15), align 4
   ret void
 }
+
+@local_symbol = internal thread_local global i32 0
+
+; USEG7: LLVM ERROR: The TLS model requires register %g7
+define i32 @use_thread_pointer_register() {
+entry:
+  %0 = load i32, i32* @local_symbol, align 4
+  ret i32 %0
+}

test/CodeGen/SPARC/stack-protector.ll

 ; RUN: llc -mtriple=sparc-unknown-linux < %s | FileCheck %s --check-prefix=LINUX-32
 ; RUN: llc -mtriple=sparc64-unknown-linux < %s | FileCheck %s --check-prefix=LINUX-64
 ; RUN: llc -mtriple=sparc-unknown-solaris < %s | FileCheck %s --check-prefix=GENERIC
 ; RUN: llc -mtriple=sparc64-unknown-solaris < %s | FileCheck %s --check-prefix=GENERIC
+; RUN: not llc -mtriple=sparc-unknown-linux -mattr=-reserve-reg-g7 2>&1 < %s | FileCheck %s --check-prefix=LINUX-32-ERR
 
 ; LINUX-32: ld [%g7+20], [[REG1:%[ilo][0-9]*]]
 ; LINUX-64: ldx [%g7+40], [[REG1:%[ilo][0-9]*]]
 ; LINUX-32-NOT: __stack_chk_guard
 ; LINUX-64-NOT: __stack_chk_guard
 ; GENERIC: __stack_chk_guard
+; LINUX-32-ERR: Stack protector requires register %g7
 
 @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00"    ; <[11 x i8]*> [#uses=1]
 
 define void @test(i8* %a) nounwind ssp {
 entry:
   %a_addr = alloca i8*    ; <i8**> [#uses=2]
   %buf = alloca [8 x i8]    ; <[8 x i8]*> [#uses=2]
   %"alloca point" = bitcast i32 0 to i32    ; <i32> [#uses=0]