Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td @@ -117,6 +117,15 @@ let Defs = [RA]; } +// 16-bit Jump Reg +class JumpRegMM16 : + MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), + [], IIBranch, FrmR> { + let hasDelaySlot = 1; + let isBranch = 1; + let isIndirectBranch = 1; +} + // Base class for JRADDIUSP instruction. class JumpRAddiuStackMM16 : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm", @@ -173,6 +182,7 @@ def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>; def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>; def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>; +def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>; class WaitMM : InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [], Index: llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s =================================================================== --- llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s +++ llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s @@ -19,6 +19,8 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: jalrs16 $9 # encoding: [0xe9,0x45] # CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: jr16 $9 # encoding: [0x89,0x45] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -32,6 +34,8 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: jalrs16 $9 # encoding: [0x45,0xe9] # CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: jr16 $9 # encoding: [0x45,0x89] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] addius5 $7, -2 mfhi $9 @@ -41,3 +45,4 @@ jalr $9 jraddiusp 20 jalrs16 $9 + jr16 $9