Index: llvm/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86ISelLowering.cpp +++ llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39124,7 +39124,8 @@ if (C->getAPIntValue().isOneValue()) { SDValue Mask = Src.getOperand(0); if (Mask.getOpcode() == ISD::TRUNCATE && - Mask.getOperand(0).getValueType() != MVT::i16) + (Mask.getOperand(0).getValueType() == MVT::i8 || + Mask.getOperand(0).getValueType() == MVT::i32)) Mask = Mask.getOperand(0); return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask); } @@ -39138,11 +39139,11 @@ if (C->getAPIntValue().isOneValue()) { SDValue Mask = Src.getOperand(0).getOperand(0); if (Mask.getOpcode() == ISD::TRUNCATE && - Mask.getOperand(0).getValueType() != MVT::i16) + (Mask.getOperand(0).getValueType() == MVT::i8 || + Mask.getOperand(0).getValueType() == MVT::i32)) Mask = Mask.getOperand(0); - // Check if the initial value is an i16. scalar_to_vector fails to - // select for that type, so the combine should be aborted. - if (Mask.getValueType() == MVT::i16) + // Check if the initial value is of a legal type for scalar_to_vector. + if (Mask.getValueType() != MVT::i8 && Mask.getValueType() != MVT::i32) return SDValue(); return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), MVT::v1i1, Mask); } Index: llvm/test/CodeGen/X86/pr37879.ll =================================================================== --- llvm/test/CodeGen/X86/pr37879.ll +++ llvm/test/CodeGen/X86/pr37879.ll @@ -1,7 +1,15 @@ -; XFAIL: * +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -O3 < %s -mtriple=x86_64-apple-darwin -mattr=+avx512bw | FileCheck %s define double @foo(i32** nocapture readonly) #0 { +; CHECK-LABEL: foo: +; CHECK: ## %bb.0: +; CHECK-NEXT: movq (%rax), %rax +; CHECK-NEXT: vcvtsi2sdq %rax, %xmm0, %xmm1 +; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: kmovd %eax, %k1 +; CHECK-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1} +; CHECK-NEXT: retq %2 = load i64, i64* undef, align 8 %3 = and i64 %2, 1 %4 = icmp eq i64 %3, 0