Index: lib/Target/R600/SIISelLowering.h
===================================================================
--- lib/Target/R600/SIISelLowering.h
+++ lib/Target/R600/SIISelLowering.h
@@ -57,6 +57,7 @@
   static SDValue performUCharToFloatCombine(SDNode *N,
                                             DAGCombinerInfo &DCI);
 
+  const SIInstrInfo *getInstrInfo() const;
 public:
   SITargetLowering(TargetMachine &tm);
   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
Index: lib/Target/R600/SIISelLowering.cpp
===================================================================
--- lib/Target/R600/SIISelLowering.cpp
+++ lib/Target/R600/SIISelLowering.cpp
@@ -231,6 +231,11 @@
   setSchedulingPreference(Sched::RegPressure);
 }
 
+const SIInstrInfo *SITargetLowering::getInstrInfo() const {
+  auto STM = getTargetMachine().getSubtargetImpl();
+  return static_cast<const SIInstrInfo *>(STM->getInstrInfo());
+}
+
 //===----------------------------------------------------------------------===//
 // TargetLowering queries
 //===----------------------------------------------------------------------===//
@@ -299,8 +304,7 @@
 
 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                          Type *Ty) const {
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   return TII->isInlineConstant(Imm);
 }
 
@@ -492,8 +496,7 @@
     MachineInstr * MI, MachineBasicBlock * BB) const {
 
   MachineBasicBlock::iterator I = *MI;
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
 
   switch (MI->getOpcode()) {
@@ -581,8 +584,7 @@
   }
   case AMDGPU::FABS_SI: {
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
+    const SIInstrInfo *TII = getInstrInfo();
     DebugLoc DL = MI->getDebugLoc();
     unsigned DestReg = MI->getOperand(0).getReg();
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
@@ -599,8 +601,7 @@
   }
   case AMDGPU::FABS64_SI: {
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+    const SIInstrInfo *TII = getInstrInfo();
 
     DebugLoc DL = MI->getDebugLoc();
     unsigned SuperReg = MI->getOperand(0).getReg();
@@ -627,8 +628,7 @@
   }
   case AMDGPU::FNEG_SI: {
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
+    const SIInstrInfo *TII = getInstrInfo();
     DebugLoc DL = MI->getDebugLoc();
     unsigned DestReg = MI->getOperand(0).getReg();
     unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
@@ -644,8 +644,7 @@
   }
   case AMDGPU::FNEG64_SI: {
     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
+    const SIInstrInfo *TII = getInstrInfo();
 
     DebugLoc DL = MI->getDebugLoc();
     unsigned SrcReg = MI->getOperand(1).getReg();
@@ -670,8 +669,7 @@
     break;
   }
   case AMDGPU::FCLAMP_SI: {
-    const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-        getTargetMachine().getSubtargetImpl()->getInstrInfo());
+    const SIInstrInfo *TII = getInstrInfo();
     DebugLoc DL = MI->getDebugLoc();
     unsigned DestReg = MI->getOperand(0).getReg();
     BuildMI(*BB, I, DL, TII->get(AMDGPU::V_ADD_F32_e64), DestReg)
@@ -769,8 +767,7 @@
 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
 
   MachineFunction &MF = DAG.getMachineFunction();
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
   FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
   unsigned FrameIndex = FINode->getIndex();
@@ -1411,8 +1408,7 @@
                                bool &ScalarSlotUsed) const {
 
   MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
     return false;
 
@@ -1446,8 +1442,7 @@
 
 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
                                    SelectionDAG &DAG, const SDValue &Op) const {
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   const SIRegisterInfo &TRI = TII->getRegisterInfo();
 
   if (!Op->isMachineOpcode()) {
@@ -1566,8 +1561,7 @@
 
   // Original encoding (either e32 or e64)
   int Opcode = Node->getMachineOpcode();
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   const MCInstrDesc *Desc = &TII->get(Opcode);
 
   unsigned NumDefs = Desc->getNumDefs();
@@ -1822,8 +1816,7 @@
 /// \brief Fold the instructions after selecting them.
 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
                                           SelectionDAG &DAG) const {
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   Node = AdjustRegClass(Node, DAG);
 
   if (TII->isMIMG(Node->getMachineOpcode()))
@@ -1836,8 +1829,7 @@
 /// bits set in the writemask
 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
                                                      SDNode *Node) const {
-  const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
-      getTargetMachine().getSubtargetImpl()->getInstrInfo());
+  const SIInstrInfo *TII = getInstrInfo();
   if (!TII->isMIMG(MI->getOpcode()))
     return;