Index: lib/Target/R600/SIInstrInfo.h
===================================================================
--- lib/Target/R600/SIInstrInfo.h
+++ lib/Target/R600/SIInstrInfo.h
@@ -62,6 +62,11 @@
     return RI;
   }
 
+  bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
+                            unsigned &BaseReg, unsigned &Offset,
+                            const TargetRegisterInfo *TRI) const override;
+
+
   void copyPhysReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator MI, DebugLoc DL,
                    unsigned DestReg, unsigned SrcReg,
Index: lib/Target/R600/SIInstrInfo.cpp
===================================================================
--- lib/Target/R600/SIInstrInfo.cpp
+++ lib/Target/R600/SIInstrInfo.cpp
@@ -32,6 +32,38 @@
 // TargetInstrInfo callbacks
 //===----------------------------------------------------------------------===//
 
+bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
+                                       unsigned &BaseReg, unsigned &Offset,
+                                       const TargetRegisterInfo *TRI) const {
+  // TODO: Other address spaces.
+  unsigned Opc = LdSt->getOpcode();
+  if (isDS(Opc)) {
+    switch (Opc) {
+    case AMDGPU::DS_READ_B32:
+    case AMDGPU::DS_READ_B64:
+    case AMDGPU::DS_READ_I16:
+    case AMDGPU::DS_READ_U16:
+    case AMDGPU::DS_READ_I8:
+    case AMDGPU::DS_READ_U8:
+      BaseReg = LdSt->getOperand(2).getReg(); // addr
+      Offset = LdSt->getOperand(3).getImm(); // offset
+      return true;
+    case AMDGPU::DS_WRITE_B32:
+    case AMDGPU::DS_WRITE_B64:
+    case AMDGPU::DS_WRITE_B16:
+    case AMDGPU::DS_WRITE_B8:
+      BaseReg = LdSt->getOperand(1).getReg(); // addr
+      Offset = LdSt->getOperand(3).getImm(); // offset
+      return true;
+    default:
+      // Skip read2 / write2 and atomics.
+      return false;
+    }
+  }
+
+  return false;
+}
+
 void
 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MI, DebugLoc DL,