[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.

[gberry]

Summary

When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.

[mcrosier]

LGTM. Thanks, Geoff. It would be nice to get this into the 6.0.1 release, if at all possible.

llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/DebugCounter.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <iterator>
 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "falkor-hwpf-fix"
 
 STATISTIC(NumStridedLoadsMarked, "Number of strided loads marked");
 STATISTIC(NumCollisionsAvoided,
           "Number of HW prefetch tag collisions avoided");
 STATISTIC(NumCollisionsNotAvoided,
           "Number of HW prefetch tag collisions not avoided due to lack of registers");
+DEBUG_COUNTER(FixCounter, "falkor-hwpf",
+              "Controls which tag collisions are avoided");
 
 namespace {
 
 class FalkorMarkStridedAccesses {
 public:
   FalkorMarkStridedAccesses(LoopInfo &LI, ScalarEvolution &SE)
       : LI(LI), SE(SE) {}
 
for (auto I = MBB->rbegin(); I != MBB->rend(); LR.stepBackward(*I), ++I) {
         continue;
       auto &OldCollisions = TagMap[*OptOldTag];
       if (OldCollisions.size() <= 1)
         continue;
 
       bool Fixed = false;
       DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);
 
+      if (!DebugCounter::shouldExecute(FixCounter)) {
+        DEBUG(dbgs() << "Skipping fix due to debug counter:\n  " << MI);
+        continue;
+      }
+
+      // Add the non-base registers of MI as live so we don't use them as
+      // scratch registers.
+      for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {
+        if (OpI == static_cast<unsigned>(LdI.BaseRegIdx))
+          continue;
+        MachineOperand &MO = MI.getOperand(OpI);
+        if (MO.isReg() && MO.readsReg())
+          LR.addReg(MO.getReg());
+      }
+
       for (unsigned ScratchReg : AArch64::GPR64RegClass) {
         if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
           continue;
 
         LoadInfo NewLdI(LdI);
         NewLdI.BaseReg = ScratchReg;
         unsigned NewTag = *getTag(TRI, MI, NewLdI);
         // Scratch reg tag would collide too, so don't use it.

llvm/trunk/test/CodeGen/AArch64/falkor-hwpf-fix.mir

bb.0:
 
     $w0 = SUBWri $w0, 1, 0
     $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
     Bcc 9, %bb.0, implicit $nzcv
 
   bb.1:
     RET_ReallyLR
 ...
+---
+# Check that non-base registers are considered live when finding a
+# scratch register by making sure we don't use $x2 for the scratch
+# register for the inserted ORRXrs.
+# CHECK-LABEL: name: hwpf_offreg
+# CHECK: $x3 = ORRXrs $xzr, $x1, 0
+# CHECK: $w10 = LDRWroX $x3, $x2, 0, 0
+name:            hwpf_offreg
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $w0, $x1, $x2, $x17, $x18
+
+    $w10 = LDRWroX $x1, $x2, 0, 0 :: ("aarch64-strided-access" load 4)
+
+    $x2 = ORRXrs $xzr, $x10, 0
+    $w26 = LDRWroX $x1, $x2, 0, 0
+
+    $w0 = SUBWri $w0, 1, 0
+    $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
+    Bcc 9, %bb.0, implicit $nzcv
+
+  bb.1:
+    RET_ReallyLR
+...