[X86] Limit Store Forwarding Block only to cases where we can prove that the memcpy does not overlap

[lsaba]

Summary

Limit Store Forwarding Block only to cases where we can prove that the memcpy does not overlap in memory, otherwise breaking the memcpy could result in overwriting the correct value.
This limits the optimization only to cases where AA can prove that the memory locations don't alias.

[lsaba]

@chandlerc there's a good chance this solves the miscompilations you are seeing

[craig.topper]

lib/Target/X86/X86FixupSFB.cpp

465

Fix indentation of second parameter

503

Blank line between functions.

[niravd]

lib/Target/X86/X86FixupSFB.cpp

460

It looks like you're only using this to compare two operands so there's no reason to expose the internal reg/index value.

Pull the comparison into this function, e.g:

equalBaseOperands(MachineOperand &B1, MachineOperand &B2) {

if (B1.isReg() != B2.isReg()) return false;
if (B1.isReg())
    return B1.getReg() == B2.getReg();
return B1.getIndex() == B2.getIndex();

}

491

nit: The getParent check should probably be first.

495

Can MI/StoreMI have more than one memoperand? We should add an assert for a singleton list or check the crossproduct.

[lsaba]

Fixed comments in review https://reviews.llvm.org/D41330

[zvi]

lib/Target/X86/X86FixupSFB.cpp

64

Can you please commit the class rename change and rebase this patch on top?

460

Can this be committed and then rebase the patch on top?

lib/Target/X86/X86TargetMachine.cpp

65

Can you please commit the initialize-related changes and rebase?

test/CodeGen/X86/fixup-sfb.ll

7

Why were these cases removed?

[lsaba]

@zvi the changes in this commit were added to https://reviews.llvm.org/D41330 and committed already. I will close this patch

lib/Target/X86/X86FixupSFB.cpp

 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCInstrDesc.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "x86-fixup-SFB"
 
+namespace llvm {
+void initializeX86FixupSFBPassPass(PassRegistry &);
+} // end namespace llvm
+
 static cl::opt<bool> DisableX86FixupSFB("disable-fixup-SFB", cl::Hidden,
                                         cl::desc("X86: Disable SFB fixup."),
                                         cl::init(false));
 namespace {
 
-class FixupSFBPass : public MachineFunctionPass {
+class X86FixupSFBPass : public MachineFunctionPass {
 public:
-  FixupSFBPass() : MachineFunctionPass(ID) {}
+  static char ID;
+  X86FixupSFBPass() : MachineFunctionPass(ID) {
+    initializeX86FixupSFBPassPass(*PassRegistry::getPassRegistry());
+  }
 
   StringRef getPassName() const override {
     return "X86 Fixup Store Forward Block";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    MachineFunctionPass::getAnalysisUsage(AU);
+    AU.addRequired<AAResultsWrapperPass>();
+  }
+
 private:
   MachineRegisterInfo *MRI;
   const X86InstrInfo *TII;
   const X86RegisterInfo *TRI;
   SmallVector<std::pair<MachineInstr *, MachineInstr *>, 2> BlockedLoadsStores;
   SmallVector<MachineInstr *, 2> ForRemoval;
   bool Is64Bit;
+  AliasAnalysis *AA;
 
   /// \brief Returns couples of Load then Store to memory which look
   ///  like a memcpy.
   void findPotentiallylBlockedCopies(MachineFunction &MF);
   /// \brief Break the memcpy's load and store into smaller copies
   /// such that each memory load that was blocked by a smaller store
   /// would now be copied separately.
   void
   breakBlockedCopies(MachineInstr *LoadInst, MachineInstr *StoreInst,
                      const std::map<int64_t, unsigned> &BlockingStoresDisp);
   /// \brief Break a copy of size Size to smaller copies.
   void buildCopies(int Size, MachineInstr *LoadInst, int64_t LdDispImm,
                    MachineInstr *StoreInst, int64_t StDispImm,
                    int64_t LMMOffset, int64_t SMMOffset);
 
   void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
                  MachineInstr *StoreInst, unsigned NStoreOpcode,
                  int64_t StoreDisp, unsigned Size, int64_t LMMOffset,
                  int64_t SMMOffset);
 
+  bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
+
   unsigned getRegSizeInBytes(MachineInstr *Inst);
-  static char ID;
 };
 
 } // end anonymous namespace
 
-char FixupSFBPass::ID = 0;
+char X86FixupSFBPass::ID = 0;
+
+INITIALIZE_PASS_BEGIN(X86FixupSFBPass, DEBUG_TYPE, "Machine code sinking", false,
+                      false)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(X86FixupSFBPass, DEBUG_TYPE, "Machine code sinking", false,
+                    false)
 
-FunctionPass *llvm::createX86FixupSFB() { return new FixupSFBPass(); }
+FunctionPass *llvm::createX86FixupSFB() { return new X86FixupSFBPass(); }
 
 static bool isXMMLoadOpcode(unsigned Opcode) {
   return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm ||
          Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm ||
          Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm ||
          Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm ||
          Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm ||
          Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm ||
for (MachineBasicBlock::pred_iterator PB = MBB->pred_begin(),
           break;
         PotentialBlockers.push_back(&*PMI);
       }
     }
   }
   return PotentialBlockers;
 }
 
-void FixupSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
+void X86FixupSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
                              int64_t LoadDisp, MachineInstr *StoreInst,
                              unsigned NStoreOpcode, int64_t StoreDisp,
                              unsigned Size, int64_t LMMOffset,
                              int64_t SMMOffset) {
   MachineOperand &LoadBase = getBaseOperand(LoadInst);
   MachineOperand &StoreBase = getBaseOperand(StoreInst);
   MachineBasicBlock *MBB = LoadInst->getParent();
   MachineMemOperand *LMMO = *LoadInst->memoperands_begin();
BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
       .addImm(StoreDisp)
       .addReg(X86::NoRegister)
       .addReg(Reg1)
       .addMemOperand(
           MBB->getParent()->getMachineMemOperand(SMMO, SMMOffset, Size));
   DEBUG(StInst->getPrevNode()->dump());
 }
 
-void FixupSFBPass::buildCopies(int Size, MachineInstr *LoadInst,
+void X86FixupSFBPass::buildCopies(int Size, MachineInstr *LoadInst,
                                int64_t LdDispImm, MachineInstr *StoreInst,
                                int64_t StDispImm, int64_t LMMOffset,
                                int64_t SMMOffset) {
   int LdDisp = LdDispImm;
   int StDisp = StDispImm;
   while (Size > 0) {
     if ((Size - MOV128SZ >= 0) && isYMMLoadOpcode(LoadInst->getOpcode())) {
       Size = Size - MOV128SZ;
static void updateKillStatus(MachineInstr *LoadInst, MachineInstr *StoreInst) {
   if (StoreBase.isReg()) {
     MachineInstr *StInst = StoreInst;
     if (StoreInst->getPrevNode() == LoadInst)
       StInst = LoadInst;
     getBaseOperand(StInst->getPrevNode()).setIsKill(StoreBase.isKill());
   }
 }
 
-void FixupSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) {
+static int getBaseOperandValue(MachineOperand &BaseOperand) {
+  return BaseOperand.isReg() ? BaseOperand.getReg() : BaseOperand.getIndex();
+}
+
+bool X86FixupSFBPass::alias(const MachineMemOperand &Op1,
+                         const MachineMemOperand &Op2) const {
+  if (!Op1.getValue() || !Op2.getValue())
+    return true;
+
+  int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
+  int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset;
+  int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
+
+  AliasResult AAResult =
+      AA->alias(MemoryLocation(Op1.getValue(), Overlapa, Op1.getAAInfo()),
+                MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo()));
+  return AAResult != NoAlias;
+}
+
+void X86FixupSFBPass::findPotentiallylBlockedCopies(MachineFunction &MF) {
   for (auto &MBB : MF)
     for (auto &MI : MBB)
       if (isPotentialBlockedMemCpyLd(MI.getOpcode())) {
         int DefVR = MI.getOperand(0).getReg();
         if (MRI->hasOneUse(DefVR))
           for (auto UI = MRI->use_nodbg_begin(DefVR), UE = MRI->use_nodbg_end();
                UI != UE;) {
             MachineOperand &StoreMO = *UI++;
             MachineInstr &StoreMI = *StoreMO.getParent();
             if (isPotentialBlockedMemCpyPair(MI.getOpcode(),
                                              StoreMI.getOpcode()) &&
                 (StoreMI.getParent() == MI.getParent()))
+              // Skip cases where the memcpy may overlap.
               if (isRelevantAddressingMode(&MI) &&
-                  isRelevantAddressingMode(&StoreMI))
+                  isRelevantAddressingMode(&StoreMI) &&
+                  !alias(**MI.memoperands_begin(),
+                         **StoreMI.memoperands_begin())) {
                 BlockedLoadsStores.push_back(
                     std::pair<MachineInstr *, MachineInstr *>(&MI, &StoreMI));
               }
           }
       }
-unsigned FixupSFBPass::getRegSizeInBytes(MachineInstr *LoadInst) {
+}
+unsigned X86FixupSFBPass::getRegSizeInBytes(MachineInstr *LoadInst) {
   auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
                               *LoadInst->getParent()->getParent());
   return TRI->getRegSizeInBits(*TRC) / 8;
 }
 
-void FixupSFBPass::breakBlockedCopies(
+void X86FixupSFBPass::breakBlockedCopies(
     MachineInstr *LoadInst, MachineInstr *StoreInst,
     const std::map<int64_t, unsigned> &BlockingStoresDisp) {
   int64_t LdDispImm = getDispOperand(LoadInst).getImm();
   int64_t StDispImm = getDispOperand(StoreInst).getImm();
   int64_t LMMOffset = (*LoadInst->memoperands_begin())->getOffset();
   int64_t SMMOffset = (*StoreInst->memoperands_begin())->getOffset();
 
   int64_t LdDisp1 = LdDispImm;
for (auto inst : BlockingStoresDisp) {
     LMMOffset += Size1 + Size2;
     SMMOffset += Size1 + Size2;
   }
   unsigned Size3 = (LdDispImm + getRegSizeInBytes(LoadInst)) - LdDisp1;
   buildCopies(Size3, LoadInst, LdDisp1, StoreInst, StDisp1, LMMOffset,
               LMMOffset);
 }
 
-bool FixupSFBPass::runOnMachineFunction(MachineFunction &MF) {
+bool X86FixupSFBPass::runOnMachineFunction(MachineFunction &MF) {
   bool Changed = false;
 
   if (DisableX86FixupSFB || skipFunction(MF.getFunction()))
     return false;
 
   MRI = &MF.getRegInfo();
   assert(MRI->isSSA() && "Expected MIR to be in SSA form");
   TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
   TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
   Is64Bit = MF.getSubtarget<X86Subtarget>().is64Bit();
+  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
   DEBUG(dbgs() << "Start X86FixupSFB\n";);
   // Look for a load then a store to XMM/YMM which look like a memcpy
   findPotentiallylBlockedCopies(MF);
 
   for (auto LoadStoreInst : BlockedLoadsStores) {
     MachineInstr *LoadInst = LoadStoreInst.first;
     SmallVector<MachineInstr *, 2> PotentialBlockers =
         findPotentialBlockers(LoadInst);
 
     MachineOperand &LoadBase = getBaseOperand(LoadInst);
     int64_t LdDispImm = getDispOperand(LoadInst).getImm();
     std::map<int64_t, unsigned> BlockingStoresDisp;
-    int LdBaseReg = LoadBase.isReg() ? LoadBase.getReg() : LoadBase.getIndex();
+    int LdBase = getBaseOperandValue(LoadBase);
 
     for (auto PBInst : PotentialBlockers) {
       if (isPotentialBlockingStoreInst(PBInst->getOpcode(),
                                        LoadInst->getOpcode())) {
         if (!isRelevantAddressingMode(PBInst))
           continue;
         MachineOperand &PBstoreBase = getBaseOperand(PBInst);
         int64_t PBstDispImm = getDispOperand(PBInst).getImm();
         assert(PBInst->hasOneMemOperand() && "Expected One Memory Operand");
         unsigned PBstSize = (*PBInst->memoperands_begin())->getSize();
-        int PBstBaseReg =
-            PBstoreBase.isReg() ? PBstoreBase.getReg() : PBstoreBase.getIndex();
+        int PBstBase = getBaseOperandValue(PBstoreBase);
         // This check doesn't cover all cases, but it will suffice for now.
         // TODO: take branch probability into consideration, if the blocking
         // store is in an unreached block, breaking the memcopy could lose
         // performance.
         if (((LoadBase.isReg() && PBstoreBase.isReg()) ||
              (LoadBase.isFI() && PBstoreBase.isFI())) &&
-            LdBaseReg == PBstBaseReg &&
+            LdBase == PBstBase &&
             ((PBstDispImm >= LdDispImm) &&
              (PBstDispImm <=
               LdDispImm + (getRegSizeInBytes(LoadInst) - PBstSize)))) {
           if (BlockingStoresDisp.count(PBstDispImm)) {
             if (BlockingStoresDisp[PBstDispImm] > PBstSize)
               BlockingStoresDisp[PBstDispImm] = PBstSize;
 
           } else

lib/Target/X86/X86TargetMachine.cpp

 namespace llvm {
 
 void initializeWinEHStatePassPass(PassRegistry &);
 void initializeFixupLEAPassPass(PassRegistry &);
 void initializeX86CallFrameOptimizationPass(PassRegistry &);
 void initializeX86CmovConverterPassPass(PassRegistry &);
 void initializeX86ExecutionDomainFixPass(PassRegistry &);
 void initializeX86DomainReassignmentPass(PassRegistry &);
+void initializeX86FixupSFBPassPass(PassRegistry &);
 
 } // end namespace llvm
 
 extern "C" void LLVMInitializeX86Target() {
   // Register the target.
   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializeGlobalISel(PR);
   initializeWinEHStatePassPass(PR);
   initializeFixupBWInstPassPass(PR);
   initializeEvexToVexInstPassPass(PR);
   initializeFixupLEAPassPass(PR);
   initializeX86CallFrameOptimizationPass(PR);
   initializeX86CmovConverterPassPass(PR);
   initializeX86ExecutionDomainFixPass(PR);
   initializeX86DomainReassignmentPass(PR);
+  initializeX86FixupSFBPassPass(PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO()) {
     if (TT.getArch() == Triple::x86_64)
       return llvm::make_unique<X86_64MachoTargetObjectFile>();
     return llvm::make_unique<TargetLoweringObjectFileMachO>();
   }

test/CodeGen/X86/fixup-sfb-32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefix=CHECK
 ; RUN: llc < %s -mtriple=i686-linux --disable-fixup-SFB | FileCheck %s --check-prefix=DISABLED
 ; RUN: llc < %s -mtriple=i686-linux -mattr +sse4.1 | FileCheck %s -check-prefix=CHECK-AVX2
 ; RUN: llc < %s -mtriple=i686-linux -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq | FileCheck %s -check-prefix=CHECK-AVX512
 
 %struct.S = type { i32, i32, i32, i32 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_conditional_block(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    .cfi_offset %esi, -12
 ; CHECK-NEXT:    .cfi_offset %edi, -8
if.end:                                           ; preds = %if.then, %entry
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_imm_store(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3) local_unnamed_addr #0 {
+define void @test_imm_store(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_imm_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; CHECK-NEXT:    movl $0, (%edx)
 ; CHECK-NEXT:    movl $1, (%ecx)
 ; CHECK-NEXT:    movl (%edx), %ecx
entry:
   store i32 1, i32* %a1, align 4
   %0 = bitcast %struct.S* %s2 to i8*
   %1 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_nondirect_br(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_nondirect_br(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_nondirect_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    .cfi_offset %esi, -12
 ; CHECK-NEXT:    .cfi_offset %edi, -8
if.end3:                                          ; preds = %if.then2, %if.end
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_2preds_block(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_2preds_block(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_2preds_block:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
if.end:                                           ; preds = %if.then, %entry
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 %struct.S2 = type { i64, i64 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_type64(%struct.S2* nocapture %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_type64(%struct.S2* nocapture noalias %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_type64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    .cfi_offset %esi, -12
 ; CHECK-NEXT:    .cfi_offset %edi, -8
if.end:                                           ; preds = %if.then, %entry
   %2 = bitcast %struct.S2* %s2 to i8*
   %3 = bitcast %struct.S2* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 8, i1 false)
   ret void
 }
 %struct.S3 = type { i64, i8, i8, i16, i32 }
 
 ; Function Attrs: noinline nounwind uwtable
-define void @test_mixed_type(%struct.S3* nocapture %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 {
+define void @test_mixed_type(%struct.S3* nocapture noalias %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_mixed_type:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
if.end:                                           ; preds = %if.then, %entry
   %0 = bitcast %struct.S3* %s2 to i8*
   %1 = bitcast %struct.S3* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 8, i1 false)
   ret void
 }
 %struct.S4 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_multiple_blocks(%struct.S4* nocapture %s1, %struct.S4* nocapture %s2) local_unnamed_addr #0 {
+define void @test_multiple_blocks(%struct.S4* nocapture noalias %s1, %struct.S4* nocapture %s2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_multiple_blocks:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl $0, 4(%ecx)
 ; CHECK-NEXT:    movl $0, 36(%ecx)
 ; CHECK-NEXT:    movups 16(%ecx), %xmm0
 ; CHECK-NEXT:    movups %xmm0, 16(%eax)
entry:
   %0 = bitcast %struct.S4* %s2 to i8*
   %1 = bitcast %struct.S4* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 48, i32 4, i1 false)
   ret void
 }
 %struct.S5 = type { i16, i16, i16, i16, i16, i16, i16, i16 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_type16(%struct.S5* nocapture %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_type16(%struct.S5* nocapture noalias %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_type16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    .cfi_offset %esi, -12
 ; CHECK-NEXT:    .cfi_offset %edi, -8

 }
 
 %struct.S6 = type { [4 x i32], i32, i32, i32, i32 }
 
 ; Function Attrs: nounwind uwtable
 define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval nocapture readnone align 8 %s1, %struct.S6* byval nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_stack:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %edi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
 ; CHECK-NEXT:    movups %xmm0, (%eax)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl %ecx, 16(%eax)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl %ecx, 20(%eax)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl %ecx, 24(%eax)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl %ecx, 28(%eax)
-; CHECK-NEXT:    popl %ecx
+; CHECK-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; CHECK-NEXT:    movups %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    addl $4, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %edi
 ; CHECK-NEXT:    retl $4
 ;
 ; DISABLED-LABEL: test_stack:
 ; DISABLED:       # %bb.0: # %entry
 ; DISABLED-NEXT:    pushl %eax
 ; DISABLED-NEXT:    .cfi_def_cfa_offset 8
 ; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; DISABLED-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; DISABLED-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; DISABLED-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
 ; DISABLED-NEXT:    movups %xmm0, (%eax)
 ; DISABLED-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
 ; DISABLED-NEXT:    movups %xmm0, 16(%eax)
+; DISABLED-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
+; DISABLED-NEXT:    movups {{[0-9]+}}(%esp), %xmm1
+; DISABLED-NEXT:    movups %xmm0, {{[0-9]+}}(%esp)
+; DISABLED-NEXT:    movups %xmm1, {{[0-9]+}}(%esp)
 ; DISABLED-NEXT:    popl %ecx
 ; DISABLED-NEXT:    retl $4
 ;
 ; CHECK-AVX2-LABEL: test_stack:
 ; CHECK-AVX2:       # %bb.0: # %entry
-; CHECK-AVX2-NEXT:    pushl %eax
+; CHECK-AVX2-NEXT:    pushl %edi
 ; CHECK-AVX2-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-AVX2-NEXT:    pushl %esi
+; CHECK-AVX2-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-AVX2-NEXT:    pushl %eax
+; CHECK-AVX2-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-AVX2-NEXT:    .cfi_offset %esi, -12
+; CHECK-AVX2-NEXT:    .cfi_offset %edi, -8
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-AVX2-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-AVX2-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
 ; CHECK-AVX2-NEXT:    movups %xmm0, (%eax)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX2-NEXT:    movl %ecx, 16(%eax)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX2-NEXT:    movl %ecx, 20(%eax)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX2-NEXT:    movl %ecx, 24(%eax)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX2-NEXT:    movl %ecx, 28(%eax)
-; CHECK-AVX2-NEXT:    popl %ecx
+; CHECK-AVX2-NEXT:    movups {{[0-9]+}}(%esp), %xmm0
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; CHECK-AVX2-NEXT:    movups %xmm0, {{[0-9]+}}(%esp)
+; CHECK-AVX2-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-AVX2-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; CHECK-AVX2-NEXT:    movl %esi, {{[0-9]+}}(%esp)
+; CHECK-AVX2-NEXT:    movl %edi, {{[0-9]+}}(%esp)
+; CHECK-AVX2-NEXT:    addl $4, %esp
+; CHECK-AVX2-NEXT:    popl %esi
+; CHECK-AVX2-NEXT:    popl %edi
 ; CHECK-AVX2-NEXT:    retl $4
 ;
 ; CHECK-AVX512-LABEL: test_stack:
 ; CHECK-AVX512:       # %bb.0: # %entry
 ; CHECK-AVX512-NEXT:    pushl %eax
 ; CHECK-AVX512-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-AVX512-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX512-NEXT:    movl %ecx, 16(%eax)
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX512-NEXT:    movl %ecx, 20(%eax)
-; CHECK-AVX512-NEXT:    vmovups {{[0-9]+}}(%esp), %xmm0
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX512-NEXT:    movl %ecx, 24(%eax)
-; CHECK-AVX512-NEXT:    vmovups %xmm0, (%eax)
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-AVX512-NEXT:    movl %ecx, 28(%eax)
+; CHECK-AVX512-NEXT:    vmovups {{[0-9]+}}(%esp), %xmm0
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-AVX512-NEXT:    vmovups %xmm0, (%eax)
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-AVX512-NEXT:    vmovups {{[0-9]+}}(%esp), %xmm0
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
+; CHECK-AVX512-NEXT:    vmovups %xmm0, {{[0-9]+}}(%esp)
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; CHECK-AVX512-NEXT:    popl %ecx
 ; CHECK-AVX512-NEXT:    retl $4
 entry:
   %s6.sroa.0.0..sroa_cast1 = bitcast %struct.S6* %s2 to i8*
   %s6.sroa.3.0..sroa_idx4 = getelementptr inbounds %struct.S6, %struct.S6* %s2, i64 0, i32 3
   store i32 %x, i32* %s6.sroa.3.0..sroa_idx4, align 8
   %0 = bitcast %struct.S6* %agg.result to i8*
+  %s6.sroa.0.0..sroa_cast2 = bitcast %struct.S6* %s1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* nonnull %s6.sroa.0.0..sroa_cast1, i64 32, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %s6.sroa.0.0..sroa_cast2, i8* nonnull %s6.sroa.0.0..sroa_cast1, i64 32, i32 4, i1 false)
+
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_limit_all(%struct.S* %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_limit_all(%struct.S* noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_limit_all:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
if.end:                                           ; preds = %if.then, %entry
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_limit_one_pred(%struct.S* %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_limit_one_pred:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16

 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
 
 attributes #0 = { nounwind uwtable "target-cpu"="x86-64" }
 
 %struct.S7 = type { float, float, float , float, float, float, float, float }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block_float(%struct.S7* nocapture %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 {
+define void @test_conditional_block_float(%struct.S7* nocapture noalias %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
if.end:                                           ; preds = %if.then, %entry
   %3 = bitcast %struct.S7* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 32, i32 4, i1 false)
   ret void
 }
 
 %struct.S8 = type { i64, i64, i64, i64, i64, i64 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block_ymm(%struct.S8* nocapture %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_conditional_block_ymm(%struct.S8* nocapture noalias %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block_ymm:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebx
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    pushl %edi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    pushl %esi
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
if.end:                                           ; preds = %if.then, %entry
   %0 = bitcast %struct.S8* %s3 to i8*
   %1 = bitcast %struct.S8* %s4 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 32, i32 4, i1 false)
   %2 = bitcast %struct.S8* %s2 to i8*
   %3 = bitcast %struct.S8* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 32, i32 4, i1 false)
   ret void
 }
+define dso_local void @test_alias(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: test_alias:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl %eax, (%ecx)
+; CHECK-NEXT:    movups (%ecx), %xmm0
+; CHECK-NEXT:    movups %xmm0, 4(%ecx)
+; CHECK-NEXT:    retl
+;
+; DISABLED-LABEL: test_alias:
+; DISABLED:       # %bb.0: # %entry
+; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; DISABLED-NEXT:    movl %eax, (%ecx)
+; DISABLED-NEXT:    movups (%ecx), %xmm0
+; DISABLED-NEXT:    movups %xmm0, 4(%ecx)
+; DISABLED-NEXT:    retl
+;
+; CHECK-AVX2-LABEL: test_alias:
+; CHECK-AVX2:       # %bb.0: # %entry
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX2-NEXT:    movl %eax, (%ecx)
+; CHECK-AVX2-NEXT:    movups (%ecx), %xmm0
+; CHECK-AVX2-NEXT:    movups %xmm0, 4(%ecx)
+; CHECK-AVX2-NEXT:    retl
+;
+; CHECK-AVX512-LABEL: test_alias:
+; CHECK-AVX512:       # %bb.0: # %entry
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %eax, (%ecx)
+; CHECK-AVX512-NEXT:    vmovups (%ecx), %xmm0
+; CHECK-AVX512-NEXT:    vmovups %xmm0, 4(%ecx)
+; CHECK-AVX512-NEXT:    retl
+entry:
+  %a = bitcast i8* %A to i32*
+  store i32 %x, i32* %a, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %A, i64 4
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %add.ptr, i8* align 4 %A, i64 16, i32 4, i1 false)
+  ret void
+}
+
+; Function Attrs: nounwind uwtable
+define dso_local void @test_noalias(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: test_noalias:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl %eax, (%ecx)
+; CHECK-NEXT:    movl (%ecx), %eax
+; CHECK-NEXT:    movl %eax, 20(%ecx)
+; CHECK-NEXT:    movl 4(%ecx), %eax
+; CHECK-NEXT:    movl %eax, 24(%ecx)
+; CHECK-NEXT:    movl 8(%ecx), %eax
+; CHECK-NEXT:    movl %eax, 28(%ecx)
+; CHECK-NEXT:    movl 12(%ecx), %eax
+; CHECK-NEXT:    movl %eax, 32(%ecx)
+; CHECK-NEXT:    retl
+;
+; DISABLED-LABEL: test_noalias:
+; DISABLED:       # %bb.0: # %entry
+; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; DISABLED-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; DISABLED-NEXT:    movl %eax, (%ecx)
+; DISABLED-NEXT:    movups (%ecx), %xmm0
+; DISABLED-NEXT:    movups %xmm0, 20(%ecx)
+; DISABLED-NEXT:    retl
+;
+; CHECK-AVX2-LABEL: test_noalias:
+; CHECK-AVX2:       # %bb.0: # %entry
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX2-NEXT:    movl %eax, (%ecx)
+; CHECK-AVX2-NEXT:    movl (%ecx), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 20(%ecx)
+; CHECK-AVX2-NEXT:    movl 4(%ecx), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 24(%ecx)
+; CHECK-AVX2-NEXT:    movl 8(%ecx), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 28(%ecx)
+; CHECK-AVX2-NEXT:    movl 12(%ecx), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 32(%ecx)
+; CHECK-AVX2-NEXT:    retl
+;
+; CHECK-AVX512-LABEL: test_noalias:
+; CHECK-AVX512:       # %bb.0: # %entry
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-AVX512-NEXT:    movl %eax, (%ecx)
+; CHECK-AVX512-NEXT:    movl (%ecx), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 20(%ecx)
+; CHECK-AVX512-NEXT:    movl 4(%ecx), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 24(%ecx)
+; CHECK-AVX512-NEXT:    movl 8(%ecx), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 28(%ecx)
+; CHECK-AVX512-NEXT:    movl 12(%ecx), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 32(%ecx)
+; CHECK-AVX512-NEXT:    retl
+entry:
+  %a = bitcast i8* %A to i32*
+  store i32 %x, i32* %a, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %A, i64 20
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %add.ptr, i8* align 4 %A, i64 16, i32 4, i1 false)
+  ret void
+}
+
 

test/CodeGen/X86/fixup-sfb.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK
 ; RUN: llc < %s -mtriple=x86_64-linux --disable-fixup-SFB | FileCheck %s --check-prefix=DISABLED
 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core-avx2 | FileCheck %s -check-prefix=CHECK-AVX2
 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=skx | FileCheck %s -check-prefix=CHECK-AVX512
 
-; RUN: llc < %s -mtriple=i686-linux
-; RUN: llc < %s -mtriple=i686-linux --disable-fixup-SFB
-; RUN: llc < %s -mtriple=i686-linux -mattr sse4
-; RUN: llc < %s -mtriple=i686-linux -mattr avx512
-
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 %struct.S = type { i32, i32, i32, i32 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_conditional_block(%struct.S* nocapture noalias %s1 , %struct.S* nocapture noalias %s2, i32 %x, %struct.S* nocapture noalias  %s3, %struct.S* nocapture noalias readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movl %edx, 4(%rdi)
 ; CHECK-NEXT:  .LBB0_2: # %if.end
 ; CHECK-NEXT:    movups (%r8), %xmm0
if.end:                                           ; preds = %if.then, %entry
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_imm_store(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3) local_unnamed_addr #0 {
+define void @test_imm_store(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_imm_store:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl $0, (%rdi)
 ; CHECK-NEXT:    movl $1, (%rcx)
 ; CHECK-NEXT:    movl (%rdi), %eax
 ; CHECK-NEXT:    movl %eax, (%rsi)
 ; CHECK-NEXT:    movq 4(%rdi), %rax
 ; CHECK-NEXT:    movq %rax, 4(%rsi)
entry:
   store i32 1, i32* %a1, align 4
   %0 = bitcast %struct.S* %s2 to i8*
   %1 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_nondirect_br(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_nondirect_br(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_nondirect_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movl %edx, 4(%rdi)
 ; CHECK-NEXT:  .LBB2_2: # %if.end
 ; CHECK-NEXT:    cmpl $14, %r9d
if.end3:                                          ; preds = %if.then2, %if.end
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_2preds_block(%struct.S* nocapture %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_2preds_block(%struct.S* nocapture noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_2preds_block:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl %r9d, 12(%rdi)
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB3_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movl %edx, 4(%rdi)
 ; CHECK-NEXT:  .LBB3_2: # %if.end
if.end:                                           ; preds = %if.then, %entry
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 %struct.S2 = type { i64, i64 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_type64(%struct.S2* nocapture %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_type64(%struct.S2* nocapture noalias %s1, %struct.S2* nocapture %s2, i32 %x, %struct.S2* nocapture %s3, %struct.S2* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_type64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB4_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movslq %edx, %rax
 ; CHECK-NEXT:    movq %rax, 8(%rdi)
 ; CHECK-NEXT:  .LBB4_2: # %if.end
if.end:                                           ; preds = %if.then, %entry
   %2 = bitcast %struct.S2* %s2 to i8*
   %3 = bitcast %struct.S2* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 8, i1 false)
   ret void
 }
 %struct.S3 = type { i64, i8, i8, i16, i32 }
 
 ; Function Attrs: noinline nounwind uwtable
-define void @test_mixed_type(%struct.S3* nocapture %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 {
+define void @test_mixed_type(%struct.S3* nocapture noalias %s1, %struct.S3* nocapture %s2, i32 %x, %struct.S3* nocapture readnone %s3, %struct.S3* nocapture readnone %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_mixed_type:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB5_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movslq %edx, %rax
 ; CHECK-NEXT:    movq %rax, (%rdi)
 ; CHECK-NEXT:    movb %dl, 8(%rdi)
if.end:                                           ; preds = %if.then, %entry
   %0 = bitcast %struct.S3* %s2 to i8*
   %1 = bitcast %struct.S3* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 8, i1 false)
   ret void
 }
 %struct.S4 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_multiple_blocks(%struct.S4* nocapture %s1, %struct.S4* nocapture %s2) local_unnamed_addr #0 {
+define void @test_multiple_blocks(%struct.S4* nocapture noalias %s1, %struct.S4* nocapture %s2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_multiple_blocks:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl $0, 4(%rdi)
 ; CHECK-NEXT:    movl $0, 36(%rdi)
 ; CHECK-NEXT:    movups 16(%rdi), %xmm0
 ; CHECK-NEXT:    movups %xmm0, 16(%rsi)
 ; CHECK-NEXT:    movl 32(%rdi), %eax
 ; CHECK-NEXT:    movl %eax, 32(%rsi)
entry:
   %0 = bitcast %struct.S4* %s2 to i8*
   %1 = bitcast %struct.S4* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 48, i32 4, i1 false)
   ret void
 }
 %struct.S5 = type { i16, i16, i16, i16, i16, i16, i16, i16 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_type16(%struct.S5* nocapture %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_type16(%struct.S5* nocapture noalias %s1, %struct.S5* nocapture %s2, i32 %x, %struct.S5* nocapture %s3, %struct.S5* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_type16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movw %dx, 2(%rdi)
 ; CHECK-NEXT:  .LBB7_2: # %if.end
 ; CHECK-NEXT:    movups (%r8), %xmm0

 ; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm0
 ; CHECK-NEXT:    movups %xmm0, (%rdi)
 ; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    movq %rax, 16(%rdi)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    movl %eax, 24(%rdi)
 ; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-NEXT:    movl %eax, 28(%rdi)
+; CHECK-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm0
+; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%rsp), %edx
+; CHECK-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movl %edx, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
 ;
 ; DISABLED-LABEL: test_stack:
 ; DISABLED:       # %bb.0: # %entry
 ; DISABLED-NEXT:    movl %esi, {{[0-9]+}}(%rsp)
 ; DISABLED-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm0
 ; DISABLED-NEXT:    movups %xmm0, (%rdi)
 ; DISABLED-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm0
 ; DISABLED-NEXT:    movups %xmm0, 16(%rdi)
+; DISABLED-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm0
+; DISABLED-NEXT:    movaps {{[0-9]+}}(%rsp), %xmm1
+; DISABLED-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
+; DISABLED-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; DISABLED-NEXT:    movq %rdi, %rax
 ; DISABLED-NEXT:    retq
 ;
 ; CHECK-AVX2-LABEL: test_stack:
 ; CHECK-AVX2:       # %bb.0: # %entry
 ; CHECK-AVX2-NEXT:    movl %esi, {{[0-9]+}}(%rsp)
 ; CHECK-AVX2-NEXT:    vmovups {{[0-9]+}}(%rsp), %xmm0
 ; CHECK-AVX2-NEXT:    vmovups %xmm0, (%rdi)
 ; CHECK-AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; CHECK-AVX2-NEXT:    movq %rax, 16(%rdi)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-AVX2-NEXT:    movl %eax, 24(%rdi)
 ; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-AVX2-NEXT:    movl %eax, 28(%rdi)
+; CHECK-AVX2-NEXT:    vmovups {{[0-9]+}}(%rsp), %xmm0
+; CHECK-AVX2-NEXT:    vmovups %xmm0, {{[0-9]+}}(%rsp)
+; CHECK-AVX2-NEXT:    movq {{[0-9]+}}(%rsp), %rax
+; CHECK-AVX2-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%rsp), %eax
+; CHECK-AVX2-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; CHECK-AVX2-NEXT:    movl {{[0-9]+}}(%rsp), %eax
+; CHECK-AVX2-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
 ; CHECK-AVX2-NEXT:    movq %rdi, %rax
 ; CHECK-AVX2-NEXT:    retq
 ;
 ; CHECK-AVX512-LABEL: test_stack:
 ; CHECK-AVX512:       # %bb.0: # %entry
 ; CHECK-AVX512-NEXT:    movl %esi, {{[0-9]+}}(%rsp)
 ; CHECK-AVX512-NEXT:    vmovups {{[0-9]+}}(%rsp), %xmm0
 ; CHECK-AVX512-NEXT:    vmovups %xmm0, (%rdi)
 ; CHECK-AVX512-NEXT:    movq {{[0-9]+}}(%rsp), %rax
 ; CHECK-AVX512-NEXT:    movq %rax, 16(%rdi)
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-AVX512-NEXT:    movl %eax, 24(%rdi)
 ; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%rsp), %eax
 ; CHECK-AVX512-NEXT:    movl %eax, 28(%rdi)
+; CHECK-AVX512-NEXT:    vmovups {{[0-9]+}}(%rsp), %xmm0
+; CHECK-AVX512-NEXT:    vmovups %xmm0, {{[0-9]+}}(%rsp)
+; CHECK-AVX512-NEXT:    movq {{[0-9]+}}(%rsp), %rax
+; CHECK-AVX512-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%rsp), %eax
+; CHECK-AVX512-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
+; CHECK-AVX512-NEXT:    movl {{[0-9]+}}(%rsp), %eax
+; CHECK-AVX512-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
 ; CHECK-AVX512-NEXT:    movq %rdi, %rax
 ; CHECK-AVX512-NEXT:    retq
 entry:
   %s6.sroa.0.0..sroa_cast1 = bitcast %struct.S6* %s2 to i8*
   %s6.sroa.3.0..sroa_idx4 = getelementptr inbounds %struct.S6, %struct.S6* %s2, i64 0, i32 3
   store i32 %x, i32* %s6.sroa.3.0..sroa_idx4, align 8
   %0 = bitcast %struct.S6* %agg.result to i8*
+  %s6.sroa.0.0..sroa_cast2 = bitcast %struct.S6* %s1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* nonnull %s6.sroa.0.0..sroa_cast1, i64 32, i32 4, i1 false)
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %s6.sroa.0.0..sroa_cast2, i8* nonnull %s6.sroa.0.0..sroa_cast1, i64 32, i32 4, i1 false)
+
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_limit_all(%struct.S* %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_limit_all(%struct.S* noalias  %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_limit_all:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushq %rbp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    pushq %r15
 ; CHECK-NEXT:    .cfi_def_cfa_offset 24
 ; CHECK-NEXT:    pushq %r14
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
if.end:                                           ; preds = %if.then, %entry
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 16, i32 4, i1 false)
   %2 = bitcast %struct.S* %s2 to i8*
   %3 = bitcast %struct.S* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 16, i32 4, i1 false)
   ret void
 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_limit_one_pred(%struct.S* %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
+define void @test_limit_one_pred(%struct.S* noalias %s1, %struct.S* nocapture %s2, i32 %x, %struct.S* nocapture %s3, %struct.S* nocapture readonly %s4, i32 %x2) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_limit_one_pred:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushq %r15
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    pushq %r14
 ; CHECK-NEXT:    .cfi_def_cfa_offset 24
 ; CHECK-NEXT:    pushq %r12
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32

 ; Function Attrs: argmemonly nounwind
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1
 
 attributes #0 = { nounwind uwtable "target-cpu"="x86-64" }
 
 %struct.S7 = type { float, float, float , float, float, float, float, float }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block_float(%struct.S7* nocapture %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 {
+define void @test_conditional_block_float(%struct.S7* nocapture noalias %s1, %struct.S7* nocapture %s2, i32 %x, %struct.S7* nocapture %s3, %struct.S7* nocapture readonly %s4, float %y) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block_float:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB11_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movl $1065353216, 4(%rdi) # imm = 0x3F800000
 ; CHECK-NEXT:  .LBB11_2: # %if.end
 ; CHECK-NEXT:    movups (%r8), %xmm0
if.end:                                           ; preds = %if.then, %entry
   %3 = bitcast %struct.S7* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 32, i32 4, i1 false)
   ret void
 }
 
 %struct.S8 = type { i64, i64, i64, i64, i64, i64 }
 
 ; Function Attrs: nounwind uwtable
-define void @test_conditional_block_ymm(%struct.S8* nocapture %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 {
+define void @test_conditional_block_ymm(%struct.S8* nocapture noalias %s1, %struct.S8* nocapture %s2, i32 %x, %struct.S8* nocapture %s3, %struct.S8* nocapture readonly %s4) local_unnamed_addr #0 {
 ; CHECK-LABEL: test_conditional_block_ymm:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpl $18, %edx
 ; CHECK-NEXT:    jl .LBB12_2
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ; CHECK-NEXT:    movq $1, 8(%rdi)
 ; CHECK-NEXT:  .LBB12_2: # %if.end
 ; CHECK-NEXT:    movups (%r8), %xmm0
if.end:                                           ; preds = %if.then, %entry
   %1 = bitcast %struct.S8* %s4 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* %1, i64 32, i32 4, i1 false)
   %2 = bitcast %struct.S8* %s2 to i8*
   %3 = bitcast %struct.S8* %s1 to i8*
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 32, i32 4, i1 false)
   ret void
 }
 
+define dso_local void @test_alias(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: test_alias:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, (%rdi)
+; CHECK-NEXT:    movups (%rdi), %xmm0
+; CHECK-NEXT:    movups %xmm0, 4(%rdi)
+; CHECK-NEXT:    retq
+;
+; DISABLED-LABEL: test_alias:
+; DISABLED:       # %bb.0: # %entry
+; DISABLED-NEXT:    movl %esi, (%rdi)
+; DISABLED-NEXT:    movups (%rdi), %xmm0
+; DISABLED-NEXT:    movups %xmm0, 4(%rdi)
+; DISABLED-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test_alias:
+; CHECK-AVX2:       # %bb.0: # %entry
+; CHECK-AVX2-NEXT:    movl %esi, (%rdi)
+; CHECK-AVX2-NEXT:    vmovups (%rdi), %xmm0
+; CHECK-AVX2-NEXT:    vmovups %xmm0, 4(%rdi)
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-AVX512-LABEL: test_alias:
+; CHECK-AVX512:       # %bb.0: # %entry
+; CHECK-AVX512-NEXT:    movl %esi, (%rdi)
+; CHECK-AVX512-NEXT:    vmovups (%rdi), %xmm0
+; CHECK-AVX512-NEXT:    vmovups %xmm0, 4(%rdi)
+; CHECK-AVX512-NEXT:    retq
+entry:
+  %a = bitcast i8* %A to i32*
+  store i32 %x, i32* %a, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %A, i64 4
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %add.ptr, i8* align 4 %A, i64 16, i32 4, i1 false)
+  ret void
+}
+
+; Function Attrs: nounwind uwtable
+define dso_local void @test_noalias(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
+; CHECK-LABEL: test_noalias:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %esi, (%rdi)
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    movl %eax, 20(%rdi)
+; CHECK-NEXT:    movq 4(%rdi), %rax
+; CHECK-NEXT:    movq %rax, 24(%rdi)
+; CHECK-NEXT:    movl 12(%rdi), %eax
+; CHECK-NEXT:    movl %eax, 32(%rdi)
+; CHECK-NEXT:    retq
+;
+; DISABLED-LABEL: test_noalias:
+; DISABLED:       # %bb.0: # %entry
+; DISABLED-NEXT:    movl %esi, (%rdi)
+; DISABLED-NEXT:    movups (%rdi), %xmm0
+; DISABLED-NEXT:    movups %xmm0, 20(%rdi)
+; DISABLED-NEXT:    retq
+;
+; CHECK-AVX2-LABEL: test_noalias:
+; CHECK-AVX2:       # %bb.0: # %entry
+; CHECK-AVX2-NEXT:    movl %esi, (%rdi)
+; CHECK-AVX2-NEXT:    movl (%rdi), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 20(%rdi)
+; CHECK-AVX2-NEXT:    movq 4(%rdi), %rax
+; CHECK-AVX2-NEXT:    movq %rax, 24(%rdi)
+; CHECK-AVX2-NEXT:    movl 12(%rdi), %eax
+; CHECK-AVX2-NEXT:    movl %eax, 32(%rdi)
+; CHECK-AVX2-NEXT:    retq
+;
+; CHECK-AVX512-LABEL: test_noalias:
+; CHECK-AVX512:       # %bb.0: # %entry
+; CHECK-AVX512-NEXT:    movl %esi, (%rdi)
+; CHECK-AVX512-NEXT:    movl (%rdi), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 20(%rdi)
+; CHECK-AVX512-NEXT:    movq 4(%rdi), %rax
+; CHECK-AVX512-NEXT:    movq %rax, 24(%rdi)
+; CHECK-AVX512-NEXT:    movl 12(%rdi), %eax
+; CHECK-AVX512-NEXT:    movl %eax, 32(%rdi)
+; CHECK-AVX512-NEXT:    retq
+entry:
+  %a = bitcast i8* %A to i32*
+  store i32 %x, i32* %a, align 4
+  %add.ptr = getelementptr inbounds i8, i8* %A, i64 20
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull align 4 %add.ptr, i8* align 4 %A, i64 16, i32 4, i1 false)
+  ret void
+}
+
+
+