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Differential D42526

[X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP
ClosedPublic

Authored by RKSimon on Jan 25 2018, 3:42 AM.

Details

Reviewers
zvi
craig.topper
spatel
Commits
rG073f089c6e5b: [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP
rL323797: [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP
Summary

Similar to D42437, XOP support variable shift for v16i8/v8i16/v4i32/v2i64 types.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon created this revision.Jan 25 2018, 3:42 AM
Herald added subscribers: tschuett, rengolin. · View Herald TranscriptJan 25 2018, 3:42 AM
zvi accepted this revision.Jan 30 2018, 5:24 AM

LGTM

This revision is now accepted and ready to land.Jan 30 2018, 5:24 AM
Closed by commit rL323797: [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP (authored by RKSimon). · Explain WhyJan 30 2018, 10:12 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
X86ISelLowering.cpp
X86ISelLowering.cpp (revision 323414)
5 lines
test/
Transforms/
CodeGenPrepare/
X86/
x86-shuffle-sink.ll
x86-shuffle-sink.ll (revision 323414)
9 lines

Diff 131410

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const { bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
unsigned Bits = Ty->getScalarSizeInBits(); unsigned Bits = Ty->getScalarSizeInBits();
// 8-bit shifts are always expensive, but versions with a scalar amount aren't // 8-bit shifts are always expensive, but versions with a scalar amount aren't
// particularly cheaper than those without. // particularly cheaper than those without.
if (Bits == 8) if (Bits == 8)
return false; return false;
// XOP has v16i8/v8i16/v4i32/v2i64 variable vector shifts.
if (Subtarget.hasXOP() && Ty->getPrimitiveSizeInBits() == 128 &&
(Bits == 8 || Bits == 16 || Bits == 32 || Bits == 64))
return false;
// AVX2 has vpsllv[dq] instructions (and other shifts) that make variable // AVX2 has vpsllv[dq] instructions (and other shifts) that make variable
// shifts just as cheap as scalar ones. // shifts just as cheap as scalar ones.
if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64)) if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))
return false; return false;
// AVX512BW has shifts such as vpsllvw. // AVX512BW has shifts such as vpsllvw.
if (Subtarget.hasBWI() && Bits == 16) if (Subtarget.hasBWI() && Bits == 16)
return false; return false;
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test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll

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; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]] ; CHECK-SSE2-NEXT: ret <8 x i16> [[RES]]
; ;
; CHECK-XOP-LABEL: @test_16bit( ; CHECK-XOP-LABEL: @test_16bit(
; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-XOP: if_true: ; CHECK-XOP: if_true:
; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]] ; CHECK-XOP-NEXT: ret <8 x i16> [[MASK]]
; CHECK-XOP: if_false: ; CHECK-XOP: if_false:
; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer ; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
; CHECK-XOP-NEXT: [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
; CHECK-XOP-NEXT: ret <8 x i16> [[RES]] ; CHECK-XOP-NEXT: ret <8 x i16> [[RES]]
; ;
; CHECK-AVX2-LABEL: @test_16bit( ; CHECK-AVX2-LABEL: @test_16bit(
; CHECK-AVX2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer ; CHECK-AVX2-NEXT: [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
; CHECK-AVX2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-AVX2-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-AVX2: if_true: ; CHECK-AVX2: if_true:
; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]] ; CHECK-AVX2-NEXT: ret <8 x i16> [[MASK]]
; CHECK-AVX2: if_false: ; CHECK-AVX2: if_false:
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; CHECK-SSE2-NEXT: ret <4 x i32> [[RES]] ; CHECK-SSE2-NEXT: ret <4 x i32> [[RES]]
; ;
; CHECK-XOP-LABEL: @test_32bit( ; CHECK-XOP-LABEL: @test_32bit(
; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0> ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-XOP: if_true: ; CHECK-XOP: if_true:
; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]] ; CHECK-XOP-NEXT: ret <4 x i32> [[MASK]]
; CHECK-XOP: if_false: ; CHECK-XOP: if_false:
; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0> ; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
; CHECK-XOP-NEXT: [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]]
; CHECK-XOP-NEXT: ret <4 x i32> [[RES]] ; CHECK-XOP-NEXT: ret <4 x i32> [[RES]]
; ;
; CHECK-AVX-LABEL: @test_32bit( ; CHECK-AVX-LABEL: @test_32bit(
; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0> ; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-AVX: if_true: ; CHECK-AVX: if_true:
; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]] ; CHECK-AVX-NEXT: ret <4 x i32> [[MASK]]
; CHECK-AVX: if_false: ; CHECK-AVX: if_false:
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; CHECK-SSE2-NEXT: ret <2 x i64> [[RES]] ; CHECK-SSE2-NEXT: ret <2 x i64> [[RES]]
; ;
; CHECK-XOP-LABEL: @test_64bit( ; CHECK-XOP-LABEL: @test_64bit(
; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer ; CHECK-XOP-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-XOP-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-XOP: if_true: ; CHECK-XOP: if_true:
; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]] ; CHECK-XOP-NEXT: ret <2 x i64> [[MASK]]
; CHECK-XOP: if_false: ; CHECK-XOP: if_false:
; CHECK-XOP-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <2 x i32> zeroinitializer ; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
; CHECK-XOP-NEXT: [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]]
; CHECK-XOP-NEXT: ret <2 x i64> [[RES]] ; CHECK-XOP-NEXT: ret <2 x i64> [[RES]]
; ;
; CHECK-AVX-LABEL: @test_64bit( ; CHECK-AVX-LABEL: @test_64bit(
; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer ; CHECK-AVX-NEXT: [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]] ; CHECK-AVX-NEXT: br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
; CHECK-AVX: if_true: ; CHECK-AVX: if_true:
; CHECK-AVX-NEXT: ret <2 x i64> [[MASK]] ; CHECK-AVX-NEXT: ret <2 x i64> [[MASK]]
; CHECK-AVX: if_false: ; CHECK-AVX: if_false:
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