[PPC] Avoid incorrect fp-i128-fp lowering.

[timshen]

Summary

Fix an issue that's similar to what D41411 fixed:

float(__int128(float_var)) shouldn't be optimized to xscvdpsxds +
xscvsxdsp, as they mean (float)(int64_t)float_var.

[jtony]

llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

1 ↗

(On Diff #130988)

Can we explicitly put CHECK-NOT for the `xscvdpsxds +
xscvsxdsp` instructions we were generating before in this test case to avoid regression?
Other than that, the patch LGTM.

[timshen]

llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

1 ↗

(On Diff #130988)

IIRC update_llc_test_checks.py will remove old CHECKs and re-insert its own CHECKs.

I think with the current line-by-line CHECK-NEXTs, it effectively prevents xscvdpsxds and xscvsxdsp from creeping in.

[echristo]

llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

1 ↗

(On Diff #130988)

It does. And you've got a comment as well so that if it breaks when updating people know what to look for.

With that said, I'm good with this as well. Let's let jtony also ack though since he did the main review.

[jtony]

llvm/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

1 ↗

(On Diff #130988)

Sound good to me.

llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
 
   if (useSoftFloat() || !Subtarget.has64BitSupport())
     return SDValue();
 
   SelectionDAG &DAG = DCI.DAG;
   SDLoc dl(N);
   SDValue Op(N, 0);
 
-  // Don't handle ppc_fp128 here or i1 conversions.
+  // Don't handle ppc_fp128 here or conversions that are out-of-range capable
+  // from the hardware.
   if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
     return SDValue();
-  if (Op.getOperand(0).getValueType() == MVT::i1)
+  if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) ||
+      Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64))
     return SDValue();
 
   SDValue FirstOperand(Op.getOperand(0));
   bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD &&
     (FirstOperand.getValueType() == MVT::i8 ||
      FirstOperand.getValueType() == MVT::i16);
   if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
     bool Signed = N->getOpcode() == ISD::SINT_TO_FP;

llvm/trunk/test/CodeGen/PowerPC/fp-int128-fp-combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; xscvdpsxds should NOT be emitted, since it saturates the result down to i64.
+define float @f_i128_f(float %v) {
+; CHECK-LABEL: f_i128_f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    bl __fixsfti
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    bl __floattisf
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+entry:
+  %a = fptosi float %v to i128
+  %b = sitofp i128 %a to float
+  ret float %b
+}