Index: lib/Basic/Targets.cpp
===================================================================
--- lib/Basic/Targets.cpp
+++ lib/Basic/Targets.cpp
@@ -3839,6 +3839,18 @@
     return true;
   }
   bool setFPMath(StringRef Name) override;
+  bool supportsThumb(StringRef ArchName, StringRef CPUArch,
+                     unsigned CPUArchVer) const {
+    return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
+           (CPUArch.find('M') != StringRef::npos);
+  }
+  bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
+                      unsigned CPUArchVer) const {
+    // We check both CPUArchVer and ArchName because when only triple is
+    // specified, the default CPU is arm1136j-s.
+    return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
+           ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
+  }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     // Target identification.
@@ -3854,8 +3866,35 @@
       llvm_unreachable("Invalid char for architecture version number");
     }
     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
-    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+    // ACLE 6.4.1 ARM/Thumb instruction set architecture
     StringRef CPUProfile = getCPUProfile(CPU);
+    StringRef ArchName = getTriple().getArchName();
+
+    // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
+    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
+
+    // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
+    // is not defined for the M-profile.
+    // NOTE that the deffault profile is assumed to be 'A'
+    if (CPUProfile.empty() || CPUProfile != "M")
+      Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
+
+    // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
+    // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
+    // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
+    if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
+      Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
+    else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
+      Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
+
+    // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
+    // instruction set such as ARM or Thumb.
+    Builder.defineMacro("__ARM_32BIT_STATE", "1");
+
+    // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
+
+    // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
     if (!CPUProfile.empty())
       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
 
@@ -3887,11 +3926,7 @@
     if (IsThumb) {
       Builder.defineMacro("__THUMBEL__");
       Builder.defineMacro("__thumb__");
-      // We check both CPUArchVer and ArchName because when only triple is
-      // specified, the default CPU is arm1136j-s.
-      StringRef ArchName = getTriple().getArchName();
-      if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") ||
-          ArchName.endswith("v7") || ArchName.endswith("v8"))
+      if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
         Builder.defineMacro("__thumb2__");
     }
     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
Index: test/Preprocessor/arm-acle-6.4.c
===================================================================
--- /dev/null
+++ test/Preprocessor/arm-acle-6.4.c
@@ -0,0 +1,40 @@
+// RUN: %clang -target arm-eabi -mcpu=cortex-m0 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-M0
+
+// CHECK-CORTEX-M0: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-M0: __ARM_ARCH 6
+// CHECK-CORTEX-M0-NOT: __ARM_ARCH_ISA_ARM
+// CHECK-CORTEX-M0: __ARM_ARCH_ISA_THUMB 1
+// CHECK-CORTEX-M0: __ARM_ARCH_PROFILE M
+
+// RUN: %clang -target arm-eabi -mcpu=arm810 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM810
+
+// CHECK-ARM810: __ARM_32BIT_STATE 1
+// CHECK-ARM810: __ARM_ARCH 4
+// CHECK-ARM810: __ARM_ARCH_ISA_ARM 1
+// CHECK-ARM810-NOT: __ARM_ARCH_ISA_THUMB
+// CHECK-ARM810-NOT: __ARM_ARCH_PROFILE
+
+// RUN: %clang -target arm-eabi -mcpu=arm7tdmi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-ARM7TDMI
+
+// CHECK-ARM7TDMI: __ARM_32BIT_STATE 1
+// CHECK-ARM7TDMI: __ARM_ARCH 4
+// CHECK-ARM7TDMI: __ARM_ARCH_ISA_ARM 1
+// CHECK-ARM7TDMI: __ARM_ARCH_ISA_THUMB 1
+// CHECK-ARM7TDMI-NOT: __ARM_ARCH_PROFILE
+
+// RUN: %clang -target arm-eabi -mcpu=cortex-a7 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-A7
+
+// CHECK-CORTEX-A7: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-A7: __ARM_ARCH 7
+// CHECK-CORTEX-A7: __ARM_ARCH_ISA_ARM 1
+// CHECK-CORTEX-A7: __ARM_ARCH_ISA_THUMB 2
+// CHECK-CORTEX-A7: __ARM_ARCH_PROFILE A
+
+// RUN: %clang -target arm-eabi -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-CORTEX-R4
+
+// CHECK-CORTEX-R4: __ARM_32BIT_STATE 1
+// CHECK-CORTEX-R4: __ARM_ARCH 7
+// CHECK-CORTEX-R4: __ARM_ARCH_ISA_ARM 1
+// CHECK-CORTEX-R4: __ARM_ARCH_ISA_THUMB 2
+// CHECK-CORTEX-R4: __ARM_ARCH_PROFILE R
+