Index: lib/Target/R600/SIInstrInfo.cpp
===================================================================
--- lib/Target/R600/SIInstrInfo.cpp
+++ lib/Target/R600/SIInstrInfo.cpp
@@ -650,10 +650,10 @@
   case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
   case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
   case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
-  case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
-  case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
-  case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
-  case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
+  case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32_si;
+  case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32_si;
+  case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32_si;
+  case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32_si;
   case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
   case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
   case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
Index: lib/Target/R600/SIInstrInfo.td
===================================================================
--- lib/Target/R600/SIInstrInfo.td
+++ lib/Target/R600/SIInstrInfo.td
@@ -259,13 +259,16 @@
 
 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
                    string opName> {
+  // XXX - What is this for? If you use that version, the TSFlags
+  // aren't set on it, which prevents every check for what encoding
+  // this is from working.
 
-  def "" : InstSI <outs, ins, "", pattern>, VOP <opName>,
-           SIMCInstr<OpName, SISubtarget.NONE> {
-    let isPseudo = 1;
-  }
+  // def "" : InstSI <outs, ins, "", pattern>, VOP <opName>,
+  //          SIMCInstr<OpName, SISubtarget.NONE> {
+  //    let isPseudo = 1;
+  // }
 
-  def _si : VOP3 <op, outs, ins, asm, []>, SIMCInstr<opName, SISubtarget.SI>;
+  def _si : VOP3 <op, outs, ins, asm, pattern>, SIMCInstr<opName, SISubtarget.SI>;
 
 }
 
Index: lib/Target/R600/SIInstructions.td
===================================================================
--- lib/Target/R600/SIInstructions.td
+++ lib/Target/R600/SIInstructions.td
@@ -2027,22 +2027,22 @@
 def : Pat <
   (int_AMDGPU_cube v4f32:$src),
   (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
-    (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0),
-                  (EXTRACT_SUBREG $src, sub1),
-                  (EXTRACT_SUBREG $src, sub2)),
-                   sub0),
-    (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0),
-                  (EXTRACT_SUBREG $src, sub1),
-                  (EXTRACT_SUBREG $src, sub2)),
-                   sub1),
-    (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0),
-                  (EXTRACT_SUBREG $src, sub1),
-                  (EXTRACT_SUBREG $src, sub2)),
-                   sub2),
-    (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0),
-                  (EXTRACT_SUBREG $src, sub1),
-                  (EXTRACT_SUBREG $src, sub2)),
-                   sub3)
+    (V_CUBETC_F32_si (EXTRACT_SUBREG $src, sub0),
+                     (EXTRACT_SUBREG $src, sub1),
+                     (EXTRACT_SUBREG $src, sub2)),
+                     sub0),
+    (V_CUBESC_F32_si (EXTRACT_SUBREG $src, sub0),
+                     (EXTRACT_SUBREG $src, sub1),
+                     (EXTRACT_SUBREG $src, sub2)),
+                     sub1),
+    (V_CUBEMA_F32_si (EXTRACT_SUBREG $src, sub0),
+                     (EXTRACT_SUBREG $src, sub1),
+                     (EXTRACT_SUBREG $src, sub2)),
+                     sub2),
+    (V_CUBEID_F32_si (EXTRACT_SUBREG $src, sub0),
+                     (EXTRACT_SUBREG $src, sub1),
+                     (EXTRACT_SUBREG $src, sub2)),
+                     sub3)
 >;
 
 def : Pat <
@@ -2082,8 +2082,8 @@
 // VOP3 Patterns
 //===----------------------------------------------------------------------===//
 
-def : IMad24Pat<V_MAD_I32_I24>;
-def : UMad24Pat<V_MAD_U32_U24>;
+def : IMad24Pat<V_MAD_I32_I24_si>;
+def : UMad24Pat<V_MAD_U32_U24_si>;
 
 def : Pat <
   (fadd f64:$src0, f64:$src1),
@@ -2097,21 +2097,21 @@
 
 def : Pat <
   (mul i32:$src0, i32:$src1),
-  (V_MUL_LO_I32 $src0, $src1, (i32 0))
+  (V_MUL_LO_I32_si $src0, $src1, (i32 0))
 >;
 
 def : Pat <
   (mulhu i32:$src0, i32:$src1),
-  (V_MUL_HI_U32 $src0, $src1, (i32 0))
+  (V_MUL_HI_U32_si $src0, $src1, (i32 0))
 >;
 
 def : Pat <
   (mulhs i32:$src0, i32:$src1),
-  (V_MUL_HI_I32 $src0, $src1, (i32 0))
+  (V_MUL_HI_I32_si $src0, $src1, (i32 0))
 >;
 
-defm : BFIPatterns <V_BFI_B32>;
-def : ROTRPattern <V_ALIGNBIT_B32>;
+defm : BFIPatterns <V_BFI_B32_si>;
+def : ROTRPattern <V_ALIGNBIT_B32_si>;
 
 /********** ======================= **********/
 /**********   Load/Store Patterns   **********/
@@ -2474,6 +2474,6 @@
 // Miscellaneous Optimization Patterns
 //============================================================================//
 
-def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
+def : SHA256MaPattern <V_BFI_B32_si, V_XOR_B32_e32>;
 
 } // End isSI predicate