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Differential D39488

[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
ClosedPublic

Authored by dp on Nov 1 2017, 5:19 AM.

Details

Reviewers
SamWot
artem.tamazov
arsenm
vpykhtin
Commits
rG0e8924a5c721: [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
rL318955: [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
Summary

See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Diff Detail

Repository
rL LLVM

Event Timeline

dp created this revision.Nov 1 2017, 5:19 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptNov 1 2017, 5:19 AM
dp added a reviewer: vpykhtin.Nov 20 2017, 7:30 AM
dp added a comment.EditedNov 24 2017, 5:52 AM

As nobody was interested in reviewing this patch, I'll commit it next week.

SamWot accepted this revision.Nov 24 2017, 6:04 AM
This revision is now accepted and ready to land.Nov 24 2017, 6:04 AM
Closed by commit rL318955: [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 (authored by dpreobra). · Explain WhyNov 24 2017, 7:37 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
20 lines
test/
MC/
AMDGPU/
36 lines
Disassembler/
AMDGPU/
36 lines

Diff 124210

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

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let isCommutable = 1 in { let isCommutable = 1 in {
let renamedInGFX9 = 1 in { let renamedInGFX9 = 1 in {
def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>; def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>; def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>; def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
} }
let SubtargetPredicate = isGFX9 in { let SubtargetPredicate = isGFX9 in {
def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>; def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>; def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>; def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
} // End SubtargetPredicate = isGFX9 } // End SubtargetPredicate = isGFX9
def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>; def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>; def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
} // End isCommutable = 1 } // End isCommutable = 1
} // End SubtargetPredicate = Has16BitInsts } // End SubtargetPredicate = Has16BitInsts
let SubtargetPredicate = isVI in { let SubtargetPredicate = isVI in {
def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>; def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
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let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in { let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
multiclass VOP3_F16_Real_vi<bits<10> op> { multiclass VOP3_F16_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>, def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>; VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
} }
multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
}
} // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" } // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in { let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> { multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>, def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> { VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName); VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
let AsmString = AsmName # ps.AsmOperands; let AsmString = AsmName # ps.AsmOperands;
} }
} }
multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> { multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>, def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> { VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME); VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
let AsmString = AsmName # ps.AsmOperands; let AsmString = AsmName # ps.AsmOperands;
} }
} }
multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
let AsmString = AsmName # ps.AsmOperands;
}
}
multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> { multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>, def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> { VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME); VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
let AsmString = AsmName # ps.AsmOperands; let AsmString = AsmName # ps.AsmOperands;
} }
} }
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defm V_PERM_B32 : VOP3_Real_vi <0x1ed>; defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>; defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>; defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>; defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>; defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>; defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>;
defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">; defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">; defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">; defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">; defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">; defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">; defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">; defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">; defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">; defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">; defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">; defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">; defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>; defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>; defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>; defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>; defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>; defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
defm V_ADD_F64 : VOP3_Real_vi <0x280>; defm V_ADD_F64 : VOP3_Real_vi <0x280>;
defm V_MUL_F64 : VOP3_Real_vi <0x281>; defm V_MUL_F64 : VOP3_Real_vi <0x281>;
defm V_MIN_F64 : VOP3_Real_vi <0x282>; defm V_MIN_F64 : VOP3_Real_vi <0x282>;
defm V_MAX_F64 : VOP3_Real_vi <0x283>; defm V_MAX_F64 : VOP3_Real_vi <0x283>;
defm V_LDEXP_F64 : VOP3_Real_vi <0x284>; defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>; defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
// removed from VI as identical to V_MUL_LO_U32 // removed from VI as identical to V_MUL_LO_U32
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llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s

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v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04]
v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
// GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
v_interp_p2_f16 v5, v2, attr0.x, v3
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
v_interp_p2_f16 v5, -v2, attr0.x, v3
// GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
v_interp_p2_f16 v5, v2, attr0.x, |v3|
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
v_interp_p2_f16 v5, v2, attr0.w, v3
// GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
v_interp_p2_f16 v5, v2, attr0.x, v3 high
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
// GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
// GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
// GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

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# GFX9: v_mad_mixlo_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04] # GFX9: v_mad_mixlo_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04 0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04
# GFX9: v_mad_mixlo_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04] # GFX9: v_mad_mixlo_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04 0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04
# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04] # GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04 0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04
# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04
# GFX9: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44
# GFX9: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04
# GFX9: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04
# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04
# GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr31.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
# GFX9: v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04