Index: include/llvm/CodeGen/MachineOperand.h
===================================================================
--- include/llvm/CodeGen/MachineOperand.h
+++ include/llvm/CodeGen/MachineOperand.h
@@ -85,8 +85,8 @@
   /// before MachineInstr::tieOperands().
   unsigned char TiedTo : 4;
 
-  /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
-  /// operands.
+  /// IsDef/IsImp/IsDeadOrKill/IsRenamable flags - These are
+  /// only valid for MO_Register opderands.
 
   /// IsDef - True if this is a def, false if this is a use of the register.
   ///
@@ -96,13 +96,18 @@
   ///
   bool IsImp : 1;
 
-  /// IsKill - True if this instruction is the last use of the register on this
-  /// path through the function.  This is only valid on uses of registers.
-  bool IsKill : 1;
+  /// IsDeadOrKill
+  /// For uses: IsKill - True if this instruction is the last use of the
+  /// register on this path through the function.
+  /// For defs: IsDead - True if this register is never used by a subsequent
+  /// instruction.  This is only valid on definitions of registers.
+  bool IsDeadOrKill : 1;
 
-  /// IsDead - True if this register is never used by a subsequent instruction.
-  /// This is only valid on definitions of registers.
-  bool IsDead : 1;
+  /// IsRenamable - True if this register may be safely renamed,
+  /// i.e. that it does not generate a value that is somehow read in a way that
+  /// is not represented by the Machine IR (e.g. to meet an ABI or ISA
+  /// requirement).
+  bool IsRenamable : 1;
 
   /// IsUndef - True if this register operand reads an "undef" value, i.e. the
   /// read value doesn't matter.  This flag can be set on both use and def
@@ -303,12 +308,12 @@
 
   bool isDead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsDead;
+    return IsDeadOrKill & IsDef;
   }
 
   bool isKill() const {
     assert(isReg() && "Wrong MachineOperand accessor");
-    return IsKill;
+    return IsDeadOrKill & !IsDef;
   }
 
   bool isUndef() const {
@@ -316,6 +321,11 @@
     return IsUndef;
   }
 
+  bool isRenamable() const {
+    assert(isReg() && "Wrong MachineOperand accessor");
+    return IsRenamable;
+  }
+
   bool isInternalRead() const {
     assert(isReg() && "Wrong MachineOperand accessor");
     return IsInternalRead;
@@ -355,6 +365,11 @@
   /// Change the register this operand corresponds to.
   ///
   void setReg(unsigned Reg);
+  /// Same as setReg() above, but preserves the current value of isRenamable().
+  /// This allows e.g. the register allocators to create physical register
+  /// operands that are marked as being renamable if they were virtual registers
+  /// before allocation.
+  void setRegKeepRenamable(unsigned Reg);
 
   void setSubReg(unsigned subReg) {
     assert(isReg() && "Wrong MachineOperand mutator");
@@ -387,12 +402,12 @@
   void setIsKill(bool Val = true) {
     assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
     assert((!Val || !isDebug()) && "Marking a debug operation as kill");
-    IsKill = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsDead(bool Val = true) {
     assert(isReg() && IsDef && "Wrong MachineOperand mutator");
-    IsDead = Val;
+    IsDeadOrKill = Val;
   }
 
   void setIsUndef(bool Val = true) {
@@ -400,6 +415,11 @@
     IsUndef = Val;
   }
 
+  void setIsRenamable(bool Val = true) {
+    assert(isReg() && "Wrong MachineOperand mutator");
+    IsRenamable = Val;
+  }
+
   void setIsInternalRead(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand mutator");
     IsInternalRead = Val;
@@ -643,25 +663,7 @@
                                   bool isEarlyClobber = false,
                                   unsigned SubReg = 0,
                                   bool isDebug = false,
-                                  bool isInternalRead = false) {
-    assert(!(isDead && !isDef) && "Dead flag on non-def");
-    assert(!(isKill && isDef) && "Kill flag on def");
-    MachineOperand Op(MachineOperand::MO_Register);
-    Op.IsDef = isDef;
-    Op.IsImp = isImp;
-    Op.IsKill = isKill;
-    Op.IsDead = isDead;
-    Op.IsUndef = isUndef;
-    Op.IsInternalRead = isInternalRead;
-    Op.IsEarlyClobber = isEarlyClobber;
-    Op.TiedTo = 0;
-    Op.IsDebug = isDebug;
-    Op.SmallContents.RegNo = Reg;
-    Op.Contents.Reg.Prev = nullptr;
-    Op.Contents.Reg.Next = nullptr;
-    Op.setSubReg(SubReg);
-    return Op;
-  }
+                                  bool isInternalRead = false);
   static MachineOperand CreateMBB(MachineBasicBlock *MBB,
                                   unsigned char TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
Index: lib/CodeGen/MIRParser/MILexer.h
===================================================================
--- lib/CodeGen/MIRParser/MILexer.h
+++ lib/CodeGen/MIRParser/MILexer.h
@@ -56,6 +56,7 @@
     kw_dead,
     kw_dereferenceable,
     kw_killed,
+    kw_norename,
     kw_undef,
     kw_internal,
     kw_early_clobber,
@@ -164,7 +165,7 @@
   bool isRegisterFlag() const {
     return Kind == kw_implicit || Kind == kw_implicit_define ||
            Kind == kw_def || Kind == kw_dead || Kind == kw_killed ||
-           Kind == kw_undef || Kind == kw_internal ||
+           Kind == kw_norename || Kind == kw_undef || Kind == kw_internal ||
            Kind == kw_early_clobber || Kind == kw_debug_use;
   }
 
Index: lib/CodeGen/MIRParser/MILexer.cpp
===================================================================
--- lib/CodeGen/MIRParser/MILexer.cpp
+++ lib/CodeGen/MIRParser/MILexer.cpp
@@ -204,6 +204,7 @@
       .Case("def", MIToken::kw_def)
       .Case("dead", MIToken::kw_dead)
       .Case("killed", MIToken::kw_killed)
+      .Case("norename", MIToken::kw_norename)
       .Case("undef", MIToken::kw_undef)
       .Case("internal", MIToken::kw_internal)
       .Case("early-clobber", MIToken::kw_early_clobber)
Index: lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIParser.cpp
+++ lib/CodeGen/MIRParser/MIParser.cpp
@@ -184,7 +184,7 @@
   bool parseNamedRegister(unsigned &Reg);
   bool parseVirtualRegister(VRegInfo *&Info);
   bool parseRegister(unsigned &Reg, VRegInfo *&VRegInfo);
-  bool parseRegisterFlag(unsigned &Flags);
+  bool parseRegisterFlag(unsigned &Flags, bool &NoRename);
   bool parseRegisterClassOrBank(VRegInfo &RegInfo);
   bool parseSubRegisterIndex(unsigned &SubReg);
   bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx);
@@ -1030,7 +1030,7 @@
   llvm_unreachable("Unexpected register kind");
 }
 
-bool MIParser::parseRegisterFlag(unsigned &Flags) {
+bool MIParser::parseRegisterFlag(unsigned &Flags, bool &NoRename) {
   const unsigned OldFlags = Flags;
   switch (Token.kind()) {
   case MIToken::kw_implicit:
@@ -1048,6 +1048,9 @@
   case MIToken::kw_killed:
     Flags |= RegState::Kill;
     break;
+  case MIToken::kw_norename:
+    NoRename = true;
+    break;
   case MIToken::kw_undef:
     Flags |= RegState::Undef;
     break;
@@ -1137,9 +1140,10 @@
 bool MIParser::parseRegisterOperand(MachineOperand &Dest,
                                     Optional<unsigned> &TiedDefIdx,
                                     bool IsDef) {
+  bool NoRename = false;
   unsigned Flags = IsDef ? RegState::Define : 0;
   while (Token.isRegisterFlag()) {
-    if (parseRegisterFlag(Flags))
+    if (parseRegisterFlag(Flags, NoRename))
       return true;
   }
   if (!Token.isRegister())
@@ -1213,6 +1217,13 @@
       Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
       Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
       Flags & RegState::InternalRead);
+
+  // Mark MIR regs as renamable unless they are explicitly marked norename.  We
+  // will later go back through and fix up all the physical regs to be marked as
+  // not renamable if we are reading a MIR file with NoVRegs not set (i.e. from
+  // before register allocation.
+  if (!NoRename)
+    Dest.setIsRenamable(true);
   return false;
 }
 
@@ -1868,6 +1879,7 @@
   case MIToken::kw_def:
   case MIToken::kw_dead:
   case MIToken::kw_killed:
+  case MIToken::kw_norename:
   case MIToken::kw_undef:
   case MIToken::kw_internal:
   case MIToken::kw_early_clobber:
Index: lib/CodeGen/MIRParser/MIRParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIRParser.cpp
+++ lib/CodeGen/MIRParser/MIRParser.cpp
@@ -417,6 +417,16 @@
 
   computeFunctionProperties(MF);
 
+  // Fix up physical registers to be marked as norename if we are reading a
+  // MIR file with NoVRegs not set (i.e. from before register allocation).
+  if (!MF.getProperties().hasProperty(
+          MachineFunctionProperties::Property::NoVRegs))
+    for (auto &MBB : MF)
+      for (auto &MI : MBB.instrs())
+        for (auto &MO : MI.operands())
+          if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
+            MO.setIsRenamable(false);
+
   MF.verify();
   return false;
 }
Index: lib/CodeGen/MIRPrinter.cpp
===================================================================
--- lib/CodeGen/MIRPrinter.cpp
+++ lib/CodeGen/MIRPrinter.cpp
@@ -112,9 +112,10 @@
   /// Maps from stack object indices to operand indices which will be used when
   /// printing frame index machine operands.
   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
+  bool ShouldPrintIsRenamable;
 
 public:
-  MIRPrinter(raw_ostream &OS) : OS(OS) {}
+  MIRPrinter(raw_ostream &OS) : OS(OS), ShouldPrintIsRenamable(false) {}
 
   void print(const MachineFunction &MF);
 
@@ -142,6 +143,7 @@
   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
   /// Synchronization scope names registered with LLVMContext.
   SmallVector<StringRef, 8> SSNs;
+  bool ShouldPrintIsRenamable;
 
   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
@@ -149,9 +151,11 @@
 public:
   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
-            const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
+            const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping,
+            bool ShouldPrintIsRenamable)
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
-        StackObjectOperandMapping(StackObjectOperandMapping) {}
+        StackObjectOperandMapping(StackObjectOperandMapping),
+        ShouldPrintIsRenamable(ShouldPrintIsRenamable) {}
 
   void print(const MachineBasicBlock &MBB);
 
@@ -225,6 +229,8 @@
       MachineFunctionProperties::Property::RegBankSelected);
   YamlMF.Selected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Selected);
+  ShouldPrintIsRenamable = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::NoVRegs);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   ModuleSlotTracker MST(MF.getFunction()->getParent());
@@ -240,7 +246,8 @@
   for (const auto &MBB : MF) {
     if (IsNewlineNeeded)
       StrOS << "\n";
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .print(MBB);
     IsNewlineNeeded = true;
   }
@@ -350,12 +357,14 @@
   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
   if (MFI.getSavePoint()) {
     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printMBBReference(*MFI.getSavePoint());
   }
   if (MFI.getRestorePoint()) {
     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printMBBReference(*MFI.getRestorePoint());
   }
 }
@@ -444,7 +453,8 @@
   // converting the stack objects.
   if (MFI.hasStackProtectorIndex()) {
     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+              ShouldPrintIsRenamable)
         .printStackObjectReference(MFI.getStackProtectorIndex());
   }
 
@@ -505,7 +515,8 @@
     Entry.ID = ID++;
     for (const auto *MBB : Table.MBBs) {
       raw_string_ostream StrOS(Str);
-      MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+      MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping,
+                ShouldPrintIsRenamable)
           .printMBBReference(*MBB);
       Entry.Blocks.push_back(StrOS.str());
       Str.clear();
@@ -941,6 +952,8 @@
       OS << "dead ";
     if (Op.isKill())
       OS << "killed ";
+    if (ShouldPrintIsRenamable && !Op.isRenamable())
+      OS << "norename ";
     if (Op.isUndef())
       OS << "undef ";
     if (Op.isEarlyClobber())
Index: lib/CodeGen/MachineInstr.cpp
===================================================================
--- lib/CodeGen/MachineInstr.cpp
+++ lib/CodeGen/MachineInstr.cpp
@@ -87,6 +87,8 @@
 void MachineOperand::setReg(unsigned Reg) {
   if (getReg() == Reg) return; // No change.
 
+  IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
+
   // Otherwise, we have to change the register.  If this operand is embedded
   // into a machine function, we need to update the old and new register's
   // use/def lists.
@@ -104,6 +106,12 @@
   SmallContents.RegNo = Reg;
 }
 
+void MachineOperand::setRegKeepRenamable(unsigned Reg) {
+  bool SaveIsRenamable = IsRenamable;
+  setReg(Reg);
+  IsRenamable = SaveIsRenamable;
+}
+
 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
                                   const TargetRegisterInfo &TRI) {
   assert(TargetRegisterInfo::isVirtualRegister(Reg));
@@ -133,6 +141,8 @@
   assert((!Val || !isDebug()) && "Marking a debug operation as def");
   if (IsDef == Val)
     return;
+  assert(!IsDeadOrKill && "Changing operand from def to use or vice-versa "
+                          "destroys IsDead/IsKill setting");
   // MRI may keep uses and defs in different list positions.
   if (MachineInstr *MI = getParent())
     if (MachineBasicBlock *MBB = MI->getParent())
@@ -244,13 +254,15 @@
     RegInfo->removeRegOperandFromUseList(this);
 
   // Change this to a register and set the reg#.
+  assert(!(isDead && !isDef) && "Dead flag on non-def");
+  assert(!(isKill && isDef) && "Kill flag on def");
   OpKind = MO_Register;
   SmallContents.RegNo = Reg;
   SubReg_TargetFlags = 0;
   IsDef = isDef;
   IsImp = isImp;
-  IsKill = isKill;
-  IsDead = isDead;
+  IsDeadOrKill = isKill | isDead;
+  IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
   IsUndef = isUndef;
   IsInternalRead = false;
   IsEarlyClobber = false;
@@ -267,6 +279,29 @@
     RegInfo->addRegOperandToUseList(this);
 }
 
+MachineOperand MachineOperand::CreateReg(unsigned Reg, bool isDef, bool isImp,
+                                         bool isKill, bool isDead, bool isUndef,
+                                         bool isEarlyClobber, unsigned SubReg,
+                                         bool isDebug, bool isInternalRead) {
+  assert(!(isDead && !isDef) && "Dead flag on non-def");
+  assert(!(isKill && isDef) && "Kill flag on def");
+  MachineOperand Op(MachineOperand::MO_Register);
+  Op.IsDef = isDef;
+  Op.IsImp = isImp;
+  Op.IsDeadOrKill = isKill | isDead;
+  Op.IsRenamable = !TargetRegisterInfo::isPhysicalRegister(Reg);
+  Op.IsUndef = isUndef;
+  Op.IsInternalRead = isInternalRead;
+  Op.IsEarlyClobber = isEarlyClobber;
+  Op.TiedTo = 0;
+  Op.IsDebug = isDebug;
+  Op.SmallContents.RegNo = Reg;
+  Op.Contents.Reg.Prev = nullptr;
+  Op.Contents.Reg.Next = nullptr;
+  Op.setSubReg(SubReg);
+  return Op;
+}
+
 /// isIdenticalTo - Return true if this operand is identical to the specified
 /// operand. Note that this should stay in sync with the hash_value overload
 /// below.
@@ -394,7 +429,7 @@
     OS << PrintReg(getReg(), TRI, getSubReg());
 
     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
-        isInternalRead() || isEarlyClobber() || isTied()) {
+        isInternalRead() || isEarlyClobber() || isTied() || !isRenamable()) {
       OS << '<';
       bool NeedComma = false;
       if (isDef()) {
@@ -424,6 +459,11 @@
         OS << "dead";
         NeedComma = true;
       }
+      if (!isRenamable()) {
+        if (NeedComma) OS << ',';
+        OS << "norename";
+        NeedComma = true;
+      }
       if (isUndef() && isUse()) {
         if (NeedComma) OS << ',';
         OS << "undef";
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -101,6 +101,7 @@
     // Avoid querying the MachineFunctionProperties for each operand.
     bool isFunctionRegBankSelected;
     bool isFunctionSelected;
+    bool areRegsAllocated;
 
     using RegVector = SmallVector<unsigned, 16>;
     using RegMaskVector = SmallVector<const uint32_t *, 4>;
@@ -344,9 +345,7 @@
   // If a pass has introduced virtual registers without clearing the
   // NoVRegs property (or set it without allocating the vregs)
   // then report an error.
-  if (MF.getProperties().hasProperty(
-          MachineFunctionProperties::Property::NoVRegs) &&
-      MRI->getNumVirtRegs())
+  if (areRegsAllocated && MRI->getNumVirtRegs())
     report("Function has NoVRegs property but there are VReg operands", &MF);
 }
 
@@ -363,6 +362,8 @@
       MachineFunctionProperties::Property::RegBankSelected);
   isFunctionSelected = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::Selected);
+  areRegsAllocated = MF.getProperties().hasProperty(
+      MachineFunctionProperties::Property::NoVRegs);
 
   LiveVars = nullptr;
   LiveInts = nullptr;
@@ -1204,6 +1205,14 @@
         }
       }
     }
+
+    // Check isRenamable is correct if we're before RA.
+    if (!areRegsAllocated)
+      if (MO->isRenamable() != TargetRegisterInfo::isVirtualRegister(Reg))
+        report("Virtual registers should be marked isRenamable and physical "
+               "registers should not be.",
+               MO, MONum);
+
     break;
   }
 
Index: lib/CodeGen/RegAllocFast.cpp
===================================================================
--- lib/CodeGen/RegAllocFast.cpp
+++ lib/CodeGen/RegAllocFast.cpp
@@ -698,12 +698,12 @@
   MachineOperand &MO = MI.getOperand(OpNum);
   bool Dead = MO.isDead();
   if (!MO.getSubReg()) {
-    MO.setReg(PhysReg);
+    MO.setRegKeepRenamable(PhysReg);
     return MO.isKill() || Dead;
   }
 
   // Handle subregister index.
-  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
+  MO.setRegKeepRenamable(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
   MO.setSubReg(0);
 
   // A kill flag implies killing the full register. Add corresponding super
Index: lib/CodeGen/VirtRegMap.cpp
===================================================================
--- lib/CodeGen/VirtRegMap.cpp
+++ lib/CodeGen/VirtRegMap.cpp
@@ -529,7 +529,7 @@
         }
         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
         // we need the inlining here.
-        MO.setReg(PhysReg);
+        MO.setRegKeepRenamable(PhysReg);
       }
 
       // Add any missing super-register kills after rewriting the whole
Index: test/CodeGen/AArch64/arm64-csldst-mmo.ll
===================================================================
--- test/CodeGen/AArch64/arm64-csldst-mmo.ll
+++ test/CodeGen/AArch64/arm64-csldst-mmo.ll
@@ -11,7 +11,7 @@
 ; CHECK: Before post-MI-sched:
 ; CHECK-LABEL: # Machine code for function test1:
 ; CHECK: SU(2):   STRWui %WZR
-; CHECK: SU(3):   %X21<def>, %X20<def> = LDPXi %SP
+; CHECK: SU(3):   %X21<def,norename>, %X20<def,norename> = LDPXi %SP
 ; CHECK:  Predecessors:
 ; CHECK-NEXT:   SU(0): Out
 ; CHECK-NEXT:   SU(0): Out
Index: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
===================================================================
--- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -9,11 +9,11 @@
 ; CHECK:   Successors:
 ; CHECK-NEXT:    SU(5): Data Latency=4 Reg=%vreg2
 ; CHECK-NEXT:    SU(4): Ord  Latency=0
-; CHECK: SU(3):   STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
+; CHECK: SU(3):   STRWui %WZR<norename>, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
 ; CHECK:   Successors:
 ; CHECK: SU(4): Ord  Latency=0
-; CHECK: SU(4):   STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
-; CHECK: SU(5):   %W0<def> = COPY %vreg2; GPR32:%vreg2
+; CHECK: SU(4):   STRWui %WZR<norename>, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
+; CHECK: SU(5):   %W0<def,norename> = COPY %vreg2; GPR32:%vreg2
 ; CHECK: ** ScheduleDAGMI::schedule picking next node
 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
 entry:
Index: test/CodeGen/AArch64/arm64-misched-multimmo.ll
===================================================================
--- test/CodeGen/AArch64/arm64-misched-multimmo.ll
+++ test/CodeGen/AArch64/arm64-misched-multimmo.ll
@@ -12,7 +12,7 @@
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)
 ; CHECK: SU(3)
-; CHECK: SU(4):   STRWui %WZR, %X{{[0-9]+}}
+; CHECK: SU(4):   STRWui %WZR<norename>, %X{{[0-9]+}}
 define i32 @foo() {
 entry:
   %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
Index: test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
===================================================================
--- test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
+++ test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
@@ -4,7 +4,7 @@
 define void @vst(i8* %m, [4 x i64] %v) {
 entry:
 ; CHECK: vst:
-; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill>
+; CHECK: VST1d64Q %R{{[0-9]+}}<kill>, 8, %D{{[0-9]+}}<norename>, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,kill,norename>
 
   %v0 = extractvalue [4 x i64] %v, 0
   %v1 = extractvalue [4 x i64] %v, 1
@@ -37,7 +37,7 @@
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
 ; CHECK: vtbx4:
-; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use>
+; CHECK: VTBX4 {{.*}}, pred:14, pred:%noreg, %Q{{[0-9]+}}_Q{{[0-9]+}}<imp-use,norename>
 	%tmp1 = load <8 x i8>, <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x4_t, %struct.__neon_int8x8x4_t* %B
         %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0
Index: test/CodeGen/ARM/Windows/vla-cpsr.ll
===================================================================
--- test/CodeGen/ARM/Windows/vla-cpsr.ll
+++ test/CodeGen/ARM/Windows/vla-cpsr.ll
@@ -9,5 +9,5 @@
   ret void
 }
 
-; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def>, %SP<imp-use>, %R4<imp-use,kill>, %R4<imp-def>, %R12<imp-def,dead>, %CPSR<imp-def,dead>
+; CHECK: tBL pred:14, pred:%noreg, <es:__chkstk>, %LR<imp-def,norename>, %SP<imp-use,norename>, %R4<imp-use,kill,norename>, %R4<imp-def,norename>, %R12<imp-def,dead,norename>, %CPSR<imp-def,dead,norename>
 
Index: test/CodeGen/PowerPC/byval-agg-info.ll
===================================================================
--- test/CodeGen/PowerPC/byval-agg-info.ll
+++ test/CodeGen/PowerPC/byval-agg-info.ll
@@ -13,5 +13,5 @@
 
 ; Make sure that the MMO on the store has no offset from the byval
 ; variable itself (we used to have mem:ST8[%v+64]).
-; CHECK: STD %X5<kill>, 176, %X1; mem:ST8[%v](align=16)
+; CHECK: STD %X5<kill>, 176, %X1<norename>; mem:ST8[%v](align=16)
 
Index: test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
===================================================================
--- test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -6,11 +6,11 @@
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead,norename>;
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,norename>;
 ; CHECK: COPY %CR0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
@@ -25,7 +25,7 @@
 
 ; CHECK-LABEL: fn2
 define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def>;
+; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, %CR0<imp-def,norename>;
 ; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
 ; CHECK: BCC 12, [[CREG]]<kill>
   %1 = or i64 %b, %a
@@ -41,7 +41,7 @@
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def>;
+; CHECK: ANDIo {{[^, ]+}}, 10, %CR0<imp-def,norename>;
 ; CHECK: [[CREG:[^, ]+]]<def> = COPY %CR0
 ; CHECK: BCC 76, [[CREG]]<kill>
   %1 = and i32 %a, 10
Index: test/CodeGen/PowerPC/quadint-return.ll
===================================================================
--- test/CodeGen/PowerPC/quadint-return.ll
+++ test/CodeGen/PowerPC/quadint-return.ll
@@ -14,6 +14,6 @@
 
 ; CHECK: ********** Function: foo
 ; CHECK: ********** FAST REGISTER ALLOCATION **********
-; CHECK: %X3<def> = COPY %vreg
-; CHECK-NEXT: %X4<def> = COPY %vreg
+; CHECK: %X3<def,norename> = COPY %vreg
+; CHECK-NEXT: %X4<def,norename> = COPY %vreg
 ; CHECK-NEXT: BLR
Index: test/CodeGen/X86/misched-copy.ll
===================================================================
--- test/CodeGen/X86/misched-copy.ll
+++ test/CodeGen/X86/misched-copy.ll
@@ -9,8 +9,8 @@
 ; MUL_HiLo PhysReg def copies should be just below the mul.
 ;
 ; CHECK: *** Final schedule for BB#1 ***
-; CHECK:      %EAX<def> = COPY
-; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
+; CHECK:      %EAX<def,norename> = COPY
+; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def,norename>, %EDX<imp-def,norename>, %EFLAGS<imp-def,dead,norename>, %EAX<imp-use,norename>;
 ; CHECK-NEXT: COPY %E{{[AD]}}X
 ; CHECK-NEXT: COPY %E{{[AD]}}X
 ; CHECK:      DIVSSrm
Index: test/CodeGen/X86/pr28560.ll
===================================================================
--- test/CodeGen/X86/pr28560.ll
+++ test/CodeGen/X86/pr28560.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=i686-pc-linux -print-after=postrapseudos < %s 2>&1 | FileCheck %s
 
-; CHECK: MOV8rr %{{[A-D]}}L, %E[[R:[A-D]]]X<imp-use,kill>, %E[[R]]X<imp-def>
+; CHECK: MOV8rr %{{[A-D]}}L<norename>, %E[[R:[A-D]]]X<imp-use,kill,norename>, %E[[R]]X<imp-def,norename>
 define i32 @foo(i32 %i, i32 %k, i8* %p) {
   %f = icmp ne i32 %i, %k
   %s = zext i1 %f to i8
Index: test/CodeGen/X86/remat-phys-dead.ll
===================================================================
--- test/CodeGen/X86/remat-phys-dead.ll
+++ test/CodeGen/X86/remat-phys-dead.ll
@@ -9,7 +9,7 @@
 define i8 @test_remat() {
   ret i8 0
 ; CHECK: REGISTER COALESCING
-; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
+; CHECK: Remat: %EAX<def,dead,norename> = MOV32r0 %EFLAGS<imp-def,dead,norename>, %AL<imp-def,norename>
 }
 
 ; On the other hand, if it's already the correct width, we really shouldn't be
@@ -18,6 +18,6 @@
 define i32 @test_remat32() {
   ret i32 0
 ; CHECK: REGISTER COALESCING
-; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
+; CHECK: Remat: %EAX<def,norename> = MOV32r0 %EFLAGS<imp-def,dead,norename>
 }