Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -118,6 +118,9 @@ MipsAsmParser::OperandMatchResultTy ParseLSAImm(SmallVectorImpl &Operands); + MipsAsmParser::OperandMatchResultTy + ParsePCRelImm(SmallVectorImpl &Operands); + bool searchSymbolAlias(SmallVectorImpl &Operands); bool ParseOperand(SmallVectorImpl &, @@ -1955,6 +1958,27 @@ return MatchOperand_Success; } +MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParsePCRelImm( + SmallVectorImpl &Operands) { + DEBUG(dbgs() << "ParsePCRelImm\n"); + + SMLoc S = getLexer().getLoc(); + + // Integers and expressions are acceptable + OperandMatchResultTy ResTy = ParseImm(Operands); + if (ResTy != MatchOperand_NoMatch) + return ResTy; + + const MCExpr *Expr = nullptr; + if (Parser.parseExpression(Expr)) { + // We have no way of knowing if a symbol was consumed so we must ParseFail + return MatchOperand_ParseFail; + } + Operands.push_back( + MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this)); + return MatchOperand_Success; +} + MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) { MCSymbolRefExpr::VariantKind VK = Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -102,6 +102,13 @@ if (!isIntN(16, Value) && Ctx) Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup"); break; + case Mips::fixup_Mips_PC19_S2: + // Forcing a signed division because Value can be negative. + Value = (int64_t)Value / 4; + // We now check if Value can be encoded as a 19-bit signed immediate. + if (!isIntN(19, Value) && Ctx) + Ctx->FatalError(Fixup.getLoc(), "out of range PC19 fixup"); + break; } return Value; @@ -229,6 +236,7 @@ { "fixup_Mips_GOT_LO16", 0, 16, 0 }, { "fixup_Mips_CALL_HI16", 0, 16, 0 }, { "fixup_Mips_CALL_LO16", 0, 16, 0 }, + { "fixup_Mips_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, { "fixup_MICROMIPS_HI16", 0, 16, 0 }, { "fixup_MICROMIPS_LO16", 0, 16, 0 }, Index: lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -193,6 +193,9 @@ case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: Type = ELF::R_MICROMIPS_TLS_TPREL_LO16; break; + case Mips::fixup_Mips_PC19_S2: + Type = ELF::R_MIPS_PC19_S2; + break; } return Type; } Index: lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h +++ lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h @@ -128,6 +128,9 @@ // resulting in - R_MIPS_CALL_LO16 fixup_Mips_CALL_LO16, + // resulting in - R_MIPS_PC19_S2 + fixup_Mips_PC19_S2, + // resulting in - R_MICROMIPS_26_S1 fixup_MICROMIPS_26_S1, Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -611,11 +611,21 @@ MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - assert(MI.getOperand(OpNo).isImm()); - // The immediate is encoded as 'immediate << 2'. - unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); - assert((Res & 3) == 0); - return Res >> 2; + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + // The immediate is encoded as 'immediate << 2'. + unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); + assert((Res & 3) == 0); + return Res >> 2; + } + + assert(MO.isExpr() && + "getSimm19Lsl2Encoding expects only expressions or an immediate"); + + const MCExpr *Expr = MO.getExpr(); + Fixups.push_back(MCFixup::Create(0, Expr, + MCFixupKind(Mips::fixup_Mips_PC19_S2))); + return 0; } #include "MipsGenMCCodeEmitter.inc" Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -316,9 +316,17 @@ let DecoderMethod= "DecodeSimm16"; } +def MipsPCRelImmOperand : AsmOperandClass { + let Name = "PCRelImm"; + let ParserMethod = "ParsePCRelImm"; + let PredicateMethod = "isImm"; + let RenderMethod = "addImmOperands"; +} + def simm19_lsl2 : Operand { let EncoderMethod = "getSimm19Lsl2Encoding"; let DecoderMethod = "DecodeSimm19Lsl2"; + let ParserMatchClass = MipsPCRelImmOperand; } def simm20 : Operand { Index: test/MC/Mips/mips32r6/relocations.s =================================================================== --- /dev/null +++ test/MC/Mips/mips32r6/relocations.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r6 | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \ +# RUN: -mcpu=mips32r6 | llvm-readobj -r \ +# RUN: | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax +# for relocations. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: addiupc $2, bar # encoding: [A,A,0b01000AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +# CHECK-FIXUP: lwpc $2, bar # encoding: [A,A,0b01001AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +# CHECK-FIXUP: lwupc $2, bar # encoding: [A,A,0b01010AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: ] + + addiupc $2,bar + lwpc $2,bar + lwupc $2,bar + Index: test/MC/Mips/mips64r6/relocations.s =================================================================== --- /dev/null +++ test/MC/Mips/mips64r6/relocations.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \ +# RUN: -mcpu=mips64r6 | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \ +# RUN: -mcpu=mips64r6 | llvm-readobj -r \ +# RUN: | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax +# for relocations. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: addiupc $2, bar # encoding: [A,A,0b01000AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +# CHECK-FIXUP: lwpc $2, bar # encoding: [A,A,0b01001AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +# CHECK-FIXUP: lwupc $2, bar # encoding: [A,A,0b01010AAA,0xec] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC19_S2 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: ] + + addiupc $2,bar + lwpc $2,bar + lwupc $2,bar +