[WebAssembly] Add target feature for atomics

[dschuff]

Summary

This tracks the WebAssembly threads feature proposal at
https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md

This change simply add the target feature and basic support for a single instruction i32.atomic.load.

[dschuff]

• revert extra change

[jgravelle-google]

Nits aside lgtm

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

15 ↗

(On Diff #113274)

Should this surround the //==--- Atomic loads ---===// header? Looks odd to me that it starts outside it, but ends inside it.

test/CodeGen/WebAssembly/atomics.ll

16 ↗

(On Diff #113274)

This would probably be easier to read as @load_i32_atomic or something, especially as we get more atomic operations.

[dschuff]

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

15 ↗

(On Diff #113274)

Should probably be after the header it since it only applies to the instruction defs, but i guess the header refers to the patterns too.

[dschuff]

• address review comments

llvm/trunk/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

case WebAssembly::STORE16_I64:
     return 1;
   case WebAssembly::LOAD_I32:
   case WebAssembly::LOAD_F32:
   case WebAssembly::STORE_I32:
   case WebAssembly::STORE_F32:
   case WebAssembly::LOAD32_S_I64:
   case WebAssembly::LOAD32_U_I64:
   case WebAssembly::STORE32_I64:
+  case WebAssembly::ATOMIC_LOAD_I32:
     return 2;
   case WebAssembly::LOAD_I64:
   case WebAssembly::LOAD_F64:
   case WebAssembly::STORE_I64:
   case WebAssembly::STORE_F64:
     return 3;
   default:
     llvm_unreachable("Only loads and stores have p2align values");

llvm/trunk/lib/Target/WebAssembly/WebAssembly.td

 include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Subtarget features.
 //===----------------------------------------------------------------------===//
 
 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
                                       "Enable 128-bit SIMD">;
+def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
+                                      "Enable Atomics">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

 
 // Minimal Viable Product.
 def : ProcessorModel<"mvp", NoSchedModel, []>;
 
 // Generic processor: latest stable version.
 def : ProcessorModel<"generic", NoSchedModel, []>;
 
 // Latest and greatest experimental version of WebAssembly. Bugs included!
-def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
+def : ProcessorModel<"bleeding-edge", NoSchedModel,
+                      [FeatureSIMD128, FeatureAtomics]>;
 
 //===----------------------------------------------------------------------===//
 // Target Declaration
 //===----------------------------------------------------------------------===//
 
 def WebAssembly : Target {
   let InstructionSet = WebAssemblyInstrInfo;
 }

llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

WebAssemblyTargetLowering::WebAssemblyTargetLowering(
   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
   for (auto T : MVT::integer_valuetypes())
     for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
       setLoadExtAction(Ext, T, MVT::i1, Promote);
 
   // Trap lowers to wasm unreachable
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
+
+  setMaxAtomicSizeInBitsSupported(64);
 }
 
 FastISel *WebAssemblyTargetLowering::createFastISel(
     FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
   return WebAssembly::createFastISel(FuncInfo, LibInfo);
 }
 
 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

 // WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*-
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief WebAssembly Atomic operand code-gen constructs.
 ///
 //===----------------------------------------------------------------------===//
 
-// TODO: Implement atomic instructions.
-
-//===----------------------------------------------------------------------===//
-// Atomic fences
-//===----------------------------------------------------------------------===//
-
-// TODO: add atomic fences here...
-
 //===----------------------------------------------------------------------===//
 // Atomic loads
 //===----------------------------------------------------------------------===//
 
-// TODO: add atomic loads here...
+let Defs = [ARGUMENTS] in {
+// TODO: add the rest of the atomic loads
+// TODO: factor out 0xfe atomic prefix?
+def ATOMIC_LOAD_I32 : ATOMIC_I<(outs I32:$dst),
+                        (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
+                        [], "i32.atomic.load\t$dst, ${off}(${addr})${p2align}",
+                        0xfe10>;
+} // Defs = [ARGUMENTS]
+
+// Select loads with no constant offset.
+let Predicates = [HasAtomics] in {
+def : Pat<(i32 (atomic_load I32:$addr)), (ATOMIC_LOAD_I32 0, 0, $addr)>;
+}
 
 //===----------------------------------------------------------------------===//
 // Atomic stores
 //===----------------------------------------------------------------------===//
 
 // TODO: add atomic stores here...
 
 //===----------------------------------------------------------------------===//
 // Low-level exclusive operations
 //===----------------------------------------------------------------------===//
 
 // TODO: add exclusive operations here...
 
 // Load-exclusives.
 
 // Store-exclusives.
 
 // Store-release-exclusives.
 
 // And clear exclusive.
+

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrFormats.td

class I<dag oops, dag iops, list<dag> pattern, string asmstr = "", bits<32> inst = -1>
   dag InOperandList  = iops;
   let Pattern        = pattern;
 }
 
 class SIMD_I<dag oops, dag iops, list<dag> pattern,
              string asmstr = "", bits<32> inst = -1>
     : I<oops, iops, pattern, asmstr, inst>, Requires<[HasSIMD128]>;
 
+class ATOMIC_I<dag oops, dag iops, list<dag> pattern,
+               string asmstr = "", bits<32> inst = -1>
+    : I<oops, iops, pattern, asmstr, inst>, Requires<[HasAtomics]>;
+
 // Unary and binary instructions, for the local types that WebAssembly supports.
 multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst, bits<32> i64Inst> {
   def _I32 : I<(outs I32:$dst), (ins I32:$src),
                [(set I32:$dst, (node I32:$src))],
                !strconcat("i32.", !strconcat(name, "\t$dst, $src")), i32Inst>;
   def _I64 : I<(outs I64:$dst), (ins I64:$src),
                [(set I64:$dst, (node I64:$src))],
                !strconcat("i64.", !strconcat(name, "\t$dst, $src")), i64Inst>;

llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

 //===----------------------------------------------------------------------===//
 // WebAssembly Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
 
 def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
 def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
 def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
                            AssemblerPredicate<"FeatureSIMD128", "simd128">;
+def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
+                           AssemblerPredicate<"FeatureAtomics", "atomics">;
 
 //===----------------------------------------------------------------------===//
 // WebAssembly-specific DAG Node Types.
 //===----------------------------------------------------------------------===//
 
 def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
                                                   SDTCisVT<1, iPTR>]>;
 def SDT_WebAssemblyCallSeqEnd :

llvm/trunk/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp

for (auto &MI : MBB) {
       case WebAssembly::LOAD16_S_I32:
       case WebAssembly::LOAD16_U_I32:
       case WebAssembly::LOAD8_S_I64:
       case WebAssembly::LOAD8_U_I64:
       case WebAssembly::LOAD16_S_I64:
       case WebAssembly::LOAD16_U_I64:
       case WebAssembly::LOAD32_S_I64:
       case WebAssembly::LOAD32_U_I64:
+      case WebAssembly::ATOMIC_LOAD_I32:
         RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo);
         break;
       case WebAssembly::STORE_I32:
       case WebAssembly::STORE_I64:
       case WebAssembly::STORE_F32:
       case WebAssembly::STORE_F64:
       case WebAssembly::STORE8_I32:
       case WebAssembly::STORE16_I32:

llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.h

 
 #define GET_SUBTARGETINFO_HEADER
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 namespace llvm {
 
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
   bool HasSIMD128;
+  bool HasAtomics;
 
   /// String name of used CPU.
   std::string CPUString;
 
   /// What processor and OS we're targeting.
   Triple TargetTriple;
 
   WebAssemblyFrameLowering FrameLowering;
public:
   }
   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableMachineScheduler() const override;
   bool useAA() const override;
 
   // Predicates used by WebAssemblyInstrInfo.td.
   bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
   bool hasSIMD128() const { return HasSIMD128; }
+  bool hasAtomics() const { return HasAtomics; }
 
   /// Parses features string setting specified subtarget options. Definition of
   /// function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 };
 
 } // end namespace llvm
 
 #endif

llvm/trunk/lib/Target/WebAssembly/WebAssemblySubtarget.cpp

WebAssemblySubtarget::initializeSubtargetDependencies(StringRef FS) {
   return *this;
 }
 
 WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
                                            const std::string &CPU,
                                            const std::string &FS,
                                            const TargetMachine &TM)
     : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
-      CPUString(CPU), TargetTriple(TT), FrameLowering(),
+      HasAtomics(false), CPUString(CPU), TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
       TLInfo(TM, *this) {}
 
 bool WebAssemblySubtarget::enableMachineScheduler() const {
   // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
   // enableMachineSchedDefaultSched overridden, it appears to have an overall
   // negative effect for the kinds of register optimizations we're doing.
   return false;
 }
 
 bool WebAssemblySubtarget::useAA() const { return true; }

llvm/trunk/test/CodeGen/WebAssembly/atomics.ll

+; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt 
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -mattr=+atomics | FileCheck %s
+
+; Test that atomic loads are assembled properly.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-wasm"
+
+; CHECK-LABEL: load_i32_atomic:
+; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .result i32{{$}}
+; CHECK-NEXT: get_local $push[[L0:[0-9]+]]=, 0{{$}}
+; CHECK-NEXT: i32.atomic.load $push[[NUM:[0-9]+]]=, 0($pop[[L0]]){{$}}
+; CHECK-NEXT: return $pop[[NUM]]{{$}}
+
+define i32 @load_i32_atomic(i32 *%p) {
+  %v = load atomic i32, i32* %p seq_cst, align 4
+  ret i32 %v
+}