[AVX512] Use 256-bit extract instructions for extracting bits [255:128] from a 512-bit register

[craig.topper]

Summary

This enables the use of a smaller encoding by using a VEX instruction when possible.

[craig.topper]

Ping

[igorb]

LGTM

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
           (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
           (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
 def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 0))),
           (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm))>;
 def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 0))),
           (v16i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_xmm))>;
 
+// A 128-bit extract from bits [255:128] of a 512-bit vector should use a
+// smaller extract to enable EVEX->VEX.
+let Predicates = [NoVLX] in {
+def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
+          (v2i64 (VEXTRACTI128rr
+                  (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
+          (v2f64 (VEXTRACTF128rr
+                  (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
+          (v4i32 (VEXTRACTI128rr
+                  (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
+          (v4f32 (VEXTRACTF128rr
+                  (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
+          (v8i16 (VEXTRACTI128rr
+                  (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
+          (v16i8 (VEXTRACTI128rr
+                  (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+}
+
+// A 128-bit extract from bits [255:128] of a 512-bit vector should use a
+// smaller extract to enable EVEX->VEX.
+let Predicates = [HasVLX] in {
+def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))),
+          (v2i64 (VEXTRACTI32x4Z256rr
+                  (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 2))),
+          (v2f64 (VEXTRACTF32x4Z256rr
+                  (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
+          (v4i32 (VEXTRACTI32x4Z256rr
+                  (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
+          (v4f32 (VEXTRACTF32x4Z256rr
+                  (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v8i16 (extract_subvector (v32i16 VR512:$src), (iPTR 8))),
+          (v8i16 (VEXTRACTI32x4Z256rr
+                  (v16i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+def : Pat<(v16i8 (extract_subvector (v64i8 VR512:$src), (iPTR 16))),
+          (v16i8 (VEXTRACTI32x4Z256rr
+                  (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
+                  (iPTR 1)))>;
+}
+
 // A 256-bit subvector extract from the first 256-bit vector position
 // is a subregister copy that needs no instruction.
 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
           (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
           (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
           (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;

llvm/trunk/test/CodeGen/X86/avx512-cvt.ll

 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; NODQ-NEXT:    vextracti32x4 $2, %zmm0, %xmm2
 ; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
 ; NODQ-NEXT:    vcvtsi2sdq %rax, %xmm3, %xmm3
 ; NODQ-NEXT:    vmovq %xmm2, %rax
 ; NODQ-NEXT:    vcvtsi2sdq %rax, %xmm4, %xmm2
 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; NODQ-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
-; NODQ-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NODQ-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
 ; NODQ-NEXT:    vcvtsi2sdq %rax, %xmm4, %xmm3
 ; NODQ-NEXT:    vmovq %xmm2, %rax
 ; NODQ-NEXT:    vcvtsi2sdq %rax, %xmm4, %xmm2
 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; NODQ-NEXT:    vpextrq $1, %xmm0, %rax
 ; NODQ-NEXT:    vcvtsi2sdq %rax, %xmm4, %xmm3
 ; NODQ-NEXT:    vmovq %xmm0, %rax

 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
 ; NODQ-NEXT:    vextracti32x4 $2, %zmm0, %xmm2
 ; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
 ; NODQ-NEXT:    vcvtusi2sdq %rax, %xmm3, %xmm3
 ; NODQ-NEXT:    vmovq %xmm2, %rax
 ; NODQ-NEXT:    vcvtusi2sdq %rax, %xmm4, %xmm2
 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; NODQ-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
-; NODQ-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NODQ-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NODQ-NEXT:    vpextrq $1, %xmm2, %rax
 ; NODQ-NEXT:    vcvtusi2sdq %rax, %xmm4, %xmm3
 ; NODQ-NEXT:    vmovq %xmm2, %rax
 ; NODQ-NEXT:    vcvtusi2sdq %rax, %xmm4, %xmm2
 ; NODQ-NEXT:    vunpcklpd {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; NODQ-NEXT:    vpextrq $1, %xmm0, %rax
 ; NODQ-NEXT:    vcvtusi2sdq %rax, %xmm4, %xmm3
 ; NODQ-NEXT:    vmovq %xmm0, %rax

llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll

; CHECK-NEXT:    ## -- End function
   %rrr2 = insertelement <8 x double> %x, double %rrr, i32 1
   %rrr3 = insertelement <8 x double> %rrr2, double %y, i32 6
   ret <8 x double> %rrr3
 }
 
 define <16 x float> @test3(<16 x float> %x) nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vextractf32x4 $1, %zmm0, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[2,3]
 ; CHECK-NEXT:    vinsertf32x4 $0, %xmm1, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
 ; CHECK-NEXT:    ## -- End function
   %eee = extractelement <16 x float> %x, i32 4
   %rrr2 = insertelement <16 x float> %x, float %eee, i32 1
   ret <16 x float> %rrr2
 }
; SKX-NEXT:    retq
   %x2 = bitcast <8 x i1>%x1 to i8
   ret i8 %x2
 }
 
 define i64 @extract_v8i64(<8 x i64> %x, i64* %dst) {
 ; KNL-LABEL: extract_v8i64:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpextrq $1, %xmm0, %rax
-; KNL-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpextrq $1, %xmm0, (%rdi)
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: extract_v8i64:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpextrq $1, %xmm0, %rax
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpextrq $1, %xmm0, (%rdi)
 ; SKX-NEXT:    vzeroupper
 ; SKX-NEXT:    retq
   %r1 = extractelement <8 x i64> %x, i32 1
   %r2 = extractelement <8 x i64> %x, i32 3
   store i64 %r2, i64* %dst, align 1
   ret i64 %r1
 }
; CHECK-NEXT:    retq
   store i64 %r2, i64* %dst, align 1
   ret i64 %r1
 }
 
 define i32 @extract_v16i32(<16 x i32> %x, i32* %dst) {
 ; KNL-LABEL: extract_v16i32:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpextrd $1, %xmm0, %eax
-; KNL-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpextrd $1, %xmm0, (%rdi)
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: extract_v16i32:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpextrd $1, %xmm0, %eax
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpextrd $1, %xmm0, (%rdi)
 ; SKX-NEXT:    vzeroupper
 ; SKX-NEXT:    retq
   %r1 = extractelement <16 x i32> %x, i32 1
   %r2 = extractelement <16 x i32> %x, i32 5
   store i32 %r2, i32* %dst, align 1
   ret i32 %r1
 }

 ; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpextrw $1, %xmm0, (%rdi)
 ; KNL-NEXT:    ## kill: %AX<def> %AX<kill> %EAX<kill>
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: extract_v32i16:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpextrw $1, %xmm0, %eax
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpextrw $1, %xmm0, (%rdi)
 ; SKX-NEXT:    ## kill: %AX<def> %AX<kill> %EAX<kill>
 ; SKX-NEXT:    vzeroupper
 ; SKX-NEXT:    retq
   %r1 = extractelement <32 x i16> %x, i32 1
   %r2 = extractelement <32 x i16> %x, i32 9
   store i16 %r2, i16* %dst, align 1
   ret i16 %r1

 ; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpextrb $1, %xmm0, (%rdi)
 ; KNL-NEXT:    ## kill: %AL<def> %AL<kill> %EAX<kill>
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: extract_v64i8:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpextrb $1, %xmm0, %eax
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpextrb $1, %xmm0, (%rdi)
 ; SKX-NEXT:    ## kill: %AL<def> %AL<kill> %EAX<kill>
 ; SKX-NEXT:    vzeroupper
 ; SKX-NEXT:    retq
   %r1 = extractelement <64 x i8> %x, i32 1
   %r2 = extractelement <64 x i8> %x, i32 17
   store i8 %r2, i8* %dst, align 1
   ret i8 %r1
; CHECK-NEXT:    retq
   ret i8 %r1
 }
 
 define <8 x i64> @insert_v8i64(<8 x i64> %x, i64 %y , i64* %ptr) {
 ; CHECK-LABEL: insert_v8i64:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpinsrq $1, (%rsi), %xmm0, %xmm1
 ; CHECK-NEXT:    vinserti32x4 $0, %xmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; CHECK-NEXT:    vpinsrq $1, %rdi, %xmm0, %xmm0
 ; CHECK-NEXT:    vinserti32x4 $1, %xmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %val = load i64, i64* %ptr
   %r1 = insertelement <8 x i64> %x, i64 %val, i32 1
   %r2 = insertelement <8 x i64> %r1, i64 %y, i32 3
   ret <8 x i64> %r2
 }
; CHECK-NEXT:    retq
   ret <2 x i64> %r2
 }
 
 define <16 x i32> @insert_v16i32(<16 x i32> %x, i32 %y, i32* %ptr) {
 ; CHECK-LABEL: insert_v16i32:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    vpinsrd $1, (%rsi), %xmm0, %xmm1
 ; CHECK-NEXT:    vinserti32x4 $0, %xmm1, %zmm0, %zmm1
-; CHECK-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; CHECK-NEXT:    vpinsrd $1, %edi, %xmm0, %xmm0
 ; CHECK-NEXT:    vinserti32x4 $1, %xmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %val = load i32, i32* %ptr
   %r1 = insertelement <16 x i32> %x, i32 %val, i32 1
   %r2 = insertelement <16 x i32> %r1, i32 %y, i32 5
   ret <16 x i32> %r2
 }

 ; KNL-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0
 ; KNL-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: insert_v32i16:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpinsrw $1, (%rsi), %xmm0, %xmm1
 ; SKX-NEXT:    vinserti32x4 $0, %xmm1, %zmm0, %zmm1
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpinsrw $1, %edi, %xmm0, %xmm0
 ; SKX-NEXT:    vinserti32x4 $1, %xmm0, %zmm1, %zmm0
 ; SKX-NEXT:    retq
   %val = load i16, i16* %ptr
   %r1 = insertelement <32 x i16> %x, i16 %val, i32 1
   %r2 = insertelement <32 x i16> %r1, i16 %y, i32 9
   ret <32 x i16> %r2
 }

llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll

 ; CHECK-NEXT:    kshiftlb $7, %k0, %k1
 ; CHECK-NEXT:    kshiftrb $7, %k1, %k1
 ; CHECK-NEXT:    kshiftlb $6, %k0, %k0
 ; CHECK-NEXT:    kshiftrb $7, %k0, %k0
 ; CHECK-NEXT:    kmovw %k0, %eax
 ; CHECK-NEXT:    kmovw %k1, %ecx
 ; CHECK-NEXT:    vmovd %ecx, %xmm2
 ; CHECK-NEXT:    vpinsrb $8, %eax, %xmm2, %xmm2
-; CHECK-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; CHECK-NEXT:    vpsllq $63, %xmm2, %xmm2
 ; CHECK-NEXT:    vpsraq $63, %zmm2, %zmm2
 ; CHECK-NEXT:    vblendvpd %xmm2, %xmm0, %xmm1, %xmm1
 ; CHECK-NEXT:    vandpd %xmm0, %xmm2, %xmm2
 ; CHECK-NEXT:    vaddpd %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vaddpd %xmm0, %xmm2, %xmm0
 ; CHECK-NEXT:    retq
   %res = call <2 x double> @llvm.x86.avx512.mask.vextractf64x2.512(<8 x double> %x0,i32 1, <2 x double> %x2, i8 %x3)

llvm/trunk/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi125:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi126:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NoVLX-NEXT:    vmovq %xmm2, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm3
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm3, %xmm3

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm5, %xmm0
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm6
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm6
 ; NoVLX-NEXT:    vmovq %xmm6, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm5
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm0
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi128:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi129:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm1
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; NoVLX-NEXT:    vmovq %xmm1, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm2
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm2, %xmm2

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm4, %xmm3
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm3, %xmm3
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm3, %xmm3
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm4
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm4
 ; NoVLX-NEXT:    vmovq %xmm4, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm5
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm5, %xmm5
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm7, %xmm6
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm6, %xmm6
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm6, %xmm6
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm7
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm7
 ; NoVLX-NEXT:    vmovq %xmm7, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm2
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm3, %xmm2
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm2, %xmm2
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm3
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm3
 ; NoVLX-NEXT:    vmovq %xmm3, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm4
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi507:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi508:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NoVLX-NEXT:    vmovq %xmm2, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm3
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm3, %xmm3

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm5, %xmm0
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm6
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm6
 ; NoVLX-NEXT:    vmovq %xmm6, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm5
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm0
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi510:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi511:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm1
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; NoVLX-NEXT:    vmovq %xmm1, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm2
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm2, %xmm2

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm4, %xmm3
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm3, %xmm3
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm3, %xmm3
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm4
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm4
 ; NoVLX-NEXT:    vmovq %xmm4, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm5
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm5, %xmm5
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm7, %xmm6
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm6, %xmm6
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm6, %xmm6
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm7
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm7
 ; NoVLX-NEXT:    vmovq %xmm7, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm2
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm3, %xmm2
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm2, %xmm2
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm3
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm3
 ; NoVLX-NEXT:    vmovq %xmm3, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm4
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi889:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi890:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NoVLX-NEXT:    vmovq %xmm2, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm3
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm3, %xmm3

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm4, %xmm4
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm4, %xmm4
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm4, %xmm4
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; NoVLX-NEXT:    vmovq %xmm5, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm6
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi892:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi893:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm1
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; NoVLX-NEXT:    vmovq %xmm1, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm2
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm2, %xmm2

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm2, %xmm2
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm3
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm3
 ; NoVLX-NEXT:    vmovq %xmm3, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm2, %xmm5
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm2
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm7, %xmm3
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm3, %xmm3
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm3, %xmm3
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm7
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm7
 ; NoVLX-NEXT:    vmovq %xmm7, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm2
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm3, %xmm2
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm2, %xmm2
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm3
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm3
 ; NoVLX-NEXT:    vmovq %xmm3, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm4
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi1271:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi1272:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; NoVLX-NEXT:    vmovq %xmm2, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm3
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    shrq $32, %rdx
 ; NoVLX-NEXT:    vpinsrw $2, %edx, %xmm3, %xmm3

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm5, %xmm0
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm0, %xmm0
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm6
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm6
 ; NoVLX-NEXT:    vmovq %xmm6, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm0, %xmm5
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm0
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm0, %xmm0
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    .cfi_def_cfa_offset 16
 ; NoVLX-NEXT:  .Lcfi1274:
 ; NoVLX-NEXT:    .cfi_offset %rbp, -16
 ; NoVLX-NEXT:    movq %rsp, %rbp
 ; NoVLX-NEXT:  .Lcfi1275:
 ; NoVLX-NEXT:    .cfi_def_cfa_register %rbp
 ; NoVLX-NEXT:    andq $-32, %rsp
 ; NoVLX-NEXT:    subq $64, %rsp
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm1
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; NoVLX-NEXT:    vmovq %xmm1, %rax
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    movq %rax, %rdx
 ; NoVLX-NEXT:    vmovd %eax, %xmm2
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpextrq $1, %xmm0, %rax
 ; NoVLX-NEXT:    shrq $32, %rdx

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm4, %xmm3
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm3, %xmm3
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm3, %xmm3
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm3, %xmm3
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm4
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm4
 ; NoVLX-NEXT:    vmovq %xmm4, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm3, %xmm9
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm5
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm5, %xmm5
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm7, %xmm6
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm6, %xmm6
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm6, %xmm6
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm1, %xmm7
+; NoVLX-NEXT:    vextracti128 $1, %ymm1, %xmm7
 ; NoVLX-NEXT:    vmovq %xmm7, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm6, %xmm6
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm2
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rcx, %rax

 ; NoVLX-NEXT:    vpinsrw $3, %ecx, %xmm3, %xmm2
 ; NoVLX-NEXT:    movl %eax, %ecx
 ; NoVLX-NEXT:    shrl $16, %ecx
 ; NoVLX-NEXT:    vpinsrw $4, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    vpinsrw $5, %ecx, %xmm2, %xmm2
 ; NoVLX-NEXT:    movq %rax, %rcx
 ; NoVLX-NEXT:    shrq $32, %rcx
 ; NoVLX-NEXT:    vpinsrw $6, %ecx, %xmm2, %xmm2
-; NoVLX-NEXT:    vextracti32x4 $1, %zmm0, %xmm3
+; NoVLX-NEXT:    vextracti128 $1, %ymm0, %xmm3
 ; NoVLX-NEXT:    vmovq %xmm3, %rcx
 ; NoVLX-NEXT:    shrq $48, %rax
 ; NoVLX-NEXT:    vpinsrw $7, %eax, %xmm2, %xmm2
 ; NoVLX-NEXT:    movl %ecx, %eax
 ; NoVLX-NEXT:    shrl $16, %eax
 ; NoVLX-NEXT:    vmovd %ecx, %xmm4
 ; NoVLX-NEXT:    vpinsrw $1, %eax, %xmm4, %xmm4
 ; NoVLX-NEXT:    movq %rcx, %rax

llvm/trunk/test/CodeGen/X86/pr29112.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f | FileCheck %s
 
 declare <4 x float> @foo(<4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>)
 
 ; Due to a bug in X86RegisterInfo::getLargestLegalSuperClass this test case was trying to use XMM16 and spill it without VLX support for the necessary store instruction. We briefly implemented the spill using VEXTRACTF32X4, but the bug in getLargestLegalSuperClass has now been fixed so we no longer use XMM16.
 
 define <4 x float> @bar(<4 x float>* %a1p, <4 x float>* %a2p, <4 x float> %a3, <4 x float> %a4, <16 x float>%c1, <16 x float>%c2) {
 ; CHECK-LABEL: bar:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    subq $88, %rsp
 ; CHECK-NEXT:  .Lcfi0:
 ; CHECK-NEXT:    .cfi_def_cfa_offset 96
 ; CHECK-NEXT:    vmovaps %xmm1, {{[0-9]+}}(%rsp) # 16-byte Spill
-; CHECK-NEXT:    vextractf32x4 $1, %zmm3, %xmm1
-; CHECK-NEXT:    vextractf32x4 $1, %zmm2, %xmm8
+; CHECK-NEXT:    vextractf128 $1, %ymm3, %xmm1
+; CHECK-NEXT:    vextractf128 $1, %ymm2, %xmm8
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm9 = xmm8[0],xmm1[0],xmm8[2,3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm0 = xmm9[0,1],xmm2[1],xmm9[3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm15 = xmm0[0,1,2],xmm3[1]
 ; CHECK-NEXT:    vblendps {{.*#+}} xmm4 = xmm8[0],xmm1[1],xmm8[2,3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm2[1],xmm4[3]
 ; CHECK-NEXT:    vinsertps {{.*#+}} xmm6 = xmm4[0,1,2],xmm3[1]
 ; CHECK-NEXT:    vmovaps %xmm6, {{[0-9]+}}(%rsp) # 16-byte Spill
 ; CHECK-NEXT:    vextractf32x4 $2, %zmm3, %xmm4

llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll

 ; AVX512F-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX512F-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm2
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512F-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm2
 ; AVX512F-NEXT:    vmovq %xmm0, %rax
 ; AVX512F-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm3
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX512F-NEXT:    vmovq %xmm0, %rax
 ; AVX512F-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm3
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512F-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm0
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
 ; AVX512F-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX512F-NEXT:    retq

 ; AVX512VL-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX512VL-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm2
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
 ; AVX512VL-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm2
 ; AVX512VL-NEXT:    vmovq %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm3
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
-; AVX512VL-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; AVX512VL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX512VL-NEXT:    vmovq %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm3
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
 ; AVX512VL-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtsi2ssq %rax, %xmm4, %xmm0
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
 ; AVX512VL-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX512VL-NEXT:    retq

 ; AVX512F-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX512F-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm2
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512F-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm2
 ; AVX512F-NEXT:    vmovq %xmm0, %rax
 ; AVX512F-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm3
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX512F-NEXT:    vmovq %xmm0, %rax
 ; AVX512F-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm3
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512F-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm0
 ; AVX512F-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
 ; AVX512F-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX512F-NEXT:    retq

 ; AVX512VL-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX512VL-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm2
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
 ; AVX512VL-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm2
 ; AVX512VL-NEXT:    vmovq %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm3
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
-; AVX512VL-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; AVX512VL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX512VL-NEXT:    vmovq %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm3
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
 ; AVX512VL-NEXT:    vpextrq $1, %xmm0, %rax
 ; AVX512VL-NEXT:    vcvtusi2ssq %rax, %xmm4, %xmm0
 ; AVX512VL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
 ; AVX512VL-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
 ; AVX512VL-NEXT:    retq

llvm/trunk/test/CodeGen/X86/vector-compare-results.ll

 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm6 = xmm6[1,0]
 ; AVX512-NEXT:    vucomisd %xmm5, %xmm6
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovaq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm5
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm5 = xmm7[0],xmm5[0]
 ; AVX512-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512-NEXT:    vextractf32x4 $1, %zmm2, %xmm5
-; AVX512-NEXT:    vextractf32x4 $1, %zmm0, %xmm6
+; AVX512-NEXT:    vextractf128 $1, %ymm2, %xmm5
+; AVX512-NEXT:    vextractf128 $1, %ymm0, %xmm6
 ; AVX512-NEXT:    vucomisd %xmm5, %xmm6
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovaq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm7
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm6 = xmm6[1,0]
 ; AVX512-NEXT:    vucomisd %xmm5, %xmm6
 ; AVX512-NEXT:    movl $0, %edx

 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovaq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm4
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm6[0],xmm4[0]
 ; AVX512-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512-NEXT:    vextractf32x4 $1, %zmm3, %xmm4
-; AVX512-NEXT:    vextractf32x4 $1, %zmm1, %xmm5
+; AVX512-NEXT:    vextractf128 $1, %ymm3, %xmm4
+; AVX512-NEXT:    vextractf128 $1, %ymm1, %xmm5
 ; AVX512-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovaq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm6
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512-NEXT:    movl $0, %edx

 ; AVX512F-NEXT:    vpinsrd $2, %edx, %xmm9, %xmm4
 ; AVX512F-NEXT:    vpermilps {{.*#+}} xmm5 = xmm5[3,1,2,3]
 ; AVX512F-NEXT:    vpermilps {{.*#+}} xmm6 = xmm7[3,1,2,3]
 ; AVX512F-NEXT:    vucomiss %xmm5, %xmm6
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmoval %ecx, %edx
 ; AVX512F-NEXT:    vpinsrd $3, %edx, %xmm4, %xmm4
 ; AVX512F-NEXT:    vinserti128 $1, %xmm8, %ymm4, %ymm8
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm2, %xmm5
+; AVX512F-NEXT:    vextractf128 $1, %ymm2, %xmm5
 ; AVX512F-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm0, %xmm7
+; AVX512F-NEXT:    vextractf128 $1, %ymm0, %xmm7
 ; AVX512F-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm7[1,1,3,3]
 ; AVX512F-NEXT:    vucomiss %xmm6, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmoval %ecx, %edx
 ; AVX512F-NEXT:    vucomiss %xmm5, %xmm7
 ; AVX512F-NEXT:    movl $0, %esi
 ; AVX512F-NEXT:    cmoval %ecx, %esi
 ; AVX512F-NEXT:    vmovd %esi, %xmm4

 ; AVX512F-NEXT:    vpinsrd $2, %edx, %xmm5, %xmm0
 ; AVX512F-NEXT:    vpermilps {{.*#+}} xmm4 = xmm4[3,1,2,3]
 ; AVX512F-NEXT:    vpermilps {{.*#+}} xmm5 = xmm6[3,1,2,3]
 ; AVX512F-NEXT:    vucomiss %xmm4, %xmm5
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmoval %ecx, %edx
 ; AVX512F-NEXT:    vpinsrd $3, %edx, %xmm0, %xmm0
 ; AVX512F-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm2
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm3, %xmm0
+; AVX512F-NEXT:    vextractf128 $1, %ymm3, %xmm0
 ; AVX512F-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm1, %xmm5
+; AVX512F-NEXT:    vextractf128 $1, %ymm1, %xmm5
 ; AVX512F-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
 ; AVX512F-NEXT:    vucomiss %xmm4, %xmm6
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmoval %ecx, %edx
 ; AVX512F-NEXT:    vucomiss %xmm0, %xmm5
 ; AVX512F-NEXT:    movl $0, %esi
 ; AVX512F-NEXT:    cmoval %ecx, %esi
 ; AVX512F-NEXT:    vmovd %esi, %xmm4

 ; AVX512DQ-NEXT:    vpinsrd $2, %edx, %xmm9, %xmm4
 ; AVX512DQ-NEXT:    vpermilps {{.*#+}} xmm5 = xmm5[3,1,2,3]
 ; AVX512DQ-NEXT:    vpermilps {{.*#+}} xmm6 = xmm7[3,1,2,3]
 ; AVX512DQ-NEXT:    vucomiss %xmm5, %xmm6
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmoval %ecx, %edx
 ; AVX512DQ-NEXT:    vpinsrd $3, %edx, %xmm4, %xmm4
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm8, %ymm4, %ymm8
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm2, %xmm5
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm2, %xmm5
 ; AVX512DQ-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm0, %xmm7
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm0, %xmm7
 ; AVX512DQ-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm7[1,1,3,3]
 ; AVX512DQ-NEXT:    vucomiss %xmm6, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmoval %ecx, %edx
 ; AVX512DQ-NEXT:    vucomiss %xmm5, %xmm7
 ; AVX512DQ-NEXT:    movl $0, %esi
 ; AVX512DQ-NEXT:    cmoval %ecx, %esi
 ; AVX512DQ-NEXT:    vmovd %esi, %xmm4

 ; AVX512DQ-NEXT:    vpinsrd $2, %edx, %xmm5, %xmm0
 ; AVX512DQ-NEXT:    vpermilps {{.*#+}} xmm4 = xmm4[3,1,2,3]
 ; AVX512DQ-NEXT:    vpermilps {{.*#+}} xmm5 = xmm6[3,1,2,3]
 ; AVX512DQ-NEXT:    vucomiss %xmm4, %xmm5
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmoval %ecx, %edx
 ; AVX512DQ-NEXT:    vpinsrd $3, %edx, %xmm0, %xmm0
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm2
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm3, %xmm0
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm3, %xmm0
 ; AVX512DQ-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm1, %xmm5
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm1, %xmm5
 ; AVX512DQ-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
 ; AVX512DQ-NEXT:    vucomiss %xmm4, %xmm6
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmoval %ecx, %edx
 ; AVX512DQ-NEXT:    vucomiss %xmm0, %xmm5
 ; AVX512DQ-NEXT:    movl $0, %esi
 ; AVX512DQ-NEXT:    cmoval %ecx, %esi
 ; AVX512DQ-NEXT:    vmovd %esi, %xmm4

 ; AVX512BW-NEXT:    vpinsrd $2, %edx, %xmm9, %xmm4
 ; AVX512BW-NEXT:    vpermilps {{.*#+}} xmm5 = xmm5[3,1,2,3]
 ; AVX512BW-NEXT:    vpermilps {{.*#+}} xmm6 = xmm7[3,1,2,3]
 ; AVX512BW-NEXT:    vucomiss %xmm5, %xmm6
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmoval %ecx, %edx
 ; AVX512BW-NEXT:    vpinsrd $3, %edx, %xmm4, %xmm4
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm8, %ymm4, %ymm8
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm2, %xmm5
+; AVX512BW-NEXT:    vextractf128 $1, %ymm2, %xmm5
 ; AVX512BW-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm0, %xmm7
+; AVX512BW-NEXT:    vextractf128 $1, %ymm0, %xmm7
 ; AVX512BW-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm7[1,1,3,3]
 ; AVX512BW-NEXT:    vucomiss %xmm6, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmoval %ecx, %edx
 ; AVX512BW-NEXT:    vucomiss %xmm5, %xmm7
 ; AVX512BW-NEXT:    movl $0, %esi
 ; AVX512BW-NEXT:    cmoval %ecx, %esi
 ; AVX512BW-NEXT:    vmovd %esi, %xmm4

 ; AVX512BW-NEXT:    vpinsrd $2, %edx, %xmm5, %xmm0
 ; AVX512BW-NEXT:    vpermilps {{.*#+}} xmm4 = xmm4[3,1,2,3]
 ; AVX512BW-NEXT:    vpermilps {{.*#+}} xmm5 = xmm6[3,1,2,3]
 ; AVX512BW-NEXT:    vucomiss %xmm4, %xmm5
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmoval %ecx, %edx
 ; AVX512BW-NEXT:    vpinsrd $3, %edx, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm2
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm3, %xmm0
+; AVX512BW-NEXT:    vextractf128 $1, %ymm3, %xmm0
 ; AVX512BW-NEXT:    vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm1, %xmm5
+; AVX512BW-NEXT:    vextractf128 $1, %ymm1, %xmm5
 ; AVX512BW-NEXT:    vmovshdup {{.*#+}} xmm6 = xmm5[1,1,3,3]
 ; AVX512BW-NEXT:    vucomiss %xmm4, %xmm6
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmoval %ecx, %edx
 ; AVX512BW-NEXT:    vucomiss %xmm0, %xmm5
 ; AVX512BW-NEXT:    movl $0, %esi
 ; AVX512BW-NEXT:    cmoval %ecx, %esi
 ; AVX512BW-NEXT:    vmovd %esi, %xmm4

 ; AVX512-NEXT:    vmovq %xmm5, %rdx
 ; AVX512-NEXT:    vmovq %xmm6, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovgq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm5
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm7[0]
 ; AVX512-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512-NEXT:    vextracti32x4 $1, %zmm2, %xmm5
+; AVX512-NEXT:    vextracti128 $1, %ymm2, %xmm5
 ; AVX512-NEXT:    vpextrq $1, %xmm5, %rdx
-; AVX512-NEXT:    vextracti32x4 $1, %zmm0, %xmm6
+; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm6
 ; AVX512-NEXT:    vpextrq $1, %xmm6, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovgq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm7
 ; AVX512-NEXT:    vmovq %xmm5, %rdx
 ; AVX512-NEXT:    vmovq %xmm6, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi

 ; AVX512-NEXT:    vmovq %xmm4, %rdx
 ; AVX512-NEXT:    vmovq %xmm5, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovgq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm4
 ; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm6[0]
 ; AVX512-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512-NEXT:    vpextrq $1, %xmm4, %rdx
-; AVX512-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; AVX512-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; AVX512-NEXT:    vpextrq $1, %xmm5, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi
 ; AVX512-NEXT:    movl $0, %edx
 ; AVX512-NEXT:    cmovgq %rcx, %rdx
 ; AVX512-NEXT:    vmovq %rdx, %xmm6
 ; AVX512-NEXT:    vmovq %xmm4, %rdx
 ; AVX512-NEXT:    vmovq %xmm5, %rsi
 ; AVX512-NEXT:    cmpq %rdx, %rsi

 ; AVX512F-NEXT:    vpinsrd $2, %edx, %xmm7, %xmm7
 ; AVX512F-NEXT:    vpextrd $3, %xmm5, %edx
 ; AVX512F-NEXT:    vpextrd $3, %xmm6, %esi
 ; AVX512F-NEXT:    cmpl %edx, %esi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgl %ecx, %edx
 ; AVX512F-NEXT:    vpinsrd $3, %edx, %xmm7, %xmm5
 ; AVX512F-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm2, %xmm5
+; AVX512F-NEXT:    vextracti128 $1, %ymm2, %xmm5
 ; AVX512F-NEXT:    vpextrd $1, %xmm5, %edx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm0, %xmm6
+; AVX512F-NEXT:    vextracti128 $1, %ymm0, %xmm6
 ; AVX512F-NEXT:    vpextrd $1, %xmm6, %esi
 ; AVX512F-NEXT:    cmpl %edx, %esi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgl %ecx, %edx
 ; AVX512F-NEXT:    vmovd %xmm5, %esi
 ; AVX512F-NEXT:    vmovd %xmm6, %edi
 ; AVX512F-NEXT:    cmpl %esi, %edi
 ; AVX512F-NEXT:    movl $0, %esi

 ; AVX512F-NEXT:    vpinsrd $2, %edx, %xmm6, %xmm6
 ; AVX512F-NEXT:    vpextrd $3, %xmm4, %edx
 ; AVX512F-NEXT:    vpextrd $3, %xmm5, %esi
 ; AVX512F-NEXT:    cmpl %edx, %esi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgl %ecx, %edx
 ; AVX512F-NEXT:    vpinsrd $3, %edx, %xmm6, %xmm4
 ; AVX512F-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512F-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512F-NEXT:    vpextrd $1, %xmm4, %edx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; AVX512F-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; AVX512F-NEXT:    vpextrd $1, %xmm5, %esi
 ; AVX512F-NEXT:    cmpl %edx, %esi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgl %ecx, %edx
 ; AVX512F-NEXT:    vmovd %xmm4, %esi
 ; AVX512F-NEXT:    vmovd %xmm5, %edi
 ; AVX512F-NEXT:    cmpl %esi, %edi
 ; AVX512F-NEXT:    movl $0, %esi

 ; AVX512DQ-NEXT:    vpinsrd $2, %edx, %xmm7, %xmm7
 ; AVX512DQ-NEXT:    vpextrd $3, %xmm5, %edx
 ; AVX512DQ-NEXT:    vpextrd $3, %xmm6, %esi
 ; AVX512DQ-NEXT:    cmpl %edx, %esi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgl %ecx, %edx
 ; AVX512DQ-NEXT:    vpinsrd $3, %edx, %xmm7, %xmm5
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm2, %xmm5
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm2, %xmm5
 ; AVX512DQ-NEXT:    vpextrd $1, %xmm5, %edx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm0, %xmm6
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm0, %xmm6
 ; AVX512DQ-NEXT:    vpextrd $1, %xmm6, %esi
 ; AVX512DQ-NEXT:    cmpl %edx, %esi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgl %ecx, %edx
 ; AVX512DQ-NEXT:    vmovd %xmm5, %esi
 ; AVX512DQ-NEXT:    vmovd %xmm6, %edi
 ; AVX512DQ-NEXT:    cmpl %esi, %edi
 ; AVX512DQ-NEXT:    movl $0, %esi

 ; AVX512DQ-NEXT:    vpinsrd $2, %edx, %xmm6, %xmm6
 ; AVX512DQ-NEXT:    vpextrd $3, %xmm4, %edx
 ; AVX512DQ-NEXT:    vpextrd $3, %xmm5, %esi
 ; AVX512DQ-NEXT:    cmpl %edx, %esi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgl %ecx, %edx
 ; AVX512DQ-NEXT:    vpinsrd $3, %edx, %xmm6, %xmm4
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512DQ-NEXT:    vpextrd $1, %xmm4, %edx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; AVX512DQ-NEXT:    vpextrd $1, %xmm5, %esi
 ; AVX512DQ-NEXT:    cmpl %edx, %esi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgl %ecx, %edx
 ; AVX512DQ-NEXT:    vmovd %xmm4, %esi
 ; AVX512DQ-NEXT:    vmovd %xmm5, %edi
 ; AVX512DQ-NEXT:    cmpl %esi, %edi
 ; AVX512DQ-NEXT:    movl $0, %esi

 ; AVX512BW-NEXT:    vpinsrd $2, %edx, %xmm7, %xmm7
 ; AVX512BW-NEXT:    vpextrd $3, %xmm5, %edx
 ; AVX512BW-NEXT:    vpextrd $3, %xmm6, %esi
 ; AVX512BW-NEXT:    cmpl %edx, %esi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgl %ecx, %edx
 ; AVX512BW-NEXT:    vpinsrd $3, %edx, %xmm7, %xmm5
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm2, %xmm5
+; AVX512BW-NEXT:    vextracti128 $1, %ymm2, %xmm5
 ; AVX512BW-NEXT:    vpextrd $1, %xmm5, %edx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm6
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm6
 ; AVX512BW-NEXT:    vpextrd $1, %xmm6, %esi
 ; AVX512BW-NEXT:    cmpl %edx, %esi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgl %ecx, %edx
 ; AVX512BW-NEXT:    vmovd %xmm5, %esi
 ; AVX512BW-NEXT:    vmovd %xmm6, %edi
 ; AVX512BW-NEXT:    cmpl %esi, %edi
 ; AVX512BW-NEXT:    movl $0, %esi

 ; AVX512BW-NEXT:    vpinsrd $2, %edx, %xmm6, %xmm6
 ; AVX512BW-NEXT:    vpextrd $3, %xmm4, %edx
 ; AVX512BW-NEXT:    vpextrd $3, %xmm5, %esi
 ; AVX512BW-NEXT:    cmpl %edx, %esi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgl %ecx, %edx
 ; AVX512BW-NEXT:    vpinsrd $3, %edx, %xmm6, %xmm4
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512BW-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512BW-NEXT:    vpextrd $1, %xmm4, %edx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; AVX512BW-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; AVX512BW-NEXT:    vpextrd $1, %xmm5, %esi
 ; AVX512BW-NEXT:    cmpl %edx, %esi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgl %ecx, %edx
 ; AVX512BW-NEXT:    vmovd %xmm4, %esi
 ; AVX512BW-NEXT:    vmovd %xmm5, %edi
 ; AVX512BW-NEXT:    cmpl %esi, %edi
 ; AVX512BW-NEXT:    movl $0, %esi

 ; AVX512BW-NEXT:    vpinsrw $6, %edx, %xmm7, %xmm7
 ; AVX512BW-NEXT:    vpextrw $7, %xmm5, %edx
 ; AVX512BW-NEXT:    vpextrw $7, %xmm6, %esi
 ; AVX512BW-NEXT:    cmpw %dx, %si
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgw %cx, %dx
 ; AVX512BW-NEXT:    vpinsrw $7, %edx, %xmm7, %xmm5
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm4, %ymm5, %ymm4
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm2, %xmm5
+; AVX512BW-NEXT:    vextracti128 $1, %ymm2, %xmm5
 ; AVX512BW-NEXT:    vpextrw $1, %xmm5, %edx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm6
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm6
 ; AVX512BW-NEXT:    vpextrw $1, %xmm6, %esi
 ; AVX512BW-NEXT:    cmpw %dx, %si
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgw %cx, %dx
 ; AVX512BW-NEXT:    vmovd %xmm5, %esi
 ; AVX512BW-NEXT:    vmovd %xmm6, %edi
 ; AVX512BW-NEXT:    cmpw %si, %di
 ; AVX512BW-NEXT:    movl $0, %esi

 ; AVX512BW-NEXT:    vpinsrw $6, %edx, %xmm6, %xmm6
 ; AVX512BW-NEXT:    vpextrw $7, %xmm4, %edx
 ; AVX512BW-NEXT:    vpextrw $7, %xmm5, %esi
 ; AVX512BW-NEXT:    cmpw %dx, %si
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgw %cx, %dx
 ; AVX512BW-NEXT:    vpinsrw $7, %edx, %xmm6, %xmm4
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm2, %ymm4, %ymm2
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512BW-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512BW-NEXT:    vpextrw $1, %xmm4, %edx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm1, %xmm5
+; AVX512BW-NEXT:    vextracti128 $1, %ymm1, %xmm5
 ; AVX512BW-NEXT:    vpextrw $1, %xmm5, %esi
 ; AVX512BW-NEXT:    cmpw %dx, %si
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgw %cx, %dx
 ; AVX512BW-NEXT:    vmovd %xmm4, %esi
 ; AVX512BW-NEXT:    vmovd %xmm5, %edi
 ; AVX512BW-NEXT:    cmpw %si, %di
 ; AVX512BW-NEXT:    movl $0, %esi

 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm9
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm11[0],xmm9[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm4, %xmm9
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm0, %xmm10
+; AVX512F-NEXT:    vextractf128 $1, %ymm4, %xmm9
+; AVX512F-NEXT:    vextractf128 $1, %ymm0, %xmm10
 ; AVX512F-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm11
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512F-NEXT:    movl $0, %edx

 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm0
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm10[0],xmm0[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm5, %xmm4
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm1, %xmm0
+; AVX512F-NEXT:    vextractf128 $1, %ymm5, %xmm4
+; AVX512F-NEXT:    vextractf128 $1, %ymm1, %xmm0
 ; AVX512F-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm10
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512F-NEXT:    movl $0, %edx

 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm4
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm6, %xmm1
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm2, %xmm4
+; AVX512F-NEXT:    vextractf128 $1, %ymm6, %xmm1
+; AVX512F-NEXT:    vextractf128 $1, %ymm2, %xmm4
 ; AVX512F-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm5
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx

 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm2
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm5[0],xmm2[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm7, %xmm2
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm3, %xmm4
+; AVX512F-NEXT:    vextractf128 $1, %ymm7, %xmm2
+; AVX512F-NEXT:    vextractf128 $1, %ymm3, %xmm4
 ; AVX512F-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovaq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm5
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512F-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512F-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512F-NEXT:    movl $0, %edx

 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm9
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm11[0],xmm9[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm4, %xmm9
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm0, %xmm10
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm4, %xmm9
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm0, %xmm10
 ; AVX512DQ-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm11
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512DQ-NEXT:    movl $0, %edx

 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm0
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm10[0],xmm0[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm5, %xmm4
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm1, %xmm0
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm5, %xmm4
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm1, %xmm0
 ; AVX512DQ-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm10
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512DQ-NEXT:    movl $0, %edx

 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm4
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm6, %xmm1
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm2, %xmm4
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm6, %xmm1
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm2, %xmm4
 ; AVX512DQ-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm5
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx

 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm2
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm5[0],xmm2[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm7, %xmm2
-; AVX512DQ-NEXT:    vextractf32x4 $1, %zmm3, %xmm4
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm7, %xmm2
+; AVX512DQ-NEXT:    vextractf128 $1, %ymm3, %xmm4
 ; AVX512DQ-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovaq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm5
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512DQ-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512DQ-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512DQ-NEXT:    movl $0, %edx

 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm9
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm11[0],xmm9[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm4, %xmm9
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm0, %xmm10
+; AVX512BW-NEXT:    vextractf128 $1, %ymm4, %xmm9
+; AVX512BW-NEXT:    vextractf128 $1, %ymm0, %xmm10
 ; AVX512BW-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm11
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm9 = xmm9[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm10 = xmm10[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm9, %xmm10
 ; AVX512BW-NEXT:    movl $0, %edx

 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm0
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm10[0],xmm0[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm5, %xmm4
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm1, %xmm0
+; AVX512BW-NEXT:    vextractf128 $1, %ymm5, %xmm4
+; AVX512BW-NEXT:    vextractf128 $1, %ymm1, %xmm0
 ; AVX512BW-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm10
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm4, %xmm0
 ; AVX512BW-NEXT:    movl $0, %edx

 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm5 = xmm5[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm4, %xmm5
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm4
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm6, %xmm1
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm2, %xmm4
+; AVX512BW-NEXT:    vextractf128 $1, %ymm6, %xmm1
+; AVX512BW-NEXT:    vextractf128 $1, %ymm2, %xmm4
 ; AVX512BW-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm5
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm1, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx

 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm2
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm5[0],xmm2[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm7, %xmm2
-; AVX512BW-NEXT:    vextractf32x4 $1, %zmm3, %xmm4
+; AVX512BW-NEXT:    vextractf128 $1, %ymm7, %xmm2
+; AVX512BW-NEXT:    vextractf128 $1, %ymm3, %xmm4
 ; AVX512BW-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovaq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm5
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm2 = xmm2[1,0]
 ; AVX512BW-NEXT:    vpermilpd {{.*#+}} xmm4 = xmm4[1,0]
 ; AVX512BW-NEXT:    vucomisd %xmm2, %xmm4
 ; AVX512BW-NEXT:    movl $0, %edx

 ; AVX512F-NEXT:    vmovq %xmm9, %rdx
 ; AVX512F-NEXT:    vmovq %xmm10, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm9
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm4, %xmm9
+; AVX512F-NEXT:    vextracti128 $1, %ymm4, %xmm9
 ; AVX512F-NEXT:    vpextrq $1, %xmm9, %rdx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm0, %xmm10
+; AVX512F-NEXT:    vextracti128 $1, %ymm0, %xmm10
 ; AVX512F-NEXT:    vpextrq $1, %xmm10, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm11
 ; AVX512F-NEXT:    vmovq %xmm9, %rdx
 ; AVX512F-NEXT:    vmovq %xmm10, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi

 ; AVX512F-NEXT:    vmovq %xmm4, %rdx
 ; AVX512F-NEXT:    vmovq %xmm0, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm0
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm10[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm5, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm5, %xmm0
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm1, %xmm4
+; AVX512F-NEXT:    vextracti128 $1, %ymm1, %xmm4
 ; AVX512F-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm10
 ; AVX512F-NEXT:    vmovq %xmm0, %rdx
 ; AVX512F-NEXT:    vmovq %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi

 ; AVX512F-NEXT:    vmovq %xmm4, %rdx
 ; AVX512F-NEXT:    vmovq %xmm5, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm4
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm6, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm6, %xmm0
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm2, %xmm4
+; AVX512F-NEXT:    vextracti128 $1, %ymm2, %xmm4
 ; AVX512F-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm5
 ; AVX512F-NEXT:    vmovq %xmm0, %rdx
 ; AVX512F-NEXT:    vmovq %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi

 ; AVX512F-NEXT:    vmovq %xmm2, %rdx
 ; AVX512F-NEXT:    vmovq %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm2
 ; AVX512F-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
 ; AVX512F-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm2
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm7, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm7, %xmm0
 ; AVX512F-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512F-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512F-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi
 ; AVX512F-NEXT:    movl $0, %edx
 ; AVX512F-NEXT:    cmovgq %rcx, %rdx
 ; AVX512F-NEXT:    vmovq %rdx, %xmm5
 ; AVX512F-NEXT:    vmovq %xmm0, %rdx
 ; AVX512F-NEXT:    vmovq %xmm4, %rsi
 ; AVX512F-NEXT:    cmpq %rdx, %rsi

 ; AVX512DQ-NEXT:    vmovq %xmm9, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm10, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm9
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm4, %xmm9
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm4, %xmm9
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm9, %rdx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm0, %xmm10
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm0, %xmm10
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm10, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm11
 ; AVX512DQ-NEXT:    vmovq %xmm9, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm10, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi

 ; AVX512DQ-NEXT:    vmovq %xmm4, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm0, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm0
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm10[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm5, %xmm0
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm5, %xmm0
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm1, %xmm4
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm1, %xmm4
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm10
 ; AVX512DQ-NEXT:    vmovq %xmm0, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi

 ; AVX512DQ-NEXT:    vmovq %xmm4, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm5, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm4
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm6, %xmm0
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm6, %xmm0
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm2, %xmm4
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm2, %xmm4
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm5
 ; AVX512DQ-NEXT:    vmovq %xmm0, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi

 ; AVX512DQ-NEXT:    vmovq %xmm2, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm2
 ; AVX512DQ-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
 ; AVX512DQ-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm2
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm7, %xmm0
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm7, %xmm0
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512DQ-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512DQ-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512DQ-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi
 ; AVX512DQ-NEXT:    movl $0, %edx
 ; AVX512DQ-NEXT:    cmovgq %rcx, %rdx
 ; AVX512DQ-NEXT:    vmovq %rdx, %xmm5
 ; AVX512DQ-NEXT:    vmovq %xmm0, %rdx
 ; AVX512DQ-NEXT:    vmovq %xmm4, %rsi
 ; AVX512DQ-NEXT:    cmpq %rdx, %rsi

 ; AVX512BW-NEXT:    vmovq %xmm9, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm10, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm9
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm8, %ymm9, %ymm8
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm4, %xmm9
+; AVX512BW-NEXT:    vextracti128 $1, %ymm4, %xmm9
 ; AVX512BW-NEXT:    vpextrq $1, %xmm9, %rdx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm10
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm10
 ; AVX512BW-NEXT:    vpextrq $1, %xmm10, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm11
 ; AVX512BW-NEXT:    vmovq %xmm9, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm10, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi

 ; AVX512BW-NEXT:    vmovq %xmm4, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm0, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm0
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm10[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm9, %ymm0, %ymm9
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm5, %xmm0
+; AVX512BW-NEXT:    vextracti128 $1, %ymm5, %xmm0
 ; AVX512BW-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm1, %xmm4
+; AVX512BW-NEXT:    vextracti128 $1, %ymm1, %xmm4
 ; AVX512BW-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm10
 ; AVX512BW-NEXT:    vmovq %xmm0, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi

 ; AVX512BW-NEXT:    vmovq %xmm4, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm5, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm4
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm1
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm6, %xmm0
+; AVX512BW-NEXT:    vextracti128 $1, %ymm6, %xmm0
 ; AVX512BW-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm2, %xmm4
+; AVX512BW-NEXT:    vextracti128 $1, %ymm2, %xmm4
 ; AVX512BW-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm5
 ; AVX512BW-NEXT:    vmovq %xmm0, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi

 ; AVX512BW-NEXT:    vmovq %xmm2, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm2
 ; AVX512BW-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm2
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm7, %xmm0
+; AVX512BW-NEXT:    vextracti128 $1, %ymm7, %xmm0
 ; AVX512BW-NEXT:    vpextrq $1, %xmm0, %rdx
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm3, %xmm4
+; AVX512BW-NEXT:    vextracti128 $1, %ymm3, %xmm4
 ; AVX512BW-NEXT:    vpextrq $1, %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi
 ; AVX512BW-NEXT:    movl $0, %edx
 ; AVX512BW-NEXT:    cmovgq %rcx, %rdx
 ; AVX512BW-NEXT:    vmovq %rdx, %xmm5
 ; AVX512BW-NEXT:    vmovq %xmm0, %rdx
 ; AVX512BW-NEXT:    vmovq %xmm4, %rsi
 ; AVX512BW-NEXT:    cmpq %rdx, %rsi

llvm/trunk/test/CodeGen/X86/vector-idiv-sdiv-512.ll

 ; AVX-NEXT:    imulq %rcx
 ; AVX-NEXT:    movq %rdx, %rax
 ; AVX-NEXT:    shrq $63, %rax
 ; AVX-NEXT:    sarq %rdx
 ; AVX-NEXT:    addq %rax, %rdx
 ; AVX-NEXT:    vmovq %rdx, %xmm2
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrq $1, %xmm2, %rax
 ; AVX-NEXT:    imulq %rcx
 ; AVX-NEXT:    movq %rdx, %rax
 ; AVX-NEXT:    shrq $63, %rax
 ; AVX-NEXT:    sarq %rdx
 ; AVX-NEXT:    addq %rax, %rdx
 ; AVX-NEXT:    vmovq %rdx, %xmm3
 ; AVX-NEXT:    vmovq %xmm2, %rax

 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    addl %ecx, %eax
 ; AVX-NEXT:    movl %eax, %ecx
 ; AVX-NEXT:    shrl $31, %ecx
 ; AVX-NEXT:    sarl $2, %eax
 ; AVX-NEXT:    addl %ecx, %eax
 ; AVX-NEXT:    vpinsrd $3, %eax, %xmm3, %xmm2
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrd $1, %xmm2, %eax
 ; AVX-NEXT:    cltq
 ; AVX-NEXT:    imulq $-1840700269, %rax, %rcx # imm = 0x92492493
 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    addl %ecx, %eax
 ; AVX-NEXT:    movl %eax, %ecx
 ; AVX-NEXT:    shrl $31, %ecx
 ; AVX-NEXT:    sarl $2, %eax

 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    movl %eax, %ecx
 ; AVX512BW-NEXT:    shrb $7, %cl
 ; AVX512BW-NEXT:    sarb $2, %al
 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    movzbl %al, %eax
 ; AVX512BW-NEXT:    vpinsrb $15, %eax, %xmm3, %xmm2
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX512BW-NEXT:    vpextrb $1, %xmm2, %eax
 ; AVX512BW-NEXT:    movsbl %al, %eax
 ; AVX512BW-NEXT:    imull $-109, %eax, %ecx
 ; AVX512BW-NEXT:    shrl $8, %ecx
 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    movl %eax, %ecx
 ; AVX512BW-NEXT:    shrb $7, %cl
 ; AVX512BW-NEXT:    sarb $2, %al

 ; AVX-NEXT:    sarq %rdx
 ; AVX-NEXT:    addq %rax, %rdx
 ; AVX-NEXT:    leaq (,%rdx,8), %rax
 ; AVX-NEXT:    subq %rdx, %rax
 ; AVX-NEXT:    subq %rax, %rcx
 ; AVX-NEXT:    vmovq %rcx, %xmm2
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrq $1, %xmm2, %rcx
 ; AVX-NEXT:    movq %rcx, %rax
 ; AVX-NEXT:    imulq %rsi
 ; AVX-NEXT:    movq %rdx, %rax
 ; AVX-NEXT:    shrq $63, %rax
 ; AVX-NEXT:    sarq %rdx
 ; AVX-NEXT:    addq %rax, %rdx
 ; AVX-NEXT:    leaq (,%rdx,8), %rax

 ; AVX-NEXT:    shrl $31, %edx
 ; AVX-NEXT:    sarl $2, %ecx
 ; AVX-NEXT:    addl %edx, %ecx
 ; AVX-NEXT:    leal (,%rcx,8), %edx
 ; AVX-NEXT:    subl %ecx, %edx
 ; AVX-NEXT:    subl %edx, %eax
 ; AVX-NEXT:    vpinsrd $3, %eax, %xmm3, %xmm2
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrd $1, %xmm2, %eax
 ; AVX-NEXT:    cltq
 ; AVX-NEXT:    imulq $-1840700269, %rax, %rcx # imm = 0x92492493
 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    addl %eax, %ecx
 ; AVX-NEXT:    movl %ecx, %edx
 ; AVX-NEXT:    shrl $31, %edx
 ; AVX-NEXT:    sarl $2, %ecx

 ; AVX512BW-NEXT:    sarb $2, %al
 ; AVX512BW-NEXT:    addb %dl, %al
 ; AVX512BW-NEXT:    # kill: %AL<def> %AL<kill> %EAX<kill>
 ; AVX512BW-NEXT:    mulb %dil
 ; AVX512BW-NEXT:    subb %al, %cl
 ; AVX512BW-NEXT:    movzbl %cl, %eax
 ; AVX512BW-NEXT:    vpinsrb $15, %eax, %xmm3, %xmm2
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX512BW-NEXT:    vpextrb $1, %xmm2, %eax
 ; AVX512BW-NEXT:    movsbl %al, %ecx
 ; AVX512BW-NEXT:    imull $-109, %ecx, %eax
 ; AVX512BW-NEXT:    shrl $8, %eax
 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    movl %eax, %edx
 ; AVX512BW-NEXT:    shrb $7, %dl
 ; AVX512BW-NEXT:    sarb $2, %al

llvm/trunk/test/CodeGen/X86/vector-idiv-udiv-512.ll

 ; AVX-NEXT:    mulq %rsi
 ; AVX-NEXT:    subq %rdx, %rcx
 ; AVX-NEXT:    shrq %rcx
 ; AVX-NEXT:    addq %rdx, %rcx
 ; AVX-NEXT:    shrq $2, %rcx
 ; AVX-NEXT:    vmovq %rcx, %xmm2
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrq $1, %xmm2, %rcx
 ; AVX-NEXT:    movq %rcx, %rax
 ; AVX-NEXT:    mulq %rsi
 ; AVX-NEXT:    subq %rdx, %rcx
 ; AVX-NEXT:    shrq %rcx
 ; AVX-NEXT:    addq %rdx, %rcx
 ; AVX-NEXT:    shrq $2, %rcx
 ; AVX-NEXT:    vmovq %rcx, %xmm3

 ; AVX-NEXT:    imulq $613566757, %rax, %rcx # imm = 0x24924925
 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    subl %ecx, %eax
 ; AVX-NEXT:    shrl %eax
 ; AVX-NEXT:    addl %ecx, %eax
 ; AVX-NEXT:    shrl $2, %eax
 ; AVX-NEXT:    vpinsrd $3, %eax, %xmm3, %xmm2
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrd $1, %xmm2, %eax
 ; AVX-NEXT:    imulq $613566757, %rax, %rcx # imm = 0x24924925
 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    subl %ecx, %eax
 ; AVX-NEXT:    shrl %eax
 ; AVX-NEXT:    addl %ecx, %eax
 ; AVX-NEXT:    shrl $2, %eax
 ; AVX-NEXT:    vmovd %xmm2, %ecx

 ; AVX512BW-NEXT:    shrl $8, %ecx
 ; AVX512BW-NEXT:    subb %cl, %al
 ; AVX512BW-NEXT:    shrb %al
 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    shrb $2, %al
 ; AVX512BW-NEXT:    movzbl %al, %eax
 ; AVX512BW-NEXT:    vpinsrb $15, %eax, %xmm3, %xmm2
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX512BW-NEXT:    vpextrb $1, %xmm2, %eax
 ; AVX512BW-NEXT:    imull $37, %eax, %ecx
 ; AVX512BW-NEXT:    shrl $8, %ecx
 ; AVX512BW-NEXT:    subb %cl, %al
 ; AVX512BW-NEXT:    shrb %al
 ; AVX512BW-NEXT:    addb %cl, %al
 ; AVX512BW-NEXT:    shrb $2, %al
 ; AVX512BW-NEXT:    movzbl %al, %eax

 ; AVX-NEXT:    addq %rdx, %rax
 ; AVX-NEXT:    shrq $2, %rax
 ; AVX-NEXT:    leaq (,%rax,8), %rdx
 ; AVX-NEXT:    subq %rax, %rdx
 ; AVX-NEXT:    subq %rdx, %rcx
 ; AVX-NEXT:    vmovq %rcx, %xmm2
 ; AVX-NEXT:    vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrq $1, %xmm2, %rcx
 ; AVX-NEXT:    movq %rcx, %rax
 ; AVX-NEXT:    mulq %rsi
 ; AVX-NEXT:    movq %rcx, %rax
 ; AVX-NEXT:    subq %rdx, %rax
 ; AVX-NEXT:    shrq %rax
 ; AVX-NEXT:    addq %rdx, %rax
 ; AVX-NEXT:    shrq $2, %rax

 ; AVX-NEXT:    shrl %edx
 ; AVX-NEXT:    addl %ecx, %edx
 ; AVX-NEXT:    shrl $2, %edx
 ; AVX-NEXT:    leal (,%rdx,8), %ecx
 ; AVX-NEXT:    subl %edx, %ecx
 ; AVX-NEXT:    subl %ecx, %eax
 ; AVX-NEXT:    vpinsrd $3, %eax, %xmm3, %xmm2
 ; AVX-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX-NEXT:    vpextrd $1, %xmm2, %eax
 ; AVX-NEXT:    imulq $613566757, %rax, %rcx # imm = 0x24924925
 ; AVX-NEXT:    shrq $32, %rcx
 ; AVX-NEXT:    movl %eax, %edx
 ; AVX-NEXT:    subl %ecx, %edx
 ; AVX-NEXT:    shrl %edx
 ; AVX-NEXT:    addl %ecx, %edx
 ; AVX-NEXT:    shrl $2, %edx

 ; AVX512BW-NEXT:    shrb %al
 ; AVX512BW-NEXT:    addb %sil, %al
 ; AVX512BW-NEXT:    shrb $2, %al
 ; AVX512BW-NEXT:    mulb %cl
 ; AVX512BW-NEXT:    subb %al, %dl
 ; AVX512BW-NEXT:    movzbl %dl, %eax
 ; AVX512BW-NEXT:    vpinsrb $15, %eax, %xmm3, %xmm2
 ; AVX512BW-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
-; AVX512BW-NEXT:    vextracti32x4 $1, %zmm0, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm2
 ; AVX512BW-NEXT:    vpextrb $1, %xmm2, %edx
 ; AVX512BW-NEXT:    imull $37, %edx, %esi
 ; AVX512BW-NEXT:    shrl $8, %esi
 ; AVX512BW-NEXT:    movl %edx, %eax
 ; AVX512BW-NEXT:    subb %sil, %al
 ; AVX512BW-NEXT:    shrb %al
 ; AVX512BW-NEXT:    addb %sil, %al
 ; AVX512BW-NEXT:    shrb $2, %al

llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v16.ll

 ; ALL-NEXT:    retq
   %shuffle = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <16 x i32> %shuffle
 }
 
 define <16 x i32> @shuffle_v16i32_04_04_04_04_04_04_04_04_04_04_04_04_04_04_04_04(<16 x i32> %a, <16 x i32> %b) {
 ; ALL-LABEL: shuffle_v16i32_04_04_04_04_04_04_04_04_04_04_04_04_04_04_04_04:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; ALL-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; ALL-NEXT:    vbroadcastss %xmm0, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <16 x i32> %a, <16 x i32> %b, <16 x i32><i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
   ret <16 x i32> %shuffle
 }
 
 define <16 x i32> @shuffle_v16i32_02_12_03_13_06_16_07_17_0a_1a_0b_1b_0e_1e_0f_1f(<16 x i32> %a, <16 x i32> %b) {
 ; ALL-LABEL: shuffle_v16i32_02_12_03_13_06_16_07_17_0a_1a_0b_1b_0e_1e_0f_1f:
; ALL-NEXT:    retq
   %res = shufflevector <16 x float> %v, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 6, i32 7, i32 10>
   ret <8 x float> %res
 }
 
 ;FIXME: can do better with vcompressp
 define <4 x float> @test_v16f32_0_1_3_6 (<16 x float> %v) {
 ; ALL-LABEL: test_v16f32_0_1_3_6:
 ; ALL:       # BB#0:
-; ALL-NEXT:    vextractf32x4 $1, %zmm0, %xmm1
-; ALL-NEXT:    vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
-; ALL-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,1,3,3]
-; ALL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; ALL-NEXT:    vpermilps {{.*#+}} xmm1 = xmm0[0,1,3,3]
+; ALL-NEXT:    vextractf128 $1, %ymm0, %xmm0
+; ALL-NEXT:    vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
+; ALL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
 ; ALL-NEXT:    vzeroupper
 ; ALL-NEXT:    retq
   %res = shufflevector <16 x float> %v, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 6>
   ret <4 x float> %res
 }
 
 define <16 x i32> @shuffle_v16i16_1_0_0_0_5_4_4_4_9_8_8_8_13_12_12_12(<16 x i32> %a, <16 x i32> %b)  {
 ; ALL-LABEL: shuffle_v16i16_1_0_0_0_5_4_4_4_9_8_8_8_13_12_12_12:

llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v32.ll

 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; KNL-NEXT:    vpbroadcastw %xmm0, %ymm0
 ; KNL-NEXT:    vmovdqa %ymm0, %ymm1
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: shuffle_v32i16_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08_08:
 ; SKX:       ## BB#0:
-; SKX-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; SKX-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; SKX-NEXT:    vpbroadcastw %xmm0, %zmm0
 ; SKX-NEXT:    retq
   %c = shufflevector <32 x i16> %a, <32 x i16> undef, <32 x i32> <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
   ret <32 x i16> %c
 }
 
 define <32 x i16> @shuffle_v32i16_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_1f(<32 x i16> %a)  {
 ; KNL-LABEL: shuffle_v32i16_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_01_02_05_u_u_07_u_0a_01_00_05_u_04_07_u_0a_1f:

llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll

 ; AVX512F-32-NEXT:    retl
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <8 x double> %shuffle
 }
 
 define <8 x double> @shuffle_v8f64_22222222(<8 x double> %a, <8 x double> %b) {
 ; AVX512F-LABEL: shuffle_v8f64_22222222:
 ; AVX512F:       # BB#0:
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; AVX512F-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX512F-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: shuffle_v8f64_22222222:
 ; AVX512F-32:       # BB#0:
-; AVX512F-32-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; AVX512F-32-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX512F-32-NEXT:    vbroadcastsd %xmm0, %zmm0
 ; AVX512F-32-NEXT:    retl
   %shuffle = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
   ret <8 x double> %shuffle
 }
 
 define <8 x double> @shuffle_v8f64_44444444(<8 x double> %a, <8 x double> %b) {
 ; AVX512F-LABEL: shuffle_v8f64_44444444:
; AVX512F-32-NEXT:    retl
   ret <4 x double> %res
 }
 
 ;FIXME: compressp
 define <2 x double> @test_v8f64_34 (<8 x double> %v) {
 ; AVX512F-LABEL: test_v8f64_34:
 ; AVX512F:       # BB#0:
 ; AVX512F-NEXT:    vextractf32x4 $2, %zmm0, %xmm1
-; AVX512F-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; AVX512F-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX512F-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0]
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
 ; AVX512F-32-LABEL: test_v8f64_34:
 ; AVX512F-32:       # BB#0:
 ; AVX512F-32-NEXT:    vextractf32x4 $2, %zmm0, %xmm1
-; AVX512F-32-NEXT:    vextractf32x4 $1, %zmm0, %xmm0
+; AVX512F-32-NEXT:    vextractf128 $1, %ymm0, %xmm0
 ; AVX512F-32-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0]
 ; AVX512F-32-NEXT:    vzeroupper
 ; AVX512F-32-NEXT:    retl
   %res = shufflevector <8 x double> %v, <8 x double> undef, <2 x i32> <i32 3, i32 4>
   ret <2 x double> %res
 }
 
 ; FIXME: vpcompress

llvm/trunk/test/CodeGen/X86/vector-shuffle-v1.ll

; VL_BW_DQ-NEXT:    retq
   ret <32 x i1> %b
 }
 
 define <8 x i1> @shuf8i1_u_2_u_u_2_u_2_u(i8 %a) {
 ; AVX512F-LABEL: shuf8i1_u_2_u_u_2_u_2_u:
 ; AVX512F:       # BB#0:
 ; AVX512F-NEXT:    kmovw %edi, %k1
 ; AVX512F-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
-; AVX512F-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; AVX512F-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; AVX512F-NEXT:    vpbroadcastq %xmm0, %zmm0
 ; AVX512F-NEXT:    vpsllq $63, %zmm0, %zmm0
 ; AVX512F-NEXT:    vptestmq %zmm0, %zmm0, %k1
 ; AVX512F-NEXT:    vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
 ; AVX512F-NEXT:    vpmovqw %zmm0, %xmm0
 ; AVX512F-NEXT:    vzeroupper
 ; AVX512F-NEXT:    retq
 ;
 ; VL_BW_DQ-LABEL: shuf8i1_u_2_u_u_2_u_2_u:
 ; VL_BW_DQ:       # BB#0:
 ; VL_BW_DQ-NEXT:    kmovd %edi, %k0
 ; VL_BW_DQ-NEXT:    vpmovm2q %k0, %zmm0
-; VL_BW_DQ-NEXT:    vextracti32x4 $1, %zmm0, %xmm0
+; VL_BW_DQ-NEXT:    vextracti128 $1, %ymm0, %xmm0
 ; VL_BW_DQ-NEXT:    vpbroadcastq %xmm0, %zmm0
 ; VL_BW_DQ-NEXT:    vpmovq2m %zmm0, %k0
 ; VL_BW_DQ-NEXT:    vpmovm2w %k0, %xmm0
 ; VL_BW_DQ-NEXT:    vzeroupper
 ; VL_BW_DQ-NEXT:    retq
   %b = bitcast i8 %a to <8 x i1>
   %c = shufflevector < 8 x i1> %b, <8 x i1>undef, <8 x i32> <i32 undef, i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef>
   ret <8 x i1> %c