[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes

[dp]

Summary

This is a fix for Bug 34152 (VOP3 opcodes only).
A fix for VOP2 opcodes promoted to VOP3 will be added separately.

See https://bugs.llvm.org//show_bug.cgi?id=34152

[SamWot]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPU.td

 >;
 
 def FeatureDPP : SubtargetFeature<"dpp",
   "HasDPP",
   "true",
   "Support DPP (Data Parallel Primitives) extension"
 >;
 
+def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
+  "HasIntClamp",
+  "true",
+  "Support clamp for integer destination"
+>;
+
 //===------------------------------------------------------------===//
 // Subtarget Features (options and debugging)
 //===------------------------------------------------------------===//
 
 // Some instructions do not support denormals despite this flag. Using
 // fp32 denormals also causes instructions to run at the double
 // precision rate for the device.
 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",

 >;
 
 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
    FeatureScalarStores, FeatureInv2PiInlineImm,
-   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP
+   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
+   FeatureIntClamp
   ]
 >;
 
 def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
    FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
    FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
    FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
-   FeatureFastFMAF32, FeatureDPP,
+   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
    FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
    FeatureAddNoCarryInsts
   ]
 >;
 
 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
                                   list<SubtargetFeature> Implies>
def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
   AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
 
 def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
   AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
 
 def HasDPP : Predicate<"Subtarget->hasDPP()">,
   AssemblerPredicate<"FeatureDPP">;
 
+def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
+  AssemblerPredicate<"FeatureIntClamp">;
+
 class PredicateControl {
   Predicate SubtargetPredicate;
   Predicate SIAssemblerPredicate = isSICI;
   Predicate VIAssemblerPredicate = isVI;
   list<Predicate> AssemblerPredicates = [];
   Predicate AssemblerPredicate = TruePredicate;
   list<Predicate> OtherPredicates = [];
   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td

 >;
 
 def cvt_flr_i32_f32 : PatFrag <
   (ops node:$src),
   (fp_to_sint (ffloor $src)),
   [{ (void)N; return TM.Options.NoNaNsFPMath; }]
 >;
 
-class IMad24Pat<Instruction Inst> : Pat <
+class IMad24Pat<Instruction Inst, bit HasClamp = 0> : Pat <
   (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
-  (Inst $src0, $src1, $src2)
+  !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)),
+                (Inst $src0, $src1, $src2))
 >;
 
-class UMad24Pat<Instruction Inst> : Pat <
+class UMad24Pat<Instruction Inst, bit HasClamp = 0> : Pat <
   (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
-  (Inst $src0, $src1, $src2)
+  !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)),
+                (Inst $src0, $src1, $src2))
 >;
 
 class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
   (fdiv FP_ONE, vt:$src),
   (RcpInst $src)
 >;
 
 class RsqPat<Instruction RsqInst, ValueType vt> : Pat <

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h

protected:
   bool FP64;
   bool IsGCN;
   bool GCN3Encoding;
   bool CIInsts;
   bool GFX9Insts;
   bool SGPRInitBug;
   bool HasSMemRealTime;
   bool Has16BitInsts;
+  bool HasIntClamp;
   bool HasVOP3PInsts;
   bool HasMovrel;
   bool HasVGPRIndexMode;
   bool HasScalarStores;
   bool HasInv2PiInlineImm;
   bool HasSDWA;
   bool HasSDWAOmod;
   bool HasSDWAScalar;
public:
   AMDGPUAS getAMDGPUAS() const {
     return AS;
   }
 
   bool has16BitInsts() const {
     return Has16BitInsts;
   }
 
+  bool hasIntClamp() const {
+    return HasIntClamp;
+  }
+
   bool hasVOP3PInsts() const {
     return HasVOP3PInsts;
   }
 
   bool hasHWFP64() const {
     return FP64;
   }
 

llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

: AMDGPUGenSubtargetInfo(TT, GPU, FS),
     FP64(false),
     IsGCN(false),
     GCN3Encoding(false),
     CIInsts(false),
     GFX9Insts(false),
     SGPRInitBug(false),
     HasSMemRealTime(false),
     Has16BitInsts(false),
+    HasIntClamp(false),
     HasVOP3PInsts(false),
     HasMovrel(false),
     HasVGPRIndexMode(false),
     HasScalarStores(false),
     HasInv2PiInlineImm(false),
     HasSDWA(false),
     HasSDWAOmod(false),
     HasSDWAScalar(false),

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   bool hasFlatOffsets() const {
     return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];
   }
 
   bool hasSGPR102_SGPR103() const {
     return !isVI();
   }
 
+  bool hasIntClamp() const {
+    return getFeatureBits()[AMDGPU::FeatureIntClamp];
+  }
+
   AMDGPUTargetStreamer &getTargetStreamer() {
     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     return static_cast<AMDGPUTargetStreamer &>(TS);
   }
 
   const MCRegisterInfo *getMRI() const {
     // We need this const_cast because for some reason getContext() is not const
     // in MCAsmParser.
private:
   bool parseHwregConstruct(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
 
   void errorExpTgt();
   OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
 
   bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc);
   bool validateConstantBusLimitations(const MCInst &Inst);
   bool validateEarlyClobberLimitations(const MCInst &Inst);
+  bool validateIntClampSupported(const MCInst &Inst);
   bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
   bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
   unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
 
   bool trySkipId(const StringRef Id);
   bool trySkipToken(const AsmToken::TokenKind Kind);
   bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
   bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");
if (Src.isReg()) {
         return false;
       }
     }
   }
 
   return true;
 }
 
+bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
+
+  const unsigned Opc = Inst.getOpcode();
+  const MCInstrDesc &Desc = MII.get(Opc);
+
+  if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {
+    int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);
+    assert(ClampIdx != -1);
+    return Inst.getOperand(ClampIdx).getImm() == 0;
+  }
+
+  return true;
+}
+
 bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
                                           const SMLoc &IDLoc) {
   if (!validateConstantBusLimitations(Inst)) {
     Error(IDLoc,
       "invalid operand (violates constant bus restrictions)");
     return false;
   }
   if (!validateEarlyClobberLimitations(Inst)) {
     Error(IDLoc,
       "destination must be different than all sources");
     return false;
   }
+  if (!validateIntClampSupported(Inst)) {
+    Error(IDLoc,
+      "integer clamping is not supported on this GPU");
+    return false;
+  }
 
   return true;
 }
 
 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                               OperandVector &Operands,
                                               MCStreamer &Out,
                                               uint64_t &ErrorInfo,

llvm/trunk/lib/Target/AMDGPU/SIDefines.h

// TODO: Should this be spilt into VOP3 a and b?
   Gather4 = UINT64_C(1) << 37,
   SOPK_ZEXT = UINT64_C(1) << 38,
   SCALAR_STORE = UINT64_C(1) << 39,
   FIXED_SIZE = UINT64_C(1) << 40,
   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
   HasFPClamp = UINT64_C(1) << 42,
   VOP3_OPSEL = UINT64_C(1) << 43,
   maybeAtomic = UINT64_C(1) << 44,
-  F16_ZFILL = UINT64_C(1) << 45
+  F16_ZFILL = UINT64_C(1) << 45,
+  IntClamp = UINT64_C(1) << 46
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
 // The result is true if any of these tests are true.
 enum ClassFlags {
   S_NAN = 1 << 0,        // Signaling NaN
   Q_NAN = 1 << 1,        // Quiet NaN
   N_INFINITY = 1 << 2,   // Negative infinity

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
 
   // Is it possible for this instruction to be atomic?
   field bit maybeAtomic = 0;
 
   // This bit indicates that this is a 16-bit instruction which zero-fills
   // unused bits in dst. Note that new GFX9 opcodes preserve unused bits.
   field bit F16_ZFILL = 0;
 
+  // This bit indicates that instruction may support integer clamping
+  // which depends on GPU features.
+  field bit IntClamp = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
 
   let TSFlags{2} = SOP1;
   let TSFlags{3} = SOP2;
   let TSFlags{4} = SOPC;
   let TSFlags{5} = SOPK;
class InstSI <dag outs, dag ins, string asm = "",
   let TSFlags{39} = ScalarStore;
   let TSFlags{40} = FixedSize;
   let TSFlags{41} = VOPAsmPrefer32Bit;
   let TSFlags{42} = FPClamp;
   let TSFlags{43} = VOP3_OPSEL;
 
   let TSFlags{44} = maybeAtomic;
   let TSFlags{45} = F16_ZFILL;
+  let TSFlags{46} = IntClamp;
 
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
   field bits<1> DisableVIDecoder = 0;
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
   dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0),               // VOP1
             !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
                                     (ins)));
 }
 
 // Returns the input arguments for VOP3 instructions for the given SrcVT.
 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
                 RegisterOperand Src2RC, int NumSrcArgs,
-                bit HasModifiers, bit HasOMod,
+                bit HasIntClamp, bit HasModifiers, bit HasOMod,
                 Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
 
   dag ret =
     !if (!eq(NumSrcArgs, 0),
       // VOP1 without input operands (V_NOP, V_CLREXCP)
       (ins),
       /* else */
     !if (!eq(NumSrcArgs, 1),
       !if (!eq(HasModifiers, 1),
         // VOP1 with modifiers
         (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
              clampmod:$clamp, omod:$omod)
       /* else */,
         // VOP1 without modifiers
-        (ins Src0RC:$src0)
+        !if (!eq(HasIntClamp, 1),
+          (ins Src0RC:$src0, clampmod:$clamp),
+          (ins Src0RC:$src0))
       /* endif */ ),
     !if (!eq(NumSrcArgs, 2),
       !if (!eq(HasModifiers, 1),
         // VOP 2 with modifiers
         !if( !eq(HasOMod, 1),
           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
                Src1Mod:$src1_modifiers, Src1RC:$src1,
                clampmod:$clamp, omod:$omod),
            (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
                Src1Mod:$src1_modifiers, Src1RC:$src1,
                clampmod:$clamp))
       /* else */,
         // VOP2 without modifiers
-        (ins Src0RC:$src0, Src1RC:$src1)
+        !if (!eq(HasIntClamp, 1),
+          (ins Src0RC:$src0, Src1RC:$src1, clampmod:$clamp),
+          (ins Src0RC:$src0, Src1RC:$src1))
+
       /* endif */ )
     /* NumSrcArgs == 3 */,
       !if (!eq(HasModifiers, 1),
         // VOP3 with modifiers
         !if (!eq(HasOMod, 1),
           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
                Src1Mod:$src1_modifiers, Src1RC:$src1,
                Src2Mod:$src2_modifiers, Src2RC:$src2,
                clampmod:$clamp, omod:$omod),
           (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
                Src1Mod:$src1_modifiers, Src1RC:$src1,
                Src2Mod:$src2_modifiers, Src2RC:$src2,
                clampmod:$clamp))
       /* else */,
         // VOP3 without modifiers
-        (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
+        !if (!eq(HasIntClamp, 1),
+          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod:$clamp),
+          (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
       /* endif */ ))));
 }
 
 /// XXX - src1 may only allow VGPRs?
 
 // The modifiers (except clamp) are dummy operands for the benefit of
 // printing and parsing. They defer their values to looking at the
 // srcN_modifiers for what to print.
class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
   string ret = !if(HasDst, dst, "") #
                !if(!eq(NumSrcArgs, 1), src0, "") #
                !if(!eq(NumSrcArgs, 2), src0#src1, "") #
                !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
 }
 
 // Returns the assembly string for the inputs and outputs of a VOP3
 // instruction.
-class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers,
+class getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
                 bit HasOMod, ValueType DstVT = i32> {
   string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
   string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
   string src1 = !if(!eq(NumSrcArgs, 1), "",
                    !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
                                            " $src1_modifiers,"));
   string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
+  string iclamp = !if(HasIntClamp, "$clamp", "");
   string ret =
   !if(!eq(HasModifiers, 0),
-      getAsm32<HasDst, NumSrcArgs, DstVT>.ret,
+      getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
       dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
 }
 
 // Returns the assembly string for the inputs and outputs of a VOP3P
 // instruction.
 class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
                    bit HasClamp, ValueType DstVT = i32> {
   string dst = " $vdst";
class VOPProfile <list<ValueType> _ArgVT> {
 
   field bit HasSrc0Mods = HasModifiers;
   field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
   field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
 
   field bit HasClamp = HasModifiers;
   field bit HasSDWAClamp = EmitDst;
   field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
+  field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
   field bit HasHigh = 0;
 
   field bit IsPacked = isPackedType<Src0VT>.ret;
   field bit HasOpSel = IsPacked;
   field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
   field bit HasSDWAOMod = isFloatType<DstVT>.ret;
 
   field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
class VOPProfile <list<ValueType> _ArgVT> {
   // output. This is manually overridden for them.
   field dag Outs32 = Outs;
   field dag Outs64 = Outs;
   field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
   field dag OutsSDWA = getOutsSDWA<HasDst, DstVT, DstRCSDWA>.ret;
 
   field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
   field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
-                             HasModifiers, HasOMod, Src0Mod, Src1Mod,
+                             HasIntClamp, HasModifiers, HasOMod, Src0Mod, Src1Mod,
                              Src2Mod>.ret;
   field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
                                    NumSrcArgs, HasClamp,
                                    Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
   field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64,
                                            NumSrcArgs,
                                            HasClamp,
                                            getOpSelMod<Src0VT>.ret,
                                            getOpSelMod<Src1VT>.ret,
                                            getOpSelMod<Src2VT>.ret>.ret;
   field dag InsDPP = getInsDPP<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
                                HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
   field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
                                  HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
                                  DstVT>.ret;
 
 
   field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
-  field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, HasOMod, DstVT>.ret;
+  field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
   field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasModifiers, HasClamp, DstVT>.ret;
   field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
                                               HasClamp,
                                               HasSrc0FloatMods,
                                               HasSrc1FloatMods,
                                               HasSrc2FloatMods>.ret;
   field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
   field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

(V_CVT_U32_F32_e32
     (V_MUL_F32_e32 (i32 CONST.FP_UINT_MAX_PLUS_1),
                    (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
 >;
 
 //===----------------------------------------------------------------------===//
 // VOP3 Patterns
 //===----------------------------------------------------------------------===//
 
-def : IMad24Pat<V_MAD_I32_I24>;
-def : UMad24Pat<V_MAD_U32_U24>;
+def : IMad24Pat<V_MAD_I32_I24, 1>;
+def : UMad24Pat<V_MAD_U32_U24, 1>;
 
 defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
 def : ROTRPattern <V_ALIGNBIT_B32>;
 
 def : Pat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
           (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
                           (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
 

 //===----------------------------------------------------------------------===//
 // SAD Patterns
 //===----------------------------------------------------------------------===//
 
 def : Pat <
   (add (sub_oneuse (umax i32:$src0, i32:$src1),
                    (umin i32:$src0, i32:$src1)),
        i32:$src2),
-  (V_SAD_U32 $src0, $src1, $src2)
+  (V_SAD_U32 $src0, $src1, $src2, (i1 0))
 >;
 
 def : Pat <
   (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)),
                       (sub i32:$src0, i32:$src1),
                       (sub i32:$src1, i32:$src0)),
        i32:$src2),
-  (V_SAD_U32 $src0, $src1, $src2)
+  (V_SAD_U32 $src0, $src1, $src2, (i1 0))
 >;
 
 //===----------------------------------------------------------------------===//
 // Conversion Patterns
 //===----------------------------------------------------------------------===//
 
 def : Pat<(i32 (sext_inreg i32:$src, i1)),
   (S_BFE_I32 i32:$src, (i32 65536))>; // 0 | 1 << 16

llvm/trunk/lib/Target/AMDGPU/VOP1Instructions.td

let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
 
   let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                      clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel);
 
   let Asm32 = getAsm32<1, 1>.ret;
-  let Asm64 = getAsm64<1, 1, 0, 1>.ret;
+  let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
   let AsmDPP = getAsmDPP<1, 1, 0>.ret;
   let AsmSDWA = getAsmSDWA<1, 1>.ret;
   let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
 
   let HasExt = 0;
   let HasSDWA9 = 0;
   let HasDst = 0;
   let EmitDst = 1; // force vdst emission

llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td

 def VOP_MADMK_F16 : VOP_MADMK <f16>;
 def VOP_MADMK_F32 : VOP_MADMK <f32>;
 
 // FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
 // and processing time but it makes it easier to convert to mad.
 class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
   let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
-                       HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
+                       0, HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
   let InsDPP = (ins DstRCDPP:$old,
                     Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
                     Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
                     dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
                     bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
 
   let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                      Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
                      VGPR_32:$src2, // stub argument
                      clampmod:$clamp, omod:$omod,
                      dst_sel:$dst_sel, dst_unused:$dst_unused,
                      src0_sel:$src0_sel, src1_sel:$src1_sel);
   let Asm32 = getAsm32<1, 2, vt>.ret;
-  let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, vt>.ret;
+  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, vt>.ret;
   let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret;
   let AsmSDWA = getAsmSDWA<1, 2, vt>.ret;
   let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret;
   let HasSrc2 = 0;
   let HasSrc2Mods = 0;
   let HasExt = 1;
   let HasSDWA9 = 0;
 }
 
 def VOP_MAC_F16 : VOP_MAC <f16> {
   // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
   // 'not a string initializer' error.
-  let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f16>.ret;
+  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f16>.ret;
 }
 
 def VOP_MAC_F32 : VOP_MAC <f32> {
   // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
   // 'not a string initializer' error.
-  let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f32>.ret;
+  let Asm64 = getAsm64<1, 2, 0, HasModifiers, HasOMod, f32>.ret;
 }
 
 // Write out to vcc or arbitrary SGPR.
 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
   let Asm32 = "$vdst, vcc, $src0, $src1";
   let Asm64 = "$vdst, $sdst, $src0, $src1";
   let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
   let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";

llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td

class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
   list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
   list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
   list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
   list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
                   !if(!eq(P.NumSrcArgs, 2), ret2,
                   ret1));
 }
 
+class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
+  list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
+  list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
+  list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
+  list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
+                  !if(!eq(P.NumSrcArgs, 2), ret2,
+                  ret1));
+}
+
 class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
   VOP3_Pseudo<OpName, P,
-    !if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret),
-    VOP3Only>;
+    !if(P.HasModifiers,
+        getVOP3ModPat<P, node>.ret,
+        !if(P.HasIntClamp,
+            getVOP3ClampPat<P, node>.ret,
+            getVOP3Pat<P, node>.ret)),
+    VOP3Only> {
+  let IntClamp = P.HasIntClamp;
+}
 
 class VOP3OpSelInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
   VOP3_Pseudo<OpName, P,
     !if(isFloatType<P.Src0VT>.ret,
         getVOP3OpSelModPat<P, node>.ret,
         getVOP3OpSelPat<P, node>.ret),
     1, 0, 1> {
 

 }
 
 class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
   // FIXME: Hack to stop printing _e64
   let Outs64 = (outs DstRC.RegClass:$vdst);
   let Asm64 = " " # P.Asm64;
 }
 
+class VOP3Clamp_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
+  let HasClamp = 1;
+
+  // FIXME: Hack to stop printing _e64
+  let Outs64 = (outs DstRC.RegClass:$vdst);
+  let Asm64 = " " # getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
+}
+
 class VOP3OpSel_Profile<VOPProfile P> : VOP3_Profile<P> {
   let HasClamp = 1;
   let HasOpSel = 1;
 }
 
 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
   // v_div_scale_{f32|f64} do not support input modifiers.
   let HasModifiers = 0;
   let HasOMod = 0;
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
   let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
 }
 
 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
   // FIXME: Hack to stop printing _e64
   let DstRC = RegisterOperand<VGPR_32>;
 }
 
 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
   // FIXME: Hack to stop printing _e64
   let DstRC = RegisterOperand<VReg_64>;
 }
 
 def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
+  let HasClamp = 1;
+
   // FIXME: Hack to stop printing _e64
   let DstRC = RegisterOperand<VReg_64>;
 
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
-  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
+  let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
 }
 
 //===----------------------------------------------------------------------===//
 // VOP3 INTERP
 //===----------------------------------------------------------------------===//
 
 class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
   let AsmMatchConverter = "cvtVOP3Interp";

 //===----------------------------------------------------------------------===//
 // VOP3 Instructions
 //===----------------------------------------------------------------------===//
 
 let isCommutable = 1 in {
 
 def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
 def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
-def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_i24>;
-def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_u24>;
+def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
+def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
 def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
 def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
 def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
 
 let SchedRW = [WriteDoubleAdd] in {
 def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
 def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
 def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;

 def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
 def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
 def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
 def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
 def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
 def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
 def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
 def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
-def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u8>;
-def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_hi_u8>;
-def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u16>;
-def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
+def V_SAD_U8 : VOP3Inst <"v_sad_u8",    VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
+def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
+def V_SAD_U16 : VOP3Inst <"v_sad_u16",   VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
+def V_SAD_U32 : VOP3Inst <"v_sad_u32",   VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
 def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
 def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
 
 let SchedRW = [WriteDoubleAdd] in {
 def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
 def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
 } // End SchedRW = [WriteDoubleAdd]
 
 def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
   let SchedRW = [WriteFloatFMA, WriteSALU];
   let hasExtraSrcRegAllocReq = 1;
   let AsmMatchConverter = "";
 }
 
 // Double precision division pre-scale.
 def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
   let SchedRW = [WriteDouble, WriteSALU];
   let hasExtraSrcRegAllocReq = 1;
   let AsmMatchConverter = "";
 }
 
-def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>;
+def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3Clamp_Profile<VOP_I32_I32_I32_I32>>;
 
 let Constraints = "@earlyclobber $vdst" in {
-def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_mqsad_pk_u16_u8>;
+def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3Clamp_Profile<VOP_I64_I64_I32_I64>>;
 } // End Constraints = "@earlyclobber $vdst"
 
 def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
   let SchedRW = [WriteDouble];
 }
 
 // These instructions only exist on SI and CI
 let SubtargetPredicate = isSICI in {
 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
 def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
 def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
 def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
 } // End SubtargetPredicate = isSICI
 
 let SubtargetPredicate = isVI in {
 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
 def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
 } // End SubtargetPredicate = isVI
 
 
 let SubtargetPredicate = isCIVI in {
 
 let Constraints = "@earlyclobber $vdst" in {
-def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>;
-def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>;
+def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3Clamp_Profile<VOP_I64_I64_I32_I64>>;
+def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3Clamp_Profile<VOP_V4I32_I64_I32_V4I32>>;
 } // End Constraints = "@earlyclobber $vdst"
 
 let isCommutable = 1 in {
 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = isCIVI
 
 
 let SubtargetPredicate = Has16BitInsts in {
 
 let F16_ZFILL = 1 in {
 def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
 }
 let SubtargetPredicate = isGFX9 in {
 def V_DIV_FIXUP_F16_gfx9   : VOP3Inst <"v_div_fixup_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
 }
 
 let isCommutable = 1 in {
 
 let F16_ZFILL = 1 in {
 def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
-def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
-def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3Clamp_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3Clamp_Profile<VOP_I16_I16_I16_I16>>;
 def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
 }
 
 let SubtargetPredicate = isGFX9 in {
 def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
-def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
-def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3Clamp_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3Clamp_Profile<VOP_I16_I16_I16_I16>>;
 def V_FMA_F16_gfx9   : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16>>;
 } // End SubtargetPredicate = isGFX9
 
 def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
 def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
 def V_INTERP_P2_F16   : VOP3Interp <"v_interp_p2_f16",   VOP3_INTERP16<[f16, f32, i32, f32]>>;
 
 }  // End isCommutable = 1
 } // End SubtargetPredicate = Has16BitInsts
 
 let SubtargetPredicate = isVI in {
 def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
 def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
 def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
 
 def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
 } // End SubtargetPredicate = isVI
 
 let Predicates = [Has16BitInsts] in {
 
 multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
                              Instruction inst, SDPatternOperator op3> {
 def : Pat<
   (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
-  (inst i16:$src0, i16:$src1, i16:$src2)
+  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
 >;
 
 def : Pat<
   (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
-  (inst i16:$src0, i16:$src1, i16:$src2)
+  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
 >;
 
 def : Pat<
   (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
    (REG_SEQUENCE VReg_64,
-     (inst i16:$src0, i16:$src1, i16:$src2), sub0,
+     (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)), sub0,
      (V_MOV_B32_e32 (i32 0)), sub1)
 >;
 }
 
 defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
 defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
 
 } // End Predicates = [Has16BitInsts]

 
 def V_MAD_U32_U16 : VOP3OpSelInst <"v_mad_u32_u16", VOP3OpSel_Profile<VOP_I32_I16_I16_I32>>;
 def V_MAD_I32_I16 : VOP3OpSelInst <"v_mad_i32_i16", VOP3OpSel_Profile<VOP_I32_I16_I16_I32>>;
 
 def V_CVT_PKNORM_I16_F16 : VOP3OpSelInst <"v_cvt_pknorm_i16_f16", VOP3OpSel_Profile<VOP_B32_F16_F16>>;
 def V_CVT_PKNORM_U16_F16 : VOP3OpSelInst <"v_cvt_pknorm_u16_f16", VOP3OpSel_Profile<VOP_B32_F16_F16>>;
 } // End SubtargetPredicate = isGFX9
 
+//===----------------------------------------------------------------------===//
+// Integer Clamp Patterns
+//===----------------------------------------------------------------------===//
+
+class getClampPat<VOPProfile P, SDPatternOperator node> {
+  dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
+  dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
+  dag ret1 = (P.DstVT (node P.Src0VT:$src0));
+  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
+            !if(!eq(P.NumSrcArgs, 2), ret2,
+            ret1));
+}
+
+class getClampRes<VOPProfile P, Instruction inst> {
+  dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
+  dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
+  dag ret1 = (inst P.Src0VT:$src0, (i1 0));
+  dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
+            !if(!eq(P.NumSrcArgs, 2), ret2,
+            ret1));
+}
+
+class IntClampPat<VOP3Inst inst, SDPatternOperator node> : Pat<
+  getClampPat<inst.Pfl, node>.ret,
+  getClampRes<inst.Pfl, inst>.ret
+>;
+
+def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
+def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
+
+def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
+def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
+def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
+
+def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
+def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
+
+def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
+def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
 
 //===----------------------------------------------------------------------===//
 // Target
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // SI
 //===----------------------------------------------------------------------===//

llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td

class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
   let VALU = 1;
   let FPClamp = P.HasFPClamp;
   let Uses = [EXEC];
 
   let AsmVariantName = AMDGPUAsmVariants.VOP3;
   let AsmMatchConverter =
     !if(!and(P.IsPacked, isVOP3P),
         "cvtVOP3P",
-        !if(!or(P.HasModifiers, P.HasOMod),
+        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
             "cvtVOP3",
             ""));
 
   VOPProfile Pfl = P;
 }
 
 class VOP3P_Pseudo <string opName, VOPProfile P, list<dag> pattern = []> :
   VOP3_Pseudo<opName, P, pattern, 1, 1> {

llvm/trunk/test/MC/AMDGPU/vop3-gfx9.s

 // GFX9: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
 
 v_mad_i16 v5, v1, -1, v3
 // GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
 
 v_mad_i16 v5, v1, v2, -4.0
 // GFX9: v_mad_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
 
+v_mad_i16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
 v_mad_legacy_f16_e64 v5, 0.5, v2, v3
 // GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
 
 v_mad_legacy_f16 v5, v1, 0.5, v3
 // GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
 
 v_mad_legacy_f16 v5, v1, v2, 0.5
 // GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]

 // GFX9: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
 
 v_mad_legacy_i16 v5, v1, -1, v3
 // GFX9: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
 
 v_mad_legacy_i16 v5, v1, v2, -4.0
 // GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
 
+v_mad_legacy_i16 v5, v1, v2, -4.0 clamp
+// GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 clamp ; encoding: [0x05,0x80,0xec,0xd1,0x01,0x05,0xde,0x03]
+
 v_mad_legacy_u16_e64 v5, 0, v2, v3
 // GFX9: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
 
 v_mad_legacy_u16 v5, v1, -1, v3
 // GFX9: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
 
 v_mad_legacy_u16 v5, v1, v2, -4.0
 // GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
 
+v_mad_legacy_u16 v5, v1, v2, -4.0 clamp
+// GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 clamp ; encoding: [0x05,0x80,0xeb,0xd1,0x01,0x05,0xde,0x03]
+
 v_mad_u16_e64 v5, 0, v2, v3
 // GFX9: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
 
 v_mad_u16 v5, v1, -1, v3
 // GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
 
 v_mad_u16 v5, v1, v2, -4.0
 // GFX9: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_u16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]

llvm/trunk/test/MC/AMDGPU/vop3.s

 // VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
 
 v_mad_u16 v5, v1, 0, v3
 // VI: v_mad_u16 v5, v1, 0, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
 
 v_mad_u16 v5, v1, v2, -4.0
 // VI: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
 
+///===---------------------------------------------------------------------===//
+// VOP3 with Integer Clamp
+///===---------------------------------------------------------------------===//
+
+v_mad_i32_i24 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_mad_i32_i24 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_mad_u32_u24 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_sad_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_sad_hi_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_sad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_sad_u32 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v5, v1, v2, v3 clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_msad_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// NOSICI: error: integer clamping is not supported on this GPU
+// VI: v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp ; encoding: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// NOSICI: error:
+// VI: v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp ; encoding: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp
+// NOSICI: error:
+// VI: v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp ; encoding: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 clamp
+// NOSICI: error:
+// VI: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 clamp
+// NOSICI: error:
+// VI: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
 //
 // v_interp*
 //
 
 v_interp_mov_f32_e64 v5, p10, attr0.x
 // NOSICI: error: instruction not supported on this GPU
 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
 

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx901 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
 
 # GFX9: v_fma_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04
 
 # GFX9: v_fma_f16 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
 0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24
 
 # GFX9: v_fma_f16 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04
 
 # GFX9: v_fma_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04
 
-# CHECK: v_fma_legacy_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_fma_legacy_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_fma_legacy_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
+# GFX9: v_fma_legacy_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
 0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84
 
-# CHECK: v_fma_legacy_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_fma_legacy_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_fma_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_fma_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+# GFX9: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
 0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04
 
-# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+# GFX9: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
 0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04
 
-# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+# GFX9: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
 0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03
 
-# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
+# GFX9: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
 0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4
 
-# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
+# GFX9: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04
 
-# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+# GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04
 
-# CHECK: v_div_fixup_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+# GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
 0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
 
-# CHECK: v_div_fixup_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+# GFX9: v_div_fixup_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
 0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
 
-# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+# GFX9: v_div_fixup_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
 0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
 
-# CHECK: v_div_fixup_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+# GFX9: v_div_fixup_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
 0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
 
-# CHECK: v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+# GFX9: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
 0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04
 
-# CHECK: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+# GFX9: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
 0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04
 
-# CHECK: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+# GFX9: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
 0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03
 
-# CHECK: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
+# GFX9: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
 0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4
 
-# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
+# GFX9: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04
 
-# CHECK: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+# GFX9: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
 0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04
 
-# CHECK: v_mad_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+# GFX9: v_mad_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
 0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04
 
-# CHECK: v_mad_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+# GFX9: v_mad_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
 0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
 
-# CHECK: v_mad_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
+# GFX9: v_mad_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
 0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
 
-# CHECK: v_mad_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+# GFX9: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
 0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
 
-# CHECK: v_mad_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+# GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
 0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
 
-# CHECK: v_mad_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+# GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
 0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
 
-# CHECK: v_mad_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+# GFX9: v_mad_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
 0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
 
-# CHECK: v_mad_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_mad_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_mad_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+# GFX9: v_mad_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
 0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
 
-# CHECK: v_mad_legacy_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+# GFX9: v_mad_legacy_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
 0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04
 
-# CHECK: v_mad_legacy_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+# GFX9: v_mad_legacy_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
 0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04
 
-# CHECK: v_mad_legacy_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
+# GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
 0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03
 
-# CHECK: v_mad_legacy_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+# GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 clamp ; encoding: [0x05,0x80,0xec,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x80,0xec,0xd1,0x01,0x05,0xde,0x03
+
+# GFX9: v_mad_legacy_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
 0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
 
-# CHECK: v_mad_legacy_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+# GFX9: v_mad_legacy_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
 0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
 
-# CHECK: v_mad_legacy_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+# GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
 0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
 
-# CHECK: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+# GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 clamp ; encoding: [0x05,0x80,0xeb,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x80,0xeb,0xd1,0x01,0x05,0xde,0x03
+
+# GFX9: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
 0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04
 
-# CHECK: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+# GFX9: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
 0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
 
-# CHECK: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
+# GFX9: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
 0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03
+
+# GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04

llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_vi.txt

 # VI: v_interp_p2_f16 v5, v2, attr0.x, |v3|    ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
 0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
 
 # VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high    ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
 0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
 
 # VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp    ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
 0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04
+
+# VI: v_mad_i32_i24 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_mad_u32_u24 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_sad_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_sad_hi_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_sad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_sad_u32 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_msad_u8 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp ; encoding: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp ; encoding: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp ; encoding: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_mad_i16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04