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Differential D36222

[MIPS] Add support to match more patterns for BBIT instruction.
ClosedPublic

Authored by spetrovic on Aug 2 2017, 7:54 AM.

Details

Reviewers
sdardis
Commits
rG89df797ee978: [MIPS] Add support to match more patterns for BBIT instruction
rL312111: [MIPS] Add support to match more patterns for BBIT instruction
Summary

This patch supports one more pattern for bbit0 and bbit1 instructions, I expanded CBranchBitNum class so it can take 32 bit immidate. Example:

long long var = 7;
void bbit0i32 () {

if ((var & 0x2)) {
  printf("bbit0i32");
}

}

Before the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	30210002 	andi	at,at,0x2
2c:	10200008 	beqz	at,50 <bbit0i32+0x50>
30:	00000000 	nop
34:	df810000 	ld	at,0(gp)
38:	64240000 	daddiu	a0,at,0
3c:	3c010000 	lui	at,0x0
40:	003c082d 	daddu	at,at,gp
44:	dc390000 	ld	t9,0(at)
48:	0320f809 	jalr	t9
4c:	00000000 	nop
50:	dfbc0000 	ld	gp,0(sp)
54:	dfbf0008 	ld	ra,8(sp)
58:	03e00008 	jr	ra
5c:	67bd0010 	daddiu	sp,sp,16

With the patch:

0000000000000000 <bbit0i32>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	0039082d 	daddu	at,at,t9
14:	643c0000 	daddiu	gp,at,0
18:	3c010000 	lui	at,0x0
1c:	003c082d 	daddu	at,at,gp
20:	dc210000 	ld	at,0(at)
24:	90210007 	lbu	at,7(at)
28:	c8210008 	bbit0	at,0x1,4c <bbit0i32+0x4c>
2c:	00000000 	nop
30:	df810000 	ld	at,0(gp)
34:	64240000 	daddiu	a0,at,0
38:	3c010000 	lui	at,0x0
3c:	003c082d 	daddu	at,at,gp
40:	dc390000 	ld	t9,0(at)
44:	0320f809 	jalr	t9
48:	00000000 	nop
4c:	dfbc0000 	ld	gp,0(sp)
50:	dfbf0008 	ld	ra,8(sp)
54:	03e00008 	jr	ra
58:	67bd0010 	daddiu	sp,sp,16

Diff Detail

Repository
rL LLVM

Event Timeline

spetrovic created this revision.Aug 2 2017, 7:54 AM
Herald added a subscriber: arichardson. · View Herald TranscriptAug 2 2017, 7:54 AM
spetrovic updated this revision to Diff 109353.Aug 2 2017, 7:56 AM
spetrovic retitled this revision from [MIPS] Add support to match more patterns for DINS instruction. to [MIPS] Add support to match more patterns for BBIT instruction..
sdardis edited edge metadata.Aug 2 2017, 8:11 AM
sdardis added a subscriber: llvm-commits.

Don't forget to add llvm-commits when posting.

sdardis added a comment.Aug 3 2017, 4:05 AM

The approach here is somewhat overly verbose and can be dramatically simplified:

def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)),
                       bb:$dst),
              (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
                     (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;

achieves the same result without having to define new instructions and the relevant branch analysis. Can you use that approach rather than defining codegen only instructions?

sdardis added a comment.Aug 3 2017, 4:14 AM

Also, can you simplify the test cases to call some external function such as "void g(void)" ?

spetrovic updated this revision to Diff 109726.Aug 4 2017, 7:07 AM

Comments addressed.

sdardis accepted this revision.Aug 10 2017, 9:04 AM

LGTM with inline nits addressed.

lib/Target/Mips/Mips64InstrInfo.td
64 ↗(On Diff #109726)

Use isUInt<32>(Imm) here.

test/CodeGen/Mips/octeon.ll
186 ↗(On Diff #109726)

This needs ALL-LABEL: bbit0i32:

204 ↗(On Diff #109726)

This needs ALL-LABEL: bbit0i32:

This revision is now accepted and ready to land.Aug 10 2017, 9:04 AM
spetrovic updated this revision to Diff 112887.Aug 28 2017, 6:14 AM

Comments addressed.

Closed by commit rL312111: [MIPS] Add support to match more patterns for BBIT instruction (authored by spetrovic). · Explain WhyAug 30 2017, 4:26 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
15 lines
test/
CodeGen/
Mips/
56 lines

Diff 113239

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesdef PowerOf2HI : PatLeaf<(imm), [{
if (N->getValueType(0) == MVT::i64) { if (N->getValueType(0) == MVT::i64) {
uint64_t Imm = N->getZExtValue(); uint64_t Imm = N->getZExtValue();
return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
} }
else else
return false; return false;
}]>; }]>;
def PowerOf2LO_i32 : PatLeaf<(imm), [{
if (N->getValueType(0) == MVT::i32) {
uint64_t Imm = N->getZExtValue();
return isPowerOf2_32(Imm) && isUInt<32>(Imm);
}
else
return false;
}]>;
def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
}]>; }]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions specific format // Instructions specific format
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
▲ Show 20 Lines • Show All 635 Lines • ▼ Show 20 Lines
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
(BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
(Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst),
(BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32),
(Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
// Atomic load patterns. // Atomic load patterns.
def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>; def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>; def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>; def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
// Atomic store patterns. // Atomic store patterns.
▲ Show 20 Lines • Show All 229 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/octeon.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines; MIPS64: beqz $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
%res = icmp ne i64 %bit, 0 %res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if br i1 %res, label %endif, label %if
if: if:
ret i64 48 ret i64 48
endif: endif:
ret i64 12 ret i64 12
} }
; extern void foo(void);
; long long var = 7;
; void bbit0i32 () {
; if ((var & 0x2)) {
; foo();
; }
; }
;
; void bbit1i32() {
; if (!(var & 0x2)) {
; foo();
; }
; }
@var = local_unnamed_addr global i64 7, align 8
define void @bbit0i32() local_unnamed_addr {
entry:
; ALL-LABEL: bbit0i32:
; OCTEON: bbit0 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
%0 = load i64, i64* @var, align 8
%and = and i64 %0, 2
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
tail call void @foo() #2
br label %if.end
if.end: ; preds = %entry, %if.then
ret void
}
declare void @foo() local_unnamed_addr
define void @bbit1i32() local_unnamed_addr {
entry:
; ALL-LABEL: bbit1i32:
; OCTEON: bbit1 $1, 1, [[BB0:(\$|\.L)BB[0-9_]+]]
; OCTEON-PIC-NOT: b {{[[:space:]].*}}
; OCTEON-NOT: j {{[[:space:]].*}}
%0 = load i64, i64* @var, align 8
%and = and i64 %0, 2
%tobool = icmp eq i64 %and, 0
br i1 %tobool, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @foo() #2
br label %if.end
if.end: ; preds = %entry, %if.then
ret void
}