Add "Restored" flag to CalleeSavedInfo

[kparzysz]

Summary

This version should now be restricted to the fix for the liveness of LR.

This is a follow-up to this thread:
http://lists.llvm.org/pipermail/llvm-dev/2017-July/115909.html

This patch has a few things packed together and is not really intended to be in the final form, but to demonstrate the approach for now.

The original issue was with the tail merging leaving inconsistent liveness information around. That is addressed in this patch by adding IMPLICIT_DEFs where needed. LivePhysRegs is used to determine whether something is a live-in to a block, and here's where the remaining 90% of this patch comes from:
On ARM, if MBB is a return block, LivePhysRegs will add LR to its live-ins, if LR is in CalleeSavedInfo. It does that for each register in CSI because the assumption is that if something is saved and restored, then it is live outside of the function. The problem with LR is that it is not restored (in many cases) and so it doesn't need to be treated as a live-out from the function, and subsequently as a live-in to the return block. In tail merging, having it as a live-in to a block caused IMPLICIT_DEFs defining LR to appear in some predecessors, which then prevented certain macro-fusion-like optimizations (merging cmp with a branch) from happening later on.

The approach to deal with it taken here is to add a field in CalleeSavedInfo indicating that the saved register is actually restored. It is set to "true" by default, and target's implementation of restoreCalleeSavedRegisters should only reset it to "false" when the register is not restored. Currently, this only applies to LR on ARM. This has the consequence that the CSI parameter is no longer "const", which is not something I'm a fan of. LivePhysRegs is the user of that information when it adds block live-outs.

[efriedma]

Fundamentally, the problem with LR on ARM is that it isn't really a callee-save register. We just pretend it's callee-save to avoid explicitly tracking its lifetime throughout the function. Actually, ARM isn't the only architecture that does this; the weird part about ARM is that it has the instruction "pop {pc}" (which loads the return address directly from the stack, without loading it back into LR).

If we are going to add a marking to CalleeSavedInfo, it would probably be better to add it in assignCalleeSavedSpillSlots, where we construct the CalleeSavedInfo, rather than waiting until restoreCalleeSavedRegisters.

[kparzysz]

In D36160#827796, @efriedma wrote:

If we are going to add a marking to CalleeSavedInfo, it would probably be better to add it in assignCalleeSavedSpillSlots, where we construct the CalleeSavedInfo, rather than waiting until restoreCalleeSavedRegisters.

The problem is that restoreCalleeSavedRegisters decides whether to use a pop instruction or not, which determines whether LR is restored, or loaded into PC directly. Are you suggesting moving some of that logic into assignCalleeSavedSpillSlots?

[efriedma]

Oh, I see what you mean... we don't actually decide whether to "pop {pc}" until ARMFrameLowering::emitPopInst. Actually, there's another potential problem there: if shrink-wrapping ever allows emitting multiple epilogues (D36109 etc.), we might not make the same decision for each epilogue.

Long-term, it might be more straightforward to add implicit uses to return instructions, similar to the way we add implicit defs to calls, so we don't have to make return blocks a special case in LivePhysRegs. Not sure how hard that would be.

[kparzysz]

In D36160#827859, @efriedma wrote:

Long-term, it might be more straightforward to add implicit uses to return instructions, similar to the way we add implicit defs to calls, so we don't have to make return blocks a special case in LivePhysRegs. Not sure how hard that would be.

There is a review for that as well (D33003), and it ran into the same problem. It adds all registers that are live-out from the function to the return instructions (except those which are defined by the return instruction itself). The problem is that it again uses CSI to determine for which registers such implicit uses need to be created, and again LR causes trouble: since the return instruction (pop) doesn't restore it, the code will assume that it must have been restored prior to the return and add an implicit use of LR to the return. That, in turn, is a problem since LR remains undefined (clobbered).

[qcolombet]

Long-term, it might be more straightforward to add implicit uses to return instructions, similar to the way we add implicit defs to calls, so we don't have to make return blocks a special case in LivePhysRegs. Not sure how hard that would be.

Like Eli said if we could model LR properly that would be the best. That being said, I don't know what it will take to do that.

My guts say we should make the frame lowering logic more complex than it is already.

[efriedma]

Oh, I see what you mean... we don't actually decide whether to "pop {pc}" until ARMFrameLowering::emitPopInst.

Wait, that's not right; we don't need to include lr in the list of live-outs either way. If we generate "pop {pc}", lr isn't used; if we generate "bx lr", the explicit use of lr should allow us to generate correct liveness.

[qcolombet]

My guts say we should make the frame lowering logic more complex than it is already.

*shouldn't

[kparzysz]

In D36160#827939, @efriedma wrote:

Wait, that's not right; we don't need to include lr in the list of live-outs either way. If we generate "pop {pc}", lr isn't used; if we generate "bx lr", the explicit use of lr should allow us to generate correct liveness.

The problem is that currently the return instructions don't carry any live-out information that is associated with callee-saved registers. LivePhysRegs needs to know that information, because CS registers need to be treated as live between the restore point and the exit from the function. It uses CalleeSavedInfo to get that data, which leads it to believe that LR is live at the return. If the return instruction uses LR explicitly (bx lr), this will have been already expressed in liveness, but if it's a "pop", it won't be. Still, LivePhysRegs will think that LR is live at the return and we end up with a problem.

[efriedma]

The point I was trying to make is that we should always exclude LR from the set of registers added by addLiveOutsNoPristines: whether or not we actually convert the "bx lr" into a "pop", it isn't live out of the function, and we don't need to model it that way. So assignCalleeSavedSpillSlots wouldn't need any special logic to figure that out.

[kparzysz]

In D36160#828176, @efriedma wrote:

The point I was trying to make is that we should always exclude LR from the set of registers added by addLiveOutsNoPristines: whether or not we actually convert the "bx lr" into a "pop", it isn't live out of the function, and we don't need to model it that way. So assignCalleeSavedSpillSlots wouldn't need any special logic to figure that out.

Ah, I see. However, if we want to support multiple save/restore points with different sets of registers, this patch may not help. If we kept track of what registers were saved/restored in which block, it would make things a lot easier.

[kparzysz]

I think the problem is that LR is not really a callee-saved register in the sense that it doesn't need to (and isn't) preserved across function calls. It is still included in the save lists returned by getCalleeSavedRegs. Would it make sense to change the ARM backend to remove it from these lists?

[kparzysz]

In D36160#828176, @efriedma wrote:

The point I was trying to make is that we should always exclude LR from the set of registers added by addLiveOutsNoPristines: whether or not we actually convert the "bx lr" into a "pop", it isn't live out of the function, and we don't need to model it that way. So assignCalleeSavedSpillSlots wouldn't need any special logic to figure that out.

If we remove LR from CSI in assignCalleeSavedSpillSlots, it won't be saved, and the updateLiveness function won't add it to block live-ins. On the other hand, if LR remains in CSI, addLiveOutsNoPristines will add it to the set it returns. At the moment BX_RET is not marked as using LR, so that is not keeping LR live, when I add implicit use or LR to BX_RET, the verifier fails even before register allocation, since LR is not reserved and it expects the live-ins for LR to be correct from the start.

[efriedma]

What happens if we keep the setRestored() hack, but move the ARM-specific code to call setRestored() on LR into assignCalleeSavedSpillSlots?

Long-term, the solution is probably to remove LR from CSI, make it an explicit operand of BX_RET/tail calls, and fix up prologue/epilogue lowering to do the right thing... but it's a much larger/trickier patch.

[efriedma]

What happens if we keep the setRestored() hack, but move the ARM-specific code to call setRestored() on LR into assignCalleeSavedSpillSlots?

Oh, nevermind, that'll blow up because BX_RET doesn't actually use LR.

---

Ultimately, yes, we should stop modeling LR as callee-save, but it's probably a pretty big patch to deal with all the implications (all the various return and tail-call instructions would need to be changed, and we probably need some special handling to make sure LR lands in the right place in the stack frame for stack walking code). I guess this patch isn't too evil in the meantime.

[MatzeB]

Thanks for working on this!

1. The BranchFolding changes: I've got some issue with the current approach, see below.

2. Adding the Restored bit to CSI:

• Very interesting observations!
• Can we split this change into a separate patch?
• I think the proposed change is fine as it fixes a problem with the system we have today (under the condition that you add more comments).

My long/in an ideal world:
I find the code in LivePhysRegs::addLiveOuts() and LiveRegUntis::addLiveOuts() that queries CSI on return blocks is accidental complexity that should not be there. The CSI list should be an implementation detail of the prolog epilogue inserter and disappear after that pass is done. We should be able to model things perfectly well by adding implicit uses to the return instructions; It should be equally natural to not add the implicit use of LR to pop {pc} then.

include/llvm/CodeGen/MachineFrameInfo.h

31–45 ↗

(On Diff #109140)

The discussion here clearly shows that Restored is an unintuitive concept, so we need comments to explain it in detail!

671 ↗

(On Diff #109140)

You could use /// \copydoc getCalleeSavedInfo() here.

lib/CodeGen/BranchFolding.cpp

241–253 ↗

(On Diff #109140)

• Why do you need this, given there is already LivePhysRegs::addLiveOuts()/LivePhysRegs::addLiveOutsNoPristines(). If there is a reason, then this needs a comment explaining it.
• We are working on deprecating kill-flags. This means introducing new uses of stepForward() is bad as the results will be better/worse depending on kill-flag accuracy.
• (Unrelated to this patch: I didn't realize you have to manually remove dead defs from the LiveOut set like this, I really think stepForward() should already do this for you and should be fixed accordingly)

[kparzysz]

Created D36415 for the branch folding issue. It needs the LR issue addressed, or otherwise two ARM testcases will fail.

[kparzysz]

Clean up the patch, move the branch folding part into a separate review.

[kparzysz]

Added comments as requested by Matthias.

llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h

 class BitVector;
 class AllocaInst;
 
 /// The CalleeSavedInfo class tracks the information need to locate where a
 /// callee saved register is in the current frame.
 class CalleeSavedInfo {
   unsigned Reg;
   int FrameIdx;
+  /// Flag indicating whether the register is actually restored in the epilog.
+  /// In most cases, if a register is saved, it is also restored. There are
+  /// some situations, though, when this is not the case. For example, the
+  /// LR register on ARM is usually saved, but on exit from the function its
+  /// saved value may be loaded directly into PC. Since liveness tracking of
+  /// physical registers treats callee-saved registers are live outside of
+  /// the function, LR would be treated as live-on-exit, even though in these
+  /// scenarios it is not. This flag is added to indicate that the saved
+  /// register described by this object is not restored in the epilog.
+  /// The long-term solution is to model the liveness of callee-saved registers
+  /// by implicit uses on the return instructions, however, the required
+  /// changes in the ARM backend would be quite extensive.
+  bool Restored;
 
 public:
   explicit CalleeSavedInfo(unsigned R, int FI = 0)
-  : Reg(R), FrameIdx(FI) {}
+  : Reg(R), FrameIdx(FI), Restored(true) {}
 
   // Accessors.
   unsigned getReg()                        const { return Reg; }
   int getFrameIdx()                        const { return FrameIdx; }
   void setFrameIdx(int FI)                       { FrameIdx = FI; }
+  bool isRestored()                        const { return Restored; }
+  void setRestored(bool R)                       { Restored = R; }
 };
 
 /// The MachineFrameInfo class represents an abstract stack frame until
 /// prolog/epilog code is inserted.  This class is key to allowing stack frame
 /// representation optimizations, such as frame pointer elimination.  It also
 /// allows more mundane (but still important) optimizations, such as reordering
 /// of abstract objects on the stack frame.
 ///
public:
   /// created.  This must be created whenever a variable sized object is
   /// created, whether or not the index returned is actually used.
   int CreateVariableSizedObject(unsigned Alignment, const AllocaInst *Alloca);
 
   /// Returns a reference to call saved info vector for the current function.
   const std::vector<CalleeSavedInfo> &getCalleeSavedInfo() const {
     return CSInfo;
   }
+  /// \copydoc getCalleeSavedInfo()
+  std::vector<CalleeSavedInfo> &getCalleeSavedInfo() { return CSInfo; }
 
   /// Used by prolog/epilog inserter to set the function's callee saved
   /// information.
   void setCalleeSavedInfo(const std::vector<CalleeSavedInfo> &CSI) {
     CSInfo = CSI;
   }
 
   /// Has the callee saved info been calculated yet?

llvm/trunk/include/llvm/Target/TargetFrameLowering.h

virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         const std::vector<CalleeSavedInfo> &CSI,
                                          const TargetRegisterInfo *TRI) const {
     return false;
   }
 
   /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
   /// saved registers and returns true if it isn't possible / profitable to do
   /// so by issuing a series of load instructions via loadRegToStackSlot().
+  /// If it returns true, and any of the registers in CSI is not restored,
+  /// it sets the corresponding Restored flag in CSI to false.
   /// Returns false otherwise.
   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                           std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
     return false;
   }
 
   /// Return true if the target needs to disable frame pointer elimination.
   virtual bool noFramePointerElim(const MachineFunction &MF) const;
 
   /// hasFP - Return true if the specified function should have a dedicated

llvm/trunk/lib/CodeGen/LivePhysRegs.cpp

void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
   } else if (MBB.isReturnBlock()) {
     // For the return block: Add all callee saved registers that are saved and
     // restored (somewhere); This does not include callee saved registers that
     // are unused and hence not saved and restored; they are called pristine.
     const MachineFunction &MF = *MBB.getParent();
     const MachineFrameInfo &MFI = MF.getFrameInfo();
     if (MFI.isCalleeSavedInfoValid()) {
       for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
+        if (Info.isRestored())
           addReg(Info.getReg());
     }
   }
 }
 
 void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
   if (!MBB.succ_empty()) {
     addPristines(*this, MF);

llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp

for (const CalleeSavedInfo &CS : CSI) {
       TII.storeRegToStackSlot(SaveBlock, I, Reg, true, CS.getFrameIdx(), RC,
                               TRI);
     }
   }
 }
 
 /// Insert restore code for the callee-saved registers used in the function.
 static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
-                              ArrayRef<CalleeSavedInfo> CSI) {
+                              std::vector<CalleeSavedInfo> &CSI) {
   MachineFunction &Fn = *RestoreBlock.getParent();
   const TargetInstrInfo &TII = *Fn.getSubtarget().getInstrInfo();
   const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
   const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
 
   // Restore all registers immediately before the return and any
   // terminators that precede it.
   MachineBasicBlock::iterator I = RestoreBlock.getFirstTerminator();
static void doSpillCalleeSavedRegs(MachineFunction &Fn, RegScavenger *RS,
 
   // Assign stack slots for any callee-saved registers that must be spilled.
   assignCalleeSavedSpillSlots(Fn, SavedRegs, MinCSFrameIndex, MaxCSFrameIndex);
 
   // Add the code to save and restore the callee saved registers.
   if (!F->hasFnAttribute(Attribute::Naked)) {
     MFI.setCalleeSavedInfoValid(true);
 
-    ArrayRef<CalleeSavedInfo> CSI = MFI.getCalleeSavedInfo();
+    std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
     if (!CSI.empty()) {
       for (MachineBasicBlock *SaveBlock : SaveBlocks) {
         insertCSRSaves(*SaveBlock, CSI);
         // Update the live-in information of all the blocks up to the save
         // point.
         updateLiveness(Fn);
       }
       for (MachineBasicBlock *RestoreBlock : RestoreBlocks)

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.h

int resolveFrameIndexReference(const MachineFunction &MF, int FI,
                                  bool PreferFP = false) const;
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   /// \brief Can this function use the red zone for local allocations.
   bool canUseRedZone(const MachineFunction &MF) const;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 

llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

MIB.addMemOperand(MF.getMachineMemOperand(
         MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
         MachineMemOperand::MOStore, 8, 8));
   }
   return true;
 }
 
 bool AArch64FrameLowering::restoreCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-    const std::vector<CalleeSavedInfo> &CSI,
+    std::vector<CalleeSavedInfo> &CSI,
     const TargetRegisterInfo *TRI) const {
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   DebugLoc DL;
   SmallVector<RegPairInfo, 8> RegPairs;
 
   if (MI != MBB.end())
     DL = MI->getDebugLoc();

llvm/trunk/lib/Target/ARM/ARMFrameLowering.h

public:
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool noFramePointerElim(const MachineFunction &MF) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
   int getFrameIndexReference(const MachineFunction &MF, int FI,

 
  private:
   void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                     const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
                     unsigned StrOpc, bool NoGap,
                     bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs,
                     unsigned MIFlags = 0) const;
   void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-                   const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,
+                   std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,
                    unsigned LdrOpc, bool isVarArg, bool NoGap,
                    bool(*Func)(unsigned, bool),
                    unsigned NumAlignedDPRCS2Regs) const;
 
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;
 };
 
 } // End llvm namespace
 
 #endif

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

while (i != 0) {
     // monotonicity.
     if (MI != MBB.begin())
       --MI;
   }
 }
 
 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
-                                   const std::vector<CalleeSavedInfo> &CSI,
+                                   std::vector<CalleeSavedInfo> &CSI,
                                    unsigned LdmOpc, unsigned LdrOpc,
                                    bool isVarArg, bool NoGap,
                                    bool(*Func)(unsigned, bool),
                                    unsigned NumAlignedDPRCS2Regs) const {
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
while (i != 0) {
     });
 
     if (Regs.size() > 1 || LdrOpc == 0) {
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
                                     .addReg(ARM::SP)
                                     .add(predOps(ARMCC::AL));
       for (unsigned i = 0, e = Regs.size(); i < e; ++i)
         MIB.addReg(Regs[i], getDefRegState(true));
-      if (DeleteRet && MI != MBB.end()) {
+      if (DeleteRet) {
+        if (MI != MBB.end()) {
           MIB.copyImplicitOps(*MI);
           MI->eraseFromParent();
         }
+        // If LR is not restored, mark it in CSI.
+        for (CalleeSavedInfo &I : CSI) {
+          if (I.getReg() != ARM::LR)
+            continue;
+          I.setRestored(false);
+          break;
+        }
+      }
       MI = MIB;
     } else if (Regs.size() == 1) {
       // If we adjusted the reg to PC from LR above, switch it back here. We
       // only do that for LDM.
       if (Regs[0] == ARM::PC)
         Regs[0] = ARM::LR;
       MachineInstrBuilder MIB =
         BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
   if (NumAlignedDPRCS2Regs)
     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
 
   return true;
 }
 
 bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                        std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   MachineFunction &MF = *MBB.getParent();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
   unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();

llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h

public:
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;

llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp

spillCalleeSavedRegisters(MachineBasicBlock &MBB,
   }
 
   return true;
 }
 
 bool Thumb1FrameLowering::
 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
-                            const std::vector<CalleeSavedInfo> &CSI,
+                            std::vector<CalleeSavedInfo> &CSI,
                             const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   MachineFunction &MF = *MBB.getParent();
   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
   const TargetInstrInfo &TII = *STI.getInstrInfo();
   const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(

llvm/trunk/lib/Target/AVR/AVRFrameLowering.h

public:
   bool hasFP(const MachineFunction &MF) const override;
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
   bool
   restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MI,
-                              const std::vector<CalleeSavedInfo> &CSI,
+                              std::vector<CalleeSavedInfo> &CSI,
                               const TargetRegisterInfo *TRI) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS = nullptr) const override;
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_AVR_FRAME_LOWERING_H

llvm/trunk/lib/Target/AVR/AVRFrameLowering.cpp

bool AVRFrameLowering::spillCalleeSavedRegisters(
 
   AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
 
   return true;
 }
 
 bool AVRFrameLowering::restoreCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
-    const std::vector<CalleeSavedInfo> &CSI,
+    std::vector<CalleeSavedInfo> &CSI,
     const TargetRegisterInfo *TRI) const {
   if (CSI.empty()) {
     return false;
   }
 
   DebugLoc DL = MBB.findDebugLoc(MI);
   const MachineFunction &MF = *MBB.getParent();
   const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();

llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.h

public:
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
       MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
       const TargetRegisterInfo *TRI) const override {
     return true;
   }
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-      MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
+      MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI,
       const TargetRegisterInfo *TRI) const override {
     return true;
   }
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override {
     // We always reserve call frame as a part of the initial stack allocation.
     return true;
   }

llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h

eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                      RegScavenger *RS = nullptr) const override;
 };
 
 } // End llvm namespace
 
 #endif

llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp

BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
       .addReg(Reg, RegState::Kill);
   }
   return true;
 }
 
 bool
 MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                                  MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                        std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   DebugLoc DL;
   if (MI != MBB.end()) DL = MI->getDebugLoc();
 
   MachineFunction &MF = *MBB.getParent();

llvm/trunk/lib/Target/Mips/Mips16FrameLowering.h

public:
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 };
 
 } // End llvm namespace
 
 #endif

llvm/trunk/lib/Target/Mips/Mips16FrameLowering.cpp

if (!IsRAAndRetAddrIsTaken)
       EntryBlock->addLiveIn(Reg);
   }
 
   return true;
 }
 
 bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MI,
-                                       const std::vector<CalleeSavedInfo> &CSI,
+                                       std::vector<CalleeSavedInfo> &CSI,
                                        const TargetRegisterInfo *TRI) const {
   //
   // Registers RA,S0,S1 are the callee saved registers and they will be restored
   // with the restore instruction during emitEpilogue.
   // We need to override this virtual function, otherwise llvm will try and
   // restore the registers on it's on from the stack.
   //
 

llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  const TargetRegisterInfo *TRI) const override;
 
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   /// targetHandlesStackFrameRounding - Returns true if the target is
   /// responsible for rounding up the stack frame (probably at emitPrologue
   /// time).
   bool targetHandlesStackFrameRounding() const override { return true; }
 
   /// getReturnSaveOffset - Return the previous frame offset to save the

llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp

eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
   }
   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
   return MBB.erase(I);
 }
 
 bool
 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                        std::vector<CalleeSavedInfo> &CSI,
                                         const TargetRegisterInfo *TRI) const {
 
   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
   // Return false otherwise to maintain pre-existing behavior.
   if (!Subtarget.isSVR4ABI())
     return false;
 
   MachineFunction *MF = MBB.getParent();

llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h

public:
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBII,
-                                   const std::vector<CalleeSavedInfo> &CSI,
+                                   std::vector<CalleeSavedInfo> &CSI,
                                    const TargetRegisterInfo *TRI) const
     override;
   void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                            RegScavenger *RS) const override;
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   bool hasFP(const MachineFunction &MF) const override;
   int getFrameIndexReference(const MachineFunction &MF, int FI,

llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp

spillCalleeSavedRegisters(MachineBasicBlock &MBB,
   }
 
   return true;
 }
 
 bool SystemZFrameLowering::
 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
-                            const std::vector<CalleeSavedInfo> &CSI,
+                            std::vector<CalleeSavedInfo> &CSI,
                             const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
   SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
   bool HasFP = hasFP(MF);

llvm/trunk/lib/Target/X86/X86FrameLowering.h

public:
 
   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
   bool needsFrameIndexResolution(const MachineFunction &MF) const override;
 
   int getFrameIndexReference(const MachineFunction &MF, int FI,

llvm/trunk/lib/Target/X86/X86FrameLowering.cpp

for (unsigned i = CSI.size(); i != 0; --i) {
     ++MI;
   }
 
   return true;
 }
 
 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                                MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                          std::vector<CalleeSavedInfo> &CSI,
                                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;
 
   if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
     // Don't restore CSRs in 32-bit EH funclets. Matches
     // spillCalleeSavedRegisters.
     if (STI.is32Bit())

llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h

void emitEpilogue(MachineFunction &MF,
                       MachineBasicBlock &MBB) const override;
 
     bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
                                   const std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
     bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
-                                  const std::vector<CalleeSavedInfo> &CSI,
+                                  std::vector<CalleeSavedInfo> &CSI,
                                   const TargetRegisterInfo *TRI) const override;
 
     MachineBasicBlock::iterator
     eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) const override;
 
     bool hasFP(const MachineFunction &MF) const override;
 

llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp

for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
     }
   }
   return true;
 }
 
 bool XCoreFrameLowering::
 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
-                            const std::vector<CalleeSavedInfo> &CSI,
+                            std::vector<CalleeSavedInfo> &CSI,
                             const TargetRegisterInfo *TRI) const{
   MachineFunction *MF = MBB.getParent();
   const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
   bool AtStart = MI == MBB.begin();
   MachineBasicBlock::iterator BeforeI = MI;
   if (!AtStart)
     --BeforeI;
   for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();