Index: lib/Target/AMDGPU/AMDGPU.td =================================================================== --- lib/Target/AMDGPU/AMDGPU.td +++ lib/Target/AMDGPU/AMDGPU.td @@ -79,6 +79,12 @@ "Have scratch_* flat memory instructions" >; +def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts", + "AddNoCarryInsts", + "true", + "Have VALU add/sub instructions without carry out" +>; + def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access", "UnalignedBufferAccess", "true", @@ -464,7 +470,8 @@ FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode, FeatureFastFMAF32, FeatureDPP, FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst, - FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts + FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts, + FeatureAddNoCarryInsts ] >; @@ -682,6 +689,11 @@ AssemblerPredicate<"FeatureFlatGlobalInsts">; def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">, AssemblerPredicate<"FeatureFlatScratchInsts">; +def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">, + AssemblerPredicate<"FeatureAddNoCarryInsts">; + +def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">, + AssemblerPredicate<"!FeatureAddNoCarryInsts">; def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">, AssemblerPredicate<"Feature16BitInsts">; Index: lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.h +++ lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -159,6 +159,7 @@ bool FlatInstOffsets; bool FlatGlobalInsts; bool FlatScratchInsts; + bool AddNoCarryInsts; bool R600ALUInst; bool CaymanISA; bool CFALUBug; @@ -419,6 +420,10 @@ return FlatScratchInsts; } + bool hasAddNoCarry() const { + return AddNoCarryInsts; + } + bool isMesaKernel(const MachineFunction &MF) const { return isMesa3DOS() && !AMDGPU::isShader(MF.getFunction()->getCallingConv()); } Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -167,6 +167,7 @@ FlatInstOffsets(false), FlatGlobalInsts(false), FlatScratchInsts(false), + AddNoCarryInsts(false), R600ALUInst(false), CaymanISA(false), Index: lib/Target/AMDGPU/SIInstructions.td =================================================================== --- lib/Target/AMDGPU/SIInstructions.td +++ lib/Target/AMDGPU/SIInstructions.td @@ -1300,8 +1300,43 @@ // Assembler aliases //============================================================================// +multiclass NoCarryAlias { + def : InstAlias, + Requires<[HasAddNoCarryInsts]>; + + def : InstAlias, + Requires<[HasAddNoCarryInsts]>; + + def : InstAlias, + Requires<[HasAddNoCarryInsts]>; + + def : InstAlias, + Requires<[HasAddNoCarryInsts]>; +} + +// gfx9 made a mess of add instruction names. The existing add +// instructions add _co added to the names, and their old names were +// repurposed to a version without carry out. +let Predicates = [HasAddNoCarryInsts] in { +defm : NoCarryAlias<"v_add_u32", V_ADD_U32_e32_vi, V_ADD_U32_e64_vi, + V_ADD_I32_e32_vi, V_ADD_I32_e64_vi>; +defm : NoCarryAlias<"v_sub_u32", V_SUB_U32_e32_vi, V_SUB_U32_e64_vi, + V_SUB_I32_e32_vi, V_SUB_I32_e64_vi>; +defm : NoCarryAlias<"v_subrev_u32", + V_SUBREV_U32_e32_vi, V_SUBREV_U32_e64_vi, + V_SUBREV_I32_e32_vi, V_SUBREV_I32_e64_vi>; +} + +let Predicates = [NotHasAddNoCarryInsts] in { def : MnemonicAlias<"v_add_u32", "v_add_i32">; def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; +} } // End isGCN predicate Index: lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP2Instructions.td +++ lib/Target/AMDGPU/VOP2Instructions.td @@ -375,6 +375,14 @@ defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>; defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>; defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">; + + +let SubtargetPredicate = HasAddNoCarryInsts in { +defm V_ADD_U32 : VOP2Inst <"v_add_u32", VOP_I32_I32_I32>; +defm V_SUB_U32 : VOP2Inst <"v_sub_u32", VOP_I32_I32_I32>; +defm V_SUBREV_U32 : VOP2Inst <"v_subrev_u32", VOP_I32_I32_I32, null_frag, "v_sub_u32">; +} + } // End isCommutable = 1 // These are special and do not read the exec mask. @@ -833,3 +841,9 @@ def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; } // End SubtargetPredicate = isVI + +let SubtargetPredicate = HasAddNoCarryInsts in { +defm V_ADD_U32 : VOP2_Real_e32e64_vi <0x34>; +defm V_SUB_U32 : VOP2_Real_e32e64_vi <0x35>; +defm V_SUBREV_U32 : VOP2_Real_e32e64_vi <0x36>; +} Index: test/MC/AMDGPU/add-sub-no-carry.s =================================================================== --- /dev/null +++ test/MC/AMDGPU/add-sub-no-carry.s @@ -0,0 +1,104 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefixes=GCN,GFX9 %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck -check-prefixes=GCN,VI %s + +// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck -check-prefixes=ERR-SICIVI %s +// FIXME: pre-gfx9 errors should be more useful + + +// FIXME: These should parse to VOP2 encoding +v_add_u32 v1, v2, v3 +// GFX9: v_add_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x07,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_add_u32 v1, v2, s1 +// GFX9: v_add_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0x03,0x00,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_add_u32 v1, s1, v2 +// GFX9: v_add_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x34,0xd1,0x01,0x04,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_add_u32 v1, 4.0, v2 +// GFX9: v_add_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x34,0xd1,0xf6,0x04,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_add_u32 v1, v2, 4.0 +// GFX9: v_add_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x34,0xd1,0x02,0xed,0x01,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_add_u32_e32 v1, v2, v3 +// GFX9: v_add_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x68] +// ERR-SICIVI: :19: error: invalid operand for instruction + +v_add_u32_e32 v1, s1, v3 +// GFX9: v_add_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x68] +// ERR-SICIVI: :19: error: invalid operand for instruction + + + +v_sub_u32 v1, v2, v3 +// GFX9: v_sub_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x07,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_sub_u32 v1, v2, s1 +// GFX9: v_sub_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0x03,0x00,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_sub_u32 v1, s1, v2 +// GFX9: v_sub_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x35,0xd1,0x01,0x04,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_sub_u32 v1, 4.0, v2 +// GFX9: v_sub_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x35,0xd1,0xf6,0x04,0x02,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_sub_u32 v1, v2, 4.0 +// GFX9: v_sub_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x35,0xd1,0x02,0xed,0x01,0x00] +// ERR-SICIVI: :15: error: invalid operand for instruction + +v_sub_u32_e32 v1, v2, v3 +// GFX9: v_sub_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6a] +// ERR-SICIVI: :19: error: invalid operand for instruction + +v_sub_u32_e32 v1, s1, v3 +// GFX9: v_sub_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6a] +// ERR-SICIVI: :19: error: invalid operand for instruction + + + +v_subrev_u32 v1, v2, v3 +// GFX9: v_subrev_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x07,0x02,0x00] +// ERR-SICIVI: :18: error: invalid operand for instruction + +v_subrev_u32 v1, v2, s1 +// GFX9: v_subrev_u32_e64 v1, v2, s1 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0x03,0x00,0x00] +// ERR-SICIVI: :18: error: invalid operand for instruction + +v_subrev_u32 v1, s1, v2 +// GFX9: v_subrev_u32_e64 v1, s1, v2 ; encoding: [0x01,0x00,0x36,0xd1,0x01,0x04,0x02,0x00] +// ERR-SICIVI: :18: error: invalid operand for instruction + +v_subrev_u32 v1, 4.0, v2 +// GFX9: v_subrev_u32_e64 v1, 4.0, v2 ; encoding: [0x01,0x00,0x36,0xd1,0xf6,0x04,0x02,0x00] +// ERR-SICIVI: :18: error: invalid operand for instruction + +v_subrev_u32 v1, v2, 4.0 +// GFX9: v_subrev_u32_e64 v1, v2, 4.0 ; encoding: [0x01,0x00,0x36,0xd1,0x02,0xed,0x01,0x00] +// ERR-SICIVI: :18: error: invalid operand for instruction + +v_subrev_u32_e32 v1, v2, v3 +// GFX9: v_subrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x6c] +// ERR-SICIVI: :22: error: invalid operand for instruction + +v_subrev_u32_e32 v1, s1, v3 +// GFX9: v_subrev_u32_e32 v1, s1, v3 ; encoding: [0x01,0x06,0x02,0x6c] +// ERR-SICIVI: :22: error: invalid operand for instruction + + + +v_add_u32 v1, vcc, v2, v3 +// GCN: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32] + +v_add_u32 v1, s[0:1], v2, v3 +// GCN: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]