Index: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -451,6 +451,10 @@
   case Mips::BGEZC64:  return Mips::BLTZC64;
   case Mips::BLTZC64:  return Mips::BGEZC64;
   case Mips::BLEZC64:  return Mips::BGTZC64;
+  case Mips::BBIT0:  return Mips::BBIT1;
+  case Mips::BBIT1:  return Mips::BBIT0;
+  case Mips::BBIT032:  return Mips::BBIT132;
+  case Mips::BBIT132:  return Mips::BBIT032;
   }
 }
 
@@ -541,7 +545,9 @@
           Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
           Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
           Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
-          Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
+          Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 ||
+          Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
+          Opc == Mips::BBIT132) ? Opc : 0;
 }
 
 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
Index: llvm/trunk/test/CodeGen/Mips/octeon.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/octeon.ll
+++ llvm/trunk/test/CodeGen/Mips/octeon.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
 ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
+; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
 
 define i64 @addi64(i64 %a, i64 %b) nounwind {
 entry:
@@ -88,10 +89,12 @@
   ret i64 %res2
 }
 
-define i64 @bbit0(i64 %a) nounwind {
+define i64 @bbit1(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit0:
-; OCTEON: bbit0   $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit1:
+; OCTEON: bbit1   $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
 ; MIPS64: bnez  $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
@@ -104,10 +107,12 @@
   ret i64 12
 }
 
-define i64 @bbit032(i64 %a) nounwind {
+define i64 @bbit132(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit032:
-; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit132:
+; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
@@ -122,10 +127,12 @@
   ret i64 12
 }
 
-define i64 @bbit1(i64 %a) nounwind {
+define i64 @bbit0(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit1:
-; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit0:
+; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
 ; MIPS64: beqz  $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
@@ -138,10 +145,12 @@
   ret i64 12
 }
 
-define i64 @bbit132(i64 %a) nounwind {
+define i64 @bbit032(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit132:
-; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit032:
+; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]