[GlobalISel][X86] Support G_LOAD/G_STORE i1.

[igorb]

Summary

Support G_LOAD/G_STORE i1.

[guyblank]

test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll

7 ↗

(On Diff #105757)

should there be an AND here for the truncation to i1?

[igorb]

test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll

7 ↗

(On Diff #105757)

No, truncate only drop the bits.
for reference DagISEL generate the same code

llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp

for (unsigned Op : {G_UADDE}) {
     setAction({Op, s32}, Legal);
     setAction({Op, 1, s1}, Legal);
   }
 
   for (unsigned MemOp : {G_LOAD, G_STORE}) {
     for (auto Ty : {s8, s16, s32, p0})
       setAction({MemOp, Ty}, Legal);
 
+    setAction({MemOp, s1}, WidenScalar);
     // And everything's fine in addrspace 0.
     setAction({MemOp, 1, p0}, Legal);
   }
 
   // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 
void X86LegalizerInfo::setLegalizerInfo64bit() {
   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
     for (auto Ty : {s8, s16, s32, s64})
       setAction({BinOp, Ty}, Legal);
 
   for (unsigned MemOp : {G_LOAD, G_STORE}) {
     for (auto Ty : {s8, s16, s32, s64, p0})
       setAction({MemOp, Ty}, Legal);
 
+    setAction({MemOp, s1}, WidenScalar);
     // And everything's fine in addrspace 0.
     setAction({MemOp, 1, p0}, Legal);
   }
 
   // Pointer-handling
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 

llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir

registers:
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
   - { id: 3, class: _, preferred-register: '' }
   - { id: 4, class: _, preferred-register: '' }
   - { id: 5, class: _, preferred-register: '' }
   - { id: 6, class: _, preferred-register: '' }
   - { id: 7, class: _, preferred-register: '' }
   - { id: 8, class: _, preferred-register: '' }
+  - { id: 9, class: _, preferred-register: '' }
+  - { id: 10, class: _, preferred-register: '' }
 # ALL:          %0(p0) = IMPLICIT_DEF
+# ALL-NEXT:     %11(s8) = G_LOAD %0(p0) :: (load 1)
+# ALL-NEXT:     %9(s1) = G_TRUNC %11(s8)
 # ALL-NEXT:     %1(s8) = G_LOAD %0(p0) :: (load 1)
 # ALL-NEXT:     %2(s16) = G_LOAD %0(p0) :: (load 2)
 # ALL-NEXT:     %3(s32) = G_LOAD %0(p0) :: (load 4)
 # ALL-NEXT:     %4(p0) = G_LOAD %0(p0) :: (load 8)
+# ALL-NEXT:     %10(s1) = IMPLICIT_DEF
+# ALL-NEXT:     %12(s8) = G_ZEXT %10(s1)
+# ALL-NEXT:     G_STORE %12(s8), %0(p0) :: (store 1)
 # ALL-NEXT:     %5(s8) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %5(s8), %0(p0) :: (store 1)
 # ALL-NEXT:     %6(s16) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %6(s16), %0(p0) :: (store 2)
 # ALL-NEXT:     %7(s32) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %7(s32), %0(p0) :: (store 4)
 # ALL-NEXT:     %8(p0) = IMPLICIT_DEF
 # ALL-NEXT:     G_STORE %8(p0), %0(p0) :: (store 8)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = IMPLICIT_DEF
+    %9(s1) = G_LOAD %0(p0) :: (load 1)
     %1(s8) = G_LOAD %0(p0) :: (load 1)
     %2(s16) = G_LOAD %0(p0) :: (load 2)
     %3(s32) = G_LOAD %0(p0) :: (load 4)
     %4(p0) = G_LOAD %0(p0) :: (load 8)
 
+    %10(s1) = IMPLICIT_DEF
+    G_STORE %10, %0 :: (store 1)
     %5(s8) = IMPLICIT_DEF
     G_STORE %5, %0 :: (store 1)
     %6(s16) = IMPLICIT_DEF
     G_STORE %6, %0 :: (store 2)
     %7(s32) = IMPLICIT_DEF
     G_STORE %7, %0 :: (store 4)
     %8(p0) = IMPLICIT_DEF
     G_STORE %8, %0 :: (store 8)

llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=i386-linux-gnu                       -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
 ; RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
 
 ;TODO merge with x86-64 tests (many operations not suppored yet)
 
+define i1 @test_load_i1(i1 * %p1) {
+; ALL-LABEL: test_load_i1:
+; ALL:       # BB#0:
+; ALL-NEXT:    movl 4(%esp), %eax
+; ALL-NEXT:    movb (%eax), %al
+; ALL-NEXT:    retl
+  %r = load i1, i1* %p1
+  ret i1 %r
+}
+
 define i8 @test_load_i8(i8 * %p1) {
 ; ALL-LABEL: test_load_i8:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    movl 4(%esp), %eax
 ; ALL-NEXT:    movb (%eax), %al
 ; ALL-NEXT:    retl
   %r = load i8, i8* %p1
   ret i8 %r

 ; ALL:       # BB#0:
 ; ALL-NEXT:    movl 4(%esp), %eax
 ; ALL-NEXT:    movl (%eax), %eax
 ; ALL-NEXT:    retl
   %r = load i32, i32* %p1
   ret i32 %r
 }
 
+define i1 * @test_store_i1(i1 %val, i1 * %p1) {
+; ALL-LABEL: test_store_i1:
+; ALL:       # BB#0:
+; ALL-NEXT:    movb 4(%esp), %cl
+; ALL-NEXT:    movl 8(%esp), %eax
+; ALL-NEXT:    andb $1, %cl
+; ALL-NEXT:    movb %cl, (%eax)
+; ALL-NEXT:    retl
+  store i1 %val, i1* %p1
+  ret i1 * %p1;
+}
+
 define i8 * @test_store_i8(i8 %val, i8 * %p1) {
 ; ALL-LABEL: test_store_i8:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    movb 4(%esp), %cl
 ; ALL-NEXT:    movl 8(%esp), %eax
 ; ALL-NEXT:    movb %cl, (%eax)
 ; ALL-NEXT:    retl
   store i8 %val, i8* %p1

llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-linux-gnu                       -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_FAST
 ; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_GREEDY
 
+define i1 @test_load_i1(i1 * %p1) {
+; ALL-LABEL: test_load_i1:
+; ALL:       # BB#0:
+; ALL-NEXT:    movb (%rdi), %al
+; ALL-NEXT:    retq
+  %r = load i1, i1* %p1
+  ret i1 %r
+}
+
 define i8 @test_load_i8(i8 * %p1) {
 ; ALL-LABEL: test_load_i8:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    movb (%rdi), %al
 ; ALL-NEXT:    retq
   %r = load i8, i8* %p1
   ret i8 %r
 }

 ; ALL:       # BB#0:
 ; ALL-NEXT:    movq (%rdi), %rax
 ; ALL-NEXT:    movq %rax, %xmm0
 ; ALL-NEXT:    retq
   %r = load double, double* %p1
   ret double %r
 }
 
+define i1 * @test_store_i1(i1 %val, i1 * %p1) {
+; ALL-LABEL: test_store_i1:
+; ALL:       # BB#0:
+; ALL-NEXT:    andb $1, %dil
+; ALL-NEXT:    movb %dil, (%rsi)
+; ALL-NEXT:    movq %rsi, %rax
+; ALL-NEXT:    retq
+  store i1 %val, i1* %p1
+  ret i1 * %p1;
+}
+
 define i32 * @test_store_i32(i32 %val, i32 * %p1) {
 ; ALL-LABEL: test_store_i32:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    movl %edi, (%rsi)
 ; ALL-NEXT:    movq %rsi, %rax
 ; ALL-NEXT:    retq
   store i32 %val, i32* %p1
   ret i32 * %p1;