[AArch64] Add AArch64Subtarget::isFusion function.

[fhahn]

Summary

isFusion returns true if the subtarget supports any kind of instruction
fusion, similar to ARMSubtarget::isFusion. This was suggested in D34142.

This changes the current behavior slightly, because the macro fusion mutation
is now added to the PostRA MachineScheduler in case the subtarget supports
any kind of fusion. I think that makes sense because if the PostRA
MachineScheduler is run, there is potential that instructions scheduled back to
back are re-scheduled.

[javed.absar]

lib/Target/AArch64/AArch64TargetMachine.cpp

290

This doesn't look like NFCI - as previously this would be triggered on hasFuseAES and hasFuseLiteral only, but now it will include Bcc and cbz fusion as well.

[fhahn]

Adding @joel_k_jones as a reviewer, as this change potentially changes code generated for thunderx2t99.

lib/Target/AArch64/AArch64TargetMachine.cpp

290

Indeed, that should have been clearer from the description. I'll update the description. I think it makes sense to add the macro fusion mutation in case any kind of fusion is supported, because if the PostRA machinescheduler is run, there's always potential that instructions scheduled back to back are re-scheduled.

Currently, this could potentially only change the code generated for thunderx2t99, which is the only subtarget that uses the PostRA machinescheduler AND has ArithmeticBccFusion (and not FuseAES or FuseLiterals).

[joelkevinjones]

Stefan has been doing the back-end as well.

[fhahn]

Great thank you! The change should only have minimal impact on code generated on a thunderx2t99, the worst thing that could happen is that arithmetic instructions that have been fused with BCC during instruction scheduling would now be scheduled back-to-back in the PostRA MachineScheduler too, whereas before they might not have been, because the constraints weren't added for the PostRA MachineScheduler.

[evandro]

lib/Target/AArch64/AArch64TargetMachine.cpp

290

I agree. It's probably just luck that instructions fused with the ExitSU, when the latter depends tightly on the former, have little chance of moving post the RA.

[fhahn]

Ping. @joelkevinjones @steleman are you happy for this to go in?

[steleman]

In D34958#806341, @fhahn wrote:

Ping. @joelkevinjones @steleman are you happy for this to go in?

I am running SPECint2K6 with and without your patch for comparison and
I will let you know as soon as I have all the numbers.

[steleman]

In D34958#806717, @steleman wrote:

In D34958#806341, @fhahn wrote:

Ping. @joelkevinjones @steleman are you happy for this to go in?

I am running SPECint2K6 with and without your patch for comparison and
I will let you know as soon as I have all the numbers.

Your patch shows an improvement for 462.libquantum:

1. Without your patch: 315.392 = 65.695
2. With your patch: 301.580 = 68.704

The other benchmarks either didn't show much of a difference, or the difference
was well within the noise range.

So, I have no objections to this patch.

[joelkevinjones]

Thanks Stefan. LGTM

[fhahn]

Thanks, great that it improves 462.libquantum slightly tx2

[evandro]

LGTM

lib/Target/AArch64/AArch64Subtarget.h

public:
   bool isPaired128Slow() const { return Paired128IsSlow; }
   bool useAlternateSExtLoadCVTF32Pattern() const {
     return UseAlternateSExtLoadCVTF32Pattern;
   }
   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
   bool hasFuseAES() const { return HasFuseAES; }
   bool hasFuseLiterals() const { return HasFuseLiterals; }
+
+  /// \brief Return true if the CPU supports any kind of instruction fusion.
+  bool hasFusion() const {
+    return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
+           hasFuseAES() || hasFuseLiterals();
+  }
+
   bool useRSqrt() const { return UseRSqrt; }
   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
   unsigned getVectorInsertExtractBaseCost() const {
     return VectorInsertExtractBaseCost;
   }
   unsigned getCacheLineSize() const { return CacheLineSize; }
   unsigned getPrefetchDistance() const { return PrefetchDistance; }
   unsigned getMinPrefetchStride() const { return MinPrefetchStride; }

lib/Target/AArch64/AArch64TargetMachine.cpp

createMachineScheduler(MachineSchedContext *C) const override {
     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
     DAG->addMutation(createAArch64MacroFusionDAGMutation());
     return DAG;
   }
 
   ScheduleDAGInstrs *
   createPostMachineScheduler(MachineSchedContext *C) const override {
     const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
-    if (ST.hasFuseAES() || ST.hasFuseLiterals()) {
+    if (ST.hasFusion()) {
       // Run the Macro Fusion after RA again since literals are expanded from
       // pseudos then (v. addPreSched2()).
       ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
       DAG->addMutation(createAArch64MacroFusionDAGMutation());
       return DAG;
     }
 
     return nullptr;