Index: lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -338,7 +338,7 @@
   unsigned Reg = MO.getReg();
   RegEnc |= MRI.getEncodingValue(Reg);
   RegEnc &= SDWA9_SRC_REG_MASK;
-  if (AMDGPU::isSGPR(Reg, &MRI)) {
+  if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
     RegEnc |= SDWA9_SRC_SGPR_MASK;
   }
   return RegEnc;
@@ -353,7 +353,7 @@
   const MCOperand &MO = MI.getOperand(OpNo);
 
   unsigned Reg = MO.getReg();
-  if (Reg != AMDGPU::VCC) {
+  if (AMDGPU::mc2PseudoReg(Reg) != AMDGPU::VCC) {
     RegEnc |= MRI.getEncodingValue(Reg);
     RegEnc &= SDWA9_VOPC_DST_REG_MASK;
     RegEnc |= SDWA9_VOPC_DST_VCC_MASK;
Index: test/MC/AMDGPU/vop_sdwa.s
===================================================================
--- test/MC/AMDGPU/vop_sdwa.s
+++ test/MC/AMDGPU/vop_sdwa.s
@@ -658,6 +658,11 @@
 
 // NOSICI: error:
 // NOVI: error:
+// GFX9: v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x06]
+v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+
+// NOSICI: error:
+// NOVI: error:
 // GFX9: v_add_f32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x85,0x02]
 v_add_f32 v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2