[InstCombine] prefer xor with -1 because 'not' is easier to understand

[spatel]

Summary

This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706

[efriedma]

LGTM.

llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

case Instruction::Xor: {
     if (DemandedMask.isSubsetOf(RHSKnownZero|RHSKnownOne) &&
         RHSKnownOne.isSubsetOf(LHSKnownOne)) {
       Constant *AndC = Constant::getIntegerValue(VTy,
                                                  ~RHSKnownOne & DemandedMask);
       Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
       return InsertNewInstWith(And, *I);
     }
 
-    // If the RHS is a constant, see if we can simplify it.
-    // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
+    // If the RHS is a constant, see if we can change it. Don't alter a -1
+    // constant because that's a canonical 'not' op, and that is better for
+    // combining, SCEV, and codegen.
+    const APInt *C;
+    if (match(I->getOperand(1), m_APInt(C)) && !C->isAllOnesValue()) {
+      if ((*C | ~DemandedMask).isAllOnesValue()) {
+        // Force bits to 1 to create a 'not' op.
+        I->setOperand(1, ConstantInt::getAllOnesValue(VTy));
+        return I;
+      }
+      // If we can't turn this into a 'not', try to shrink the constant.
       if (ShrinkDemandedConstant(I, 1, DemandedMask))
         return I;
+    }
 
     // If our LHS is an 'and' and if it has one use, and if any of the bits we
     // are flipping are known to be set, then the xor is just resetting those
     // bits to zero.  We can just knock out bits from the 'and' and the 'xor',
     // simplifying both of them.
     if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
       if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
           isa<ConstantInt>(I->getOperand(1)) &&

llvm/trunk/test/Transforms/InstCombine/xor.ll

 ; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A:%.*]], -1
 ; CHECK-NEXT:    [[XOR:%.*]] = and i32 [[TMP1]], [[B:%.*]]
 ; CHECK-NEXT:    ret i32 [[XOR]]
 ;
   %and = and i32 %B, %A
   %xor = xor i32 %and, %B
   ret i32 %xor
 }
+
+; PR32706 - https://bugs.llvm.org/show_bug.cgi?id=32706
+; Pin an xor constant operand to -1 if possible because 'not' is better for SCEV and codegen.
+
+define i32 @not_is_canonical(i32 %x, i32 %y) {
+; CHECK-LABEL: @not_is_canonical(
+; CHECK-NEXT:    [[SUB:%.*]] = xor i32 %x, -1
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], %y
+; CHECK-NEXT:    [[MUL:%.*]] = shl i32 [[ADD]], 2
+; CHECK-NEXT:    ret i32 [[MUL]]
+;
+  %sub = xor i32 %x, 1073741823
+  %add = add i32 %sub, %y
+  %mul = shl i32 %add, 2
+  ret i32 %mul
+}
+

llvm/trunk/test/Transforms/InstCombine/zext.ll

;
   %trunc = trunc <2 x i64> %A to <2 x i32>
   %and = and <2 x i32> %trunc, <i32 23, i32 42>
   %zext = zext <2 x i32> %and to <2 x i64>
   ret <2 x i64> %zext
 }
 
 define <2 x i64> @test4(<2 x i64> %A) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i64> %A, <i64 63, i64 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i64> %A, <i64 -1, i64 -1>
 ; CHECK-NEXT:    [[XOR:%.*]] = and <2 x i64> [[TMP1]], <i64 23, i64 42>
 ; CHECK-NEXT:    ret <2 x i64> [[XOR]]
 ;
   %trunc = trunc <2 x i64> %A to <2 x i32>
   %and = and <2 x i32> %trunc, <i32 23, i32 42>
   %xor = xor <2 x i32> %and, <i32 23, i32 42>
   %zext = zext <2 x i32> %xor to <2 x i64>
   ret <2 x i64> %zext