Index: lib/Target/X86/AsmParser/X86AsmParser.cpp
===================================================================
--- lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -679,6 +679,29 @@
         break;
       }
     }
+    // Some binary bitwise operators have a named synonymous
+    // Query a candidate string for being such a named operator
+    // and if so - invoke the appropriate handler
+    bool onNamedOperator(StringRef Name) {
+      // A named operator should be either lower or upper case, but not a mix
+      if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
+        return false;
+      if (Name.equals_lower("not"))
+        onNot();
+      else if (Name.equals_lower("or"))
+        onOr();
+      else if (Name.equals_lower("shl"))
+        onLShift();
+      else if (Name.equals_lower("shr"))
+        onRShift();
+      else if (Name.equals_lower("xor"))
+        onXor();
+      else if (Name.equals_lower("and"))
+        onAnd();
+      else
+        return false;
+      return true;
+    }
   };
 
   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
@@ -1339,6 +1362,8 @@
       UpdateLocLex = false;
       if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) {
         SM.onRegister(TmpReg);
+      } else if (SM.onNamedOperator(Identifier)) {
+        UpdateLocLex = true;
       } else if (!isParsingInlineAsm()) {
         if (getParser().parsePrimaryExpr(Val, End))
           return Error(Tok.getLoc(), "Unexpected identifier!");
Index: test/MC/X86/intel-syntax-bitwise-ops.s
===================================================================
--- test/MC/X86/intel-syntax-bitwise-ops.s
+++ test/MC/X86/intel-syntax-bitwise-ops.s
@@ -6,19 +6,37 @@
     and ecx, 1+2
 // CHECK: andl	$3, %ecx
     and ecx, 1|2
-// CHECK: andl	$3, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, 1 or 2
+// CHECK: andl $3, %ecx
     and ecx, 1*3
 // CHECK: andl	$1, %ecx
     and ecx, 1&3
-// CHECK: andl	$0, %ecx
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 3
+// CHECK: andl $0, %ecx
     and ecx, (1&2)
-// CHECK: andl	$3, %ecx
+// CHECK: andl $0, %ecx
+    and ecx, (1 and 2)
+// CHECK: andl $3, %ecx
     and ecx, ((1)|2)
-// CHECK: andl	$1, %ecx
+// CHECK: andl $3, %ecx
+    and ecx, ((1) or 2)
+// CHECK: andl $1, %ecx
     and ecx, 1&2+3
-// CHECK: addl	$4938, %eax
+// CHECK: andl $1, %ecx
+    and ecx, 1 and 2+3
+// CHECK: addl $4938, %eax
     add eax, 9876 >> 1
-// CHECK: addl	$19752, %eax
+// CHECK: addl $4938, %eax
+    add eax, 9876 shr 1
+// CHECK: addl $19752, %eax
     add eax, 9876 << 1
-// CHECK: addl	$5, %eax
+// CHECK: addl $19752, %eax
+    add eax, 9876 shl 1
+// CHECK: addl $5, %eax
     add eax, 6 ^ 3
+// CHECK: addl $5, %eax
+    add eax, 6 xor 3
+// CHECK: addl $-9, %eax
+    add eax, not 8