Index: lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.cpp
+++ lib/Target/X86/X86TargetTransformInfo.cpp
@@ -141,13 +141,19 @@
   if (Vector && !ST->hasSSE1())
     return 0;
 
-  if (ST->is64Bit())
-    return 16;
+  if (ST->is64Bit()) {
+    // KNL in 64-bit mode has 32 %zmm registers.
+    if (ST->hasAVX512())
+      return 32;
+    else
+      return 16;
+  }
   return 8;
 }
 
 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
   if (Vector) {
+    if (ST->hasAVX512()) return 512;
     if (ST->hasAVX()) return 256;
     if (ST->hasSSE1()) return 128;
     return 0;
Index: test/Transforms/LoopVectorize/X86/avx512-vector-width.ll
===================================================================
--- /dev/null
+++ test/Transforms/LoopVectorize/X86/avx512-vector-width.ll
@@ -0,0 +1,27 @@
+; RUN: opt -mattr=+avx512f -loop-vectorize -S < %s | FileCheck %s
+; CHECK: <16 x float>
+; CHECK-NOT: <8 x float>
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @foo(float* noalias %a, float* noalias %b, float* noalias %c, i32 %n) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv
+  %0 = load float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float* %b, i64 %indvars.iv
+  %1 = load float* %arrayidx2, align 4
+  %mul = fmul fast float %0, %1
+  %arrayidx4 = getelementptr inbounds float* %c, i64 %indvars.iv
+  store float %mul, float* %arrayidx4, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, 1024
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret void
+}