[MIPS] Fix uitofp and fptoui for vector and scalar types

[sdardis]

Summary

This patch fixes the lowering of uitofp and fptoui. For out of range values to fptoui and uitofp we perform fixups so that the result value is correct.

This patch is based on work by Simon Dardis.

[sdardis]

Comments inlined. I'm concerned that the legalization action of fp_to_uint is incorrect given the differences between the output of LLVM and GCC, in addition to the difference in the lowering of the i32 and i64 types.

Additionally, some of the new emit*() functions are producing bad machine code due to differences in register classes/instructions for MIPS32 / MIPS64. You can find the problems by running the test cases with -verify-machineinstrs.

With -verify-machineinstrs, two of the bad machine code errors refer to mtc1 / mfc1. You can ignore them for the purposes of this patch, this is an outstanding bug with LLVM for MIPS, as those instructions need definitions for the AFGR64 and FGR64 register classes.

lib/Target/Mips/MipsISelLowering.cpp

343

This looks incorrect. The associated lowering calls lowerFP_TO_SINT for the conversion of a floating point value to an unsigned integer. It also wildly differs from the output of gcc.

2724–2735

clang-format this chunk. There's spurious whitespace and overly long lines.

lib/Target/Mips/MipsInstrFPU.td

252

The '[' should be aligned with the (outs), not with the template parameters.

833

Overly long line, place the FGR_64 under the MipsPat.

lib/Target/Mips/MipsMSAInstrInfo.td

3775

This is formatted incorrectly. It should be formatted like the pseudo description above.

lib/Target/Mips/MipsSEISelLowering.cpp

3716

Can you provide the expansion as a comment similar to the likes of emitFPEXTEND_PSEUDO ?

3727

This variable is unused.

3739

Can you provide the expansion as a comment similar to the likes of emitFPEXTEND_PSEUDO ?

3743

FAddOp.

3764

Add BranchProbability::getOne() to the call, we know that this is a guaranteed fall-through.

3778–3781

Rather than numbers, try to name variables so that their purpose is obvious.

E.g. FPVReg3 should be FPAddReg.

3793

If src is a GPR64, this needs to be BGEZ64.

3797

This needs to be LUi64 on if GPVReg1 is a GPR64.

3806

That should be Mips::ZERO. BuildPairF64_64 is for FGR64 on Mips32.

test/CodeGen/Mips/2008-07-07-Float2Int.ll

12–13

Change that line while you're here to CHECK-LABEL: fptouint:

test/CodeGen/Mips/msa/f16-llvm-ir.ll

162–165

FIXME: This shift may be spurious given the definition of fill.w in the MSA spec.

[slthakur]

Addressed review comments

[sdardis]

Comments inlined. I'm concerned about two things in this patch, the handling of FP_TO_UINT which lowers as if it was FP_TO_SINT and the sequences which perform correction for negative values.

lib/Target/Mips/MipsISelLowering.cpp

1242

This is incorrect. Instead we need to provide a custom expander that mimics the expansion of fp_to_sint for i32, i.e. expand it to subtraction and comparison returning the appropriate converted result.

2719

This should be "SDValue Ops[2] = {Lo, Hi};".

lib/Target/Mips/MipsMSAInstrInfo.td

3776

Spurious whitespace at the end of the line here.

lib/Target/Mips/MipsSEISelLowering.cpp

3750–3753

I have some concerns about this sequence.

Firstly, the addition of negative zero does not negate the result which I believe you're trying to achieve here. You either need to subtract negative zero from the result of the conversion to negate the result or as we can only reach here if the input is less than zero, use fneg.s directly.

Secondly, although the conversion of an unsigned integer whose value is greater than the range of values that a floating point type can represent is undefined behaviour, is this behaviour compatible with GCC's result or do we need that level of compatibility?

3758–3760

This sequence treats the input as a signed value.

3764

That's acceptable for mips64r2 or later. We also need to provide a version for mips3 to mips64 which would use shifts to truncate the value.

3765–3766

This treats in the input as an unsigned value as well.

3772–3777

See my comment about using fneg directly.

3782–3790

These treat their inputs as signed values.

3804

Missing the branch label here. Also the branch labels for N32/N64 are .L, not $.

3816

These two variables have uninitialized uses...

3854–3857

dext is a mips64r2 instruction, but we also need to support the likes of mips3, mips4 and mips64. You need to provide codepaths for those systems.

3888–3924

...here if (IsSrc64 || !IsFP64) is false.

[slthakur]

Addressed review comments. Sorry for the delay.

lib/Target/Mips/MipsSEISelLowering.cpp

3750–3753

Firstly, the addition of negative zero does not negate the result which I believe you're trying to achieve here. You either need > to subtract negative zero from the result of the conversion to negate the result or as we can only reach here if the input is > less than zero, use fneg.s directly.

The convert operation is wrong here. We need to convert into a double precision and add a double precision correction value. I have fixed it now. Sorry for to confusion.

Secondly, although the conversion of an unsigned integer whose value is greater than the range of values that a floating point > type can represent is undefined behaviour, is this behaviour compatible with GCC's result or do we need that level of > compatibility?

Yes, this behavior is compatible with GCC's result.

3758–3760

The input value is supposed to be zero extended. The zero value needed to be in the higher part.

3764

Added a codepath for mips3 to mips64 below.

3765–3766

The input value is 32-bit which is represented in 64-bit format (zero extended). Since the range of 64-bit format covers all the negative 32-bit values in its positive side it ensures safe conversion to floating point single. Therefore we don't need to worry about negative values here.

3782–3790

The input value is 32-bit which is represented in 64-bit format (zero extended). Since the range of long format covers all the 32-bit values in its positive side it ensures safe conversion to floating point double. Therefore we don't need to worry about negative values here.

3888–3924

Restructured the code. The cases of FGR64onMips32 and FGR64onMips64 with 32-bit source input will he handled above. Rest all cases will be handled here.

test/CodeGen/Mips/msa/f16-llvm-ir.ll

162–165

From the dump, looks like sll is being selected from the truncate node:

SelectionDAG has 12 nodes:
  t0: ch = EntryToken
          t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0
        t3: i32 = truncate t2
      t4: f16 = uint_to_fp t3
        t12: i64 = MipsISD::Wrapper Register:i64 %vreg1, TargetGlobalAddress:i64<half* @h> 0 [TF=15]
      t13: i64,ch = load<LD8[GOT]> t0, t12, undef:i64
    t8: ch = store<ST2[@h]> t0, t4, t13, undef:i64
  t9: ch = MipsISD::Ret t8

ISEL: Starting pattern match on root node: t3: i32 = truncate t2

  Initial Opcode index to 29877
  Match failed at index 29880
  Continuing at 29924
  Created node: t16: i32 = EXTRACT_SUBREG t2, TargetConstant:i32<1>

  Morphed node: t3: i32 = SLL t16, TargetConstant:i32<0>

[sdardis]

Comments inlined. Most of them are small nits. The big change required is that you need to provide a target DAGCombine to produce the pseudos for later expansion on mips32r2 with a 64 bit fpu.

lib/Target/Mips/MipsSEISelLowering.cpp

1052–1055

Nit: can you rename UINT_TO_FP_MSA to MSA_UINT_TO_FP ? and likewise for FP_TO_UINT?

It preserves the style of how the emit functions are named.

3745–3747

This comment is incorrect, it reflects MSA_UINT_TO_FP. It should reflect MSA_FP_TO_UINT.

3849–3850

hasMips64() -> hasMips3(). Mips3 was the first MIPS ISA to support double precision FPUs.

3867

Lower than createVirtualRegister call to the point of usage, so we aren't creating virtual registers unnecessarily.

3868–3874

These sequences are not quite correct. For Mips64r2, you should use DEXT directly rather DEXT64_32 as DEXT64_32 is marked as isCodegenOnly. This means that instruction doesn't participate the ISA mapping tables. We use these tables to convert standard MIPS to microMIPS64R6, so currently this code will produce broken objects.

You need to define a GPR64 register using IMPLICIT_DEF, then use that register along with INSERT_SUBREG and Src and the subregister index. You can then use DEXT directly.

That sequence I've outlined is also required for the DSLL / DSRL sequence. This more or less handles it:

unsigned GPImpDef = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);                                          
unsigned GPRRes = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);                                            
BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), GPImpDef);                                                     
BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), GPRRes)                                                       
    .addReg(GPImpDef)                                                                                             
    .addReg(Src)                                                                                                  
    .addImm(Mips::sub_32);

You'll want to change the variable names around.

3919

Lower this to the point of usage to avoid creating unused virtual registers.

3923

hasMips64() -> hasMips3()

3964

Using FPAddResult here as the destination means that the addition and phi node instructions can be hoisted above the if block, simplifying the code here.

4004–4024

This sequence isn't being generated by LLVM. Instead, we always get the libcall expansion. Also :: emitFP_TO_UINT(...) doesn't seem able to produce the sequence with xor in it.

This occurs because the legalizer replaces the fp_to_uint node because the result type is not legal, before we can select the pseudo the generates this sequence.

What we want to do is to use setTargetDAGCombine(ISD::FP_TO_UINT) and provide a combine that replaces fp_to_uint with the correct pseudo when we're targeting mips32r2 -mfp64 and not mips3. That transformation will have to be guarded by DCI.isBeforeLegalizeOps(). See my commit fixing the multi-precision arithmetic and the optimization for madd / msub.

4037–4039

This sequence looks incorrect. It should be lui $2, 0x8000, as you're oring the value which has been truncated to 32 bits. Also, if this is FP_TO_UINT FGR64Opnd:$fs, GPR32Opnd:$rd, then the floating point operations should be on double precision values, not single precision values.

4067–4068

Double check this for endian dependant behaviour.

4082–4084

Either lui $2, 1 ; dsll $2, $2, 31 or li $2, 1; dsll32 $2, $2, 31.

4101–4102

hasMips64() -> hasMips3().

4171

This if condition looks spurious.

4173

DSLL32 with an immediate of 0.

4215–4242

Can you restructure this code so that it reads like:

if (IsDest64) {
  if (ISFGR64onMips32)
    ..
} else {
  ..
}

Rather than:

if (IsDest64) {
  ...
} else {
  ...
}

if (IsDest64) {
  ...
} else {
  ...
}

4220

This if condition looks spurious. If the destination is 64 bits in size, then we decide between mips32 or mips64.

4230–4238

FIXME: The delay slot filler fails to schedule LUi(64) into the delay slot of the BC1T.

test/CodeGen/Mips/llvm-ir/fpcvt.ll

6 ↗

(On Diff #102308)

This needs mips3, mips64 as well.

test/CodeGen/Mips/msa/f16-llvm-ir.ll

162–165

I believe my original thought was this was a redundant sign extension, as my reading of the MSA spec leads me to believe that fill.w behaves differently to MIPS32 instructions in that it doesn't need to be guarded by a sign extension.

I believe that fill.[bhw] and copy_s.[bhw] when used around argument passing in/out and for returns, there is scope to eliminate some sign extensions. That's future work though as the optimization would be tedious to implement at the SelectionDAG layer.

[slthakur]

Addressed review comments and re-synced with TOT.

[sdardis]

Taking over this work, as slthakur is no longer with IMG.

lib/Target/Mips/MipsISelLowering.cpp

if (Subtarget.isGP64bit()) {
     setOperationAction(ISD::BlockAddress,       MVT::i64,   Custom);
     setOperationAction(ISD::GlobalTLSAddress,   MVT::i64,   Custom);
     setOperationAction(ISD::JumpTable,          MVT::i64,   Custom);
     setOperationAction(ISD::ConstantPool,       MVT::i64,   Custom);
     setOperationAction(ISD::SELECT,             MVT::i64,   Custom);
     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
     setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
     setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
     setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
+    setOperationAction(ISD::UINT_TO_FP,         MVT::i64,   Legal);
   }
 
   if (!Subtarget.isGP64bit()) {
     setOperationAction(ISD::SHL_PARTS,          MVT::i32,   Custom);
     setOperationAction(ISD::SRA_PARTS,          MVT::i32,   Custom);
     setOperationAction(ISD::SRL_PARTS,          MVT::i32,   Custom);
   }
 
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setOperationAction(ISD::BR_CC,             MVT::f32,   Expand);
   setOperationAction(ISD::BR_CC,             MVT::f64,   Expand);
   setOperationAction(ISD::BR_CC,             MVT::i32,   Expand);
   setOperationAction(ISD::BR_CC,             MVT::i64,   Expand);
   setOperationAction(ISD::SELECT_CC,         MVT::i32,   Expand);
   setOperationAction(ISD::SELECT_CC,         MVT::i64,   Expand);
   setOperationAction(ISD::SELECT_CC,         MVT::f32,   Expand);
   setOperationAction(ISD::SELECT_CC,         MVT::f64,   Expand);
-  setOperationAction(ISD::UINT_TO_FP,        MVT::i32,   Expand);
-  setOperationAction(ISD::UINT_TO_FP,        MVT::i64,   Expand);
-  setOperationAction(ISD::FP_TO_UINT,        MVT::i32,   Expand);
-  setOperationAction(ISD::FP_TO_UINT,        MVT::i64,   Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,    Expand);
   if (Subtarget.hasCnMips()) {
     setOperationAction(ISD::CTPOP,           MVT::i32,   Legal);
     setOperationAction(ISD::CTPOP,           MVT::i64,   Legal);
   } else {
     setOperationAction(ISD::CTPOP,           MVT::i32,   Expand);
     setOperationAction(ISD::CTPOP,           MVT::i64,   Expand);
   }
LowerOperation(SDValue Op, SelectionDAG &DAG) const
   case ISD::EH_RETURN:          return lowerEH_RETURN(Op, DAG);
   case ISD::ATOMIC_FENCE:       return lowerATOMIC_FENCE(Op, DAG);
   case ISD::SHL_PARTS:          return lowerShiftLeftParts(Op, DAG);
   case ISD::SRA_PARTS:          return lowerShiftRightParts(Op, DAG, true);
   case ISD::SRL_PARTS:          return lowerShiftRightParts(Op, DAG, false);
   case ISD::LOAD:               return lowerLOAD(Op, DAG);
   case ISD::STORE:              return lowerSTORE(Op, DAG);
   case ISD::EH_DWARF_CFA:       return lowerEH_DWARF_CFA(Op, DAG);
   case ISD::FP_TO_SINT:         return lowerFP_TO_SINT(Op, DAG);
   }
   return SDValue();
 }
 
 //===----------------------------------------------------------------------===//
 //  Lower helper functions
 //===----------------------------------------------------------------------===//
 

 
 //===----------------------------------------------------------------------===//
 //                      Calling Convention Implementation
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // TODO: Implement a generic logic using tblgen that can support this.
 // Mips O32 ABI rules:
 // ---
 // i32 - Passed in A0, A1, A2, A3 and stack
 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
 //       an argument. Otherwise, passed in A1, A2, A3 and stack.
 // f64 - Only passed in two aliased f32 registers if no int reg has been used
 //       yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
 //       not used, it must be shadowed. If only A3 is available, shadow it and
 //       go to stack.
 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
 //         with the remainder spilled to the stack.
 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
 //         spilling the remainder to the stack.
 //
 //  For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
 //===----------------------------------------------------------------------===//
 
 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
                        CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                        CCState &State, ArrayRef<MCPhysReg> F64Regs) {
   const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
       State.getMachineFunction().getSubtarget());
 
   static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
 

lib/Target/Mips/MipsInstrFPU.td

class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
                 InstrItinClass itin>  :
    InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
           !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
           FrmFR>, HARDFLOAT {
   let isCompare = 1;
   let hasFCCRegOperand = 1;
 }
 
+class UIntToFp_FT<RegisterOperand OutRC, RegisterOperand InRC> :
+  PseudoSE<(outs OutRC:$dst), (ins InRC:$src),
+           [(set OutRC:$dst, (uint_to_fp InRC:$src))]> {
+  let usesCustomInserter = 1;
+}
+
+class FpToUInt_FT<RegisterOperand OutRC, RegisterOperand InRC> :
+  PseudoSE<(outs OutRC:$dst), (ins InRC:$src),
+           [(set OutRC:$dst, (fp_to_uint InRC:$src))]> {
+  let usesCustomInserter = 1;
+}
 
 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
                     InstrItinClass itin> {
   def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
                   C_COND_FM<fmt, 0> {
     let BaseOpcode = "c.f."#NAME;
     let isCommutable = 1;
   }

 let isPseudo = 1, isCodeGenOnly = 1 in {
   def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
   def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
   def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
 }
 
+def UInt32ToFp32Pseudo_32 : UIntToFp_FT<FGR32Opnd, GPR32Opnd>, FGR_32;
+def UInt32ToFp32Pseudo_64 : UIntToFp_FT<FGR32Opnd, GPR32Opnd>, FGR_64;
+def UInt32ToFp64Pseudo_32 : UIntToFp_FT<AFGR64Opnd, GPR32Opnd>, FGR_32;
+def UInt32ToFp64Pseudo_64 : UIntToFp_FT<FGR64Opnd, GPR32Opnd>, FGR_64;
+def UInt64ToFp64Pseudo_64 : UIntToFp_FT<FGR64Opnd, GPR64Opnd>, FGR_64;
+
+def Fp32ToUInt32Pseudo_32 : FpToUInt_FT<GPR32Opnd, FGR32Opnd>, FGR_32;
+def Fp32ToUInt32Pseudo_64 : FpToUInt_FT<GPR32Opnd, FGR32Opnd>, FGR_64;
+def Fp32ToUInt64Pseudo_64 : FpToUInt_FT<GPR64Opnd, FGR32Opnd>, FGR_64;
+def Fp64ToUInt32Pseudo_32 : FpToUInt_FT<GPR32Opnd, AFGR64Opnd>, FGR_32;
+def Fp64ToUInt32Pseudo_64 : FpToUInt_FT<GPR32Opnd, FGR64Opnd>, FGR_64;
+def Fp64ToUInt64Pseudo_64 : FpToUInt_FT<GPR64Opnd, FGR64Opnd>, FGR_64;
+
 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
              ABSS_FM<0x5, 16>;
 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
              ABSS_FM<0x7, 16>;
 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
 
 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6,
          HARDFLOAT;
 }
 //===----------------------------------------------------------------------===//
 // Floating Point Patterns
 //===----------------------------------------------------------------------===//
 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
 
 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
               (PseudoCVT_S_W GPR32Opnd:$src)>;
 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
               (TRUNC_W_S FGR32Opnd:$src)>;
 
 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
               (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
               (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;

lib/Target/Mips/MipsMSAInstrInfo.td

 
  def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd),
                                         (ins FGR64Opnd:$fs),
                               [(set MSA128F16:$wd,
                                     (f16 (fpround FGR64Opnd:$fs)))]> {
   let usesCustomInserter = 1;
  }
 
+ def MSA_UINT_TO_FP : MipsPseudo<(outs MSA128F16:$wd), (ins GPR32Opnd:$rs),
+                                 [(set MSA128F16:$wd,
+                                       (f16 (uint_to_fp GPR32Opnd:$rs)))]> {
+   let usesCustomInserter = 1;
+ }
+
+ def MSA_FP_TO_UINT : MipsPseudo<(outs GPR32Opnd:$rd), (ins MSA128F16:$ws),
+                                 [(set GPR32Opnd:$rd,
+                                       (i32 (fp_to_uint MSA128F16:$ws)))]> {
+   let usesCustomInserter = 1;
+ }
+
  def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
                (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>;
 
  def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
                (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
                          (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
        ISA_MIPS1_NOT_32R6_64R6;
 }

lib/Target/Mips/MipsSEISelLowering.h

private:
     /// \brief Emit the FEXP2_W_1 pseudo instructions.
     MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
                                            MachineBasicBlock *BB,
                                            bool IsFGR64) const;
     /// \brief Emit the FEXP2_D_1 pseudo instructions.
     MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
                                           MachineBasicBlock *BBi,
                                           bool IsFGR64) const;
+
+    MachineBasicBlock *emitMSA_UINT_TO_FP(MachineInstr &MI,
+                                          MachineBasicBlock *BB) const;
+
+    MachineBasicBlock *emitMSA_FP_TO_UINT(MachineInstr &MI,
+                                          MachineBasicBlock *BB) const;
+
+    MachineBasicBlock *emitUINT_TO_FP(MachineInstr &MI, MachineBasicBlock *BB,
+                                      unsigned CvtOp, unsigned FaddOp,
+                                      bool isFP64) const;
+
+    MachineBasicBlock *emitFP_TO_UINT(MachineInstr &MI, MachineBasicBlock *BB,
+                                      unsigned TruncOp, unsigned FSubOp,
+                                      bool isFP64) const;
   };
 }
 
 #endif

lib/Target/Mips/MipsSEISelLowering.cpp

MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case Mips::MSA_FP_EXTEND_W_PSEUDO:
     return emitFPEXTEND_PSEUDO(MI, BB, false);
   case Mips::MSA_FP_ROUND_W_PSEUDO:
     return emitFPROUND_PSEUDO(MI, BB, false);
   case Mips::MSA_FP_EXTEND_D_PSEUDO:
     return emitFPEXTEND_PSEUDO(MI, BB, true);
   case Mips::MSA_FP_ROUND_D_PSEUDO:
     return emitFPROUND_PSEUDO(MI, BB, true);
+  case Mips::MSA_UINT_TO_FP:
+    return emitMSA_UINT_TO_FP(MI, BB);
+  case Mips::MSA_FP_TO_UINT:
+    return emitMSA_FP_TO_UINT(MI, BB);
+  case Mips::UInt32ToFp32Pseudo_32:
+    return emitUINT_TO_FP(MI, BB, Mips::CVT_D32_W, Mips::FADD_D32, false);
+  case Mips::UInt32ToFp32Pseudo_64:
+    return emitUINT_TO_FP(MI, BB, Mips::CVT_S_L, 0, true);
+  case Mips::UInt32ToFp64Pseudo_32:
+    return emitUINT_TO_FP(MI, BB, Mips::CVT_D32_W, Mips::FADD_D32, false);
+  case Mips::UInt32ToFp64Pseudo_64:
+    return emitUINT_TO_FP(MI, BB, Mips::CVT_D64_L, Mips::FADD_D64, true);
+  case Mips::UInt64ToFp64Pseudo_64:
+    return emitUINT_TO_FP(MI, BB, Mips::CVT_D64_L, Mips::FADD_D64, true);
+  case Mips::Fp32ToUInt32Pseudo_32:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_W_S, Mips::FSUB_S, false);
+  case Mips::Fp32ToUInt32Pseudo_64:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_W_S, Mips::FSUB_S, true);
+  case Mips::Fp32ToUInt64Pseudo_64:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_L_S, Mips::FSUB_S, true);
+  case Mips::Fp64ToUInt32Pseudo_32:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_W_D32, Mips::FSUB_D32, false);
+  case Mips::Fp64ToUInt32Pseudo_64:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_W_D64, Mips::FSUB_D64, true);
+  case Mips::Fp64ToUInt64Pseudo_64:
+    return emitFP_TO_UINT(MI, BB, Mips::TRUNC_L_D64, Mips::FSUB_D64, true);
   }
 }
 
 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
     const CCState &CCInfo, unsigned NextStackOffset,
     const MipsFunctionInfo &FI) const {
   if (!UseMipsTailCalls)
     return false;
BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
         .addReg(FPRPHI)
         .addReg(Rtemp2);
   }
 
   MI.eraseFromParent();
   return BB;
 }
 
+// Emit the MSA_UINT_TO_FP pseudo instruction.
+//
+//  fill.w    $wtemp, $rs
+//  ffint_u.w $wtemp2, $wtemp
+//  fexdo.h   $wtemp3, $wtemp2, $wtemp2
+//
+MachineBasicBlock *
+MipsSETargetLowering::emitMSA_UINT_TO_FP(MachineInstr &MI,
+                                         MachineBasicBlock *BB) const {
+
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
+  DebugLoc DL = MI.getDebugLoc();
+  unsigned Wd1 = RegInfo.createVirtualRegister(RC);
+  unsigned Wd2 = RegInfo.createVirtualRegister(RC);
+  BuildMI(*BB, MI, DL, TII->get(Mips::FILL_W), Wd1)
+      .addReg(MI.getOperand(1).getReg());
+  BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Wd2).addReg(Wd1);
+  BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), MI.getOperand(0).getReg())
+      .addReg(Wd2)
+      .addReg(Wd2);
+
+  MI.eraseFromParent();
+  return BB;
+}
+
+// Emit the MSA_FP_TO_UINT pseudo instruction.
+//
+//  fexupr.w  $wtemp, $rs
+//  ftint_u.w $wtemp2, $wtemp
+//  copy_u.w  $rd, $wtemp2[0]
+//
+MachineBasicBlock *
+MipsSETargetLowering::emitMSA_FP_TO_UINT(MachineInstr &MI,
+                                         MachineBasicBlock *BB) const {
+
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+  const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
+  DebugLoc DL = MI.getDebugLoc();
+  unsigned Wd1 = RegInfo.createVirtualRegister(RC);
+  unsigned Wd2 = RegInfo.createVirtualRegister(RC);
+  BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wd1)
+      .addReg(MI.getOperand(1).getReg());
+  BuildMI(*BB, MI, DL, TII->get(Mips::FTINT_U_W), Wd2).addReg(Wd1);
+  BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_W), MI.getOperand(0).getReg())
+      .addReg(Wd2)
+      .addImm(0);
+
+  MI.eraseFromParent();
+  return BB;
+}
+
+// Emit the UIntToFpPseudo pseudo instruction.
+//
+// UINT_TO_FP GPR32Opnd:$rs, FGR32Opnd:$fd
+// For Mips32r2:
+// =>
+//     mtc1    $rs, $ft
+//     cvt.d.w $ft1, $ft
+//     bgez    $rs, $BB0_2
+//     nop
+//     lui     $rt, 16880
+//     mtc1    $zero, $ft2
+//     mthc1   $1, $ft2
+//     add.d   $ft1, $ft1, $ft2
+// $BB0_2:
+//     cvt.s.d $fd, $ft1
+//
+// For Mips32r2 with 64-bit FPU:
+// =>
+//     mtc1    $rs, $ft
+//     mthc1   $zero, $ft
+//     cvt.s.l $fd, $ft
+//
+// For Mips64r2:
+// =>
+//     dext    $rt, $rs, 0, 32
+//     dmtc1   $rt, $ft
+//     cvt.s.l $fd, $ft
+//
+// UINT_TO_FP GPR32Opnd:$rs, FGR64Opnd:$fd
+// For Mips32r2:
+// =>
+//     mtc1    $rs, $ft
+//     cvt.d.w $ft, $ft
+//     bgez    $rs, $BB0_2
+//     nop
+//     lui     $rt, 16880
+//     mtc1    $zero, $ft1
+//     mthc1   $rt, $ft1
+//     add.d   $fd, $ft, $ft1
+// $BB0_2:
+//
+// For Mips32r2 with 64-bit FPU:
+// =>
+//     mtc1    $rs, $ft
+//     mthc1   $zero, $ft
+//     cvt.d.l $fd, $ft
+//
+// For Mips64r2:
+// =>
+//     dext    $rt, $rs, 0, 32
+//     dmtc1   $rt, $ft
+//     cvt.d.l $fd, $ft
+//
+// UINT_TO_FP GPR64Opnd:$rs, FGR64Opnd:$fd
+// For mips32: Lowered to libcall
+// For Mips32 with 64-bit FPU: Lowered by custom hook
+// For Mips64:
+// =>
+//     dmtc1   $rs, $ft
+//     cvt.d.l $ft1, $ft
+//     bgez    $rs, .LBB0_2
+//     nop
+//     lui     $rt, 17392
+//     dsll    $rt, $rt, 32
+//     dmtc1   $rt, $ft2
+//     add.d   $fd, $ft1, $ft2
+// .LBB0_2
+//
+MachineBasicBlock *MipsSETargetLowering::emitUINT_TO_FP(MachineInstr &MI,
+                                                        MachineBasicBlock *BB,
+                                                        unsigned CvtOp,
+                                                        unsigned FAddOp,
+                                                        bool IsFP64) const {
+
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+  DebugLoc DL = MI.getDebugLoc();
+  const BasicBlock *LLVM_BB = BB->getBasicBlock();
+
+  const bool IsFGR64onMips64 = Subtarget.hasMips3() && IsFP64;
+  const bool IsFGR64onMips32 = !Subtarget.hasMips3() && IsFP64;
+
+  unsigned Dest = MI.getOperand(0).getReg();
+  unsigned Src = MI.getOperand(1).getReg();
+
+  const TargetRegisterClass *FPDestClass = RegInfo.getRegClass(Dest);
+  const TargetRegisterClass *GPSrcClass = RegInfo.getRegClass(Src);
+
+  const bool IsSrc64 = GPSrcClass == &Mips::GPR64RegClass;
+  const bool IsDest64 = FPDestClass != &Mips::FGR32RegClass;
+
+  const TargetRegisterClass *FPTempRegClass =
+      !IsFP64 ? &Mips::AFGR64RegClass : &Mips::FGR64RegClass;
+  if (IsFGR64onMips64 && !IsSrc64) {
+    unsigned GPTemp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+    unsigned FPSrc = RegInfo.createVirtualRegister(&Mips::FGR64RegClass);
+    unsigned GPImpDef = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+    unsigned GPRRes = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+      BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), GPImpDef);
+      BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), GPRRes)
+          .addReg(GPImpDef)
+          .addReg(Src, RegState::Kill)
+          .addImm(Mips::sub_32);
+    if (Subtarget.hasMips3()) {
+      BuildMI(*BB, MI, DL, TII->get(Mips::DEXT), GPTemp)
+          .addReg(GPRRes)
+          .addImm(0)
+          .addImm(32);
+    } else {
+      unsigned GPTemp1 = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+      BuildMI(*BB, MI, DL, TII->get(Mips::DSLL), GPTemp1)
+          .addReg(GPRRes)
+          .addImm(32);
+      BuildMI(*BB, MI, DL, TII->get(Mips::DSRL), GPTemp)
+          .addReg(GPTemp1)
+          .addImm(32);
+    }
+    BuildMI(*BB, MI, DL, TII->get(Mips::DMTC1), FPSrc).addReg(GPTemp);
+    BuildMI(*BB, MI, DL, TII->get(CvtOp), Dest).addReg(FPSrc);
+    MI.eraseFromParent();
+    return BB;
+  } else if (IsFGR64onMips32 && !IsSrc64) {
+    unsigned FPTemp = RegInfo.createVirtualRegister(&Mips::FGR64RegClass);
+    BuildMI(*BB, MI, DL, TII->get(Mips::BuildPairF64_64), FPTemp)
+        .addReg(Src, RegState::Kill)
+        .addReg(Mips::ZERO);
+    BuildMI(*BB, MI, DL, TII->get(CvtOp), Dest).addReg(FPTemp);
+    MI.eraseFromParent();
+    return BB;
+  }
+
+  // Transfer the remainder of BB and its successor edges to exitMBB.
+  MachineFunction *MF = BB->getParent();
+  MachineBasicBlock *newMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+
+  MachineFunction::iterator It = ++BB->getIterator();
+  MF->insert(It, newMBB);
+  MF->insert(It, exitMBB);
+
+  exitMBB->splice(exitMBB->begin(), BB,
+                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
+  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
+
+  BB->addSuccessor(newMBB);
+  BB->addSuccessor(exitMBB);
+  newMBB->addSuccessor(exitMBB, BranchProbability::getOne());
+
+  unsigned FPSrc = RegInfo.createVirtualRegister(!IsSrc64 ? &Mips::FGR32RegClass
+                                                          : FPTempRegClass);
+  unsigned FPCvtResult = RegInfo.createVirtualRegister(FPTempRegClass);
+  unsigned FPAddValue = RegInfo.createVirtualRegister(FPTempRegClass);
+  unsigned FPAddResult = RegInfo.createVirtualRegister(FPTempRegClass);
+  unsigned FPDest = RegInfo.createVirtualRegister(FPTempRegClass);
+  unsigned GPAddValue = RegInfo.createVirtualRegister(GPSrcClass);
+
+  const uint64_t AddValue = IsSrc64 ? 0x43F0 : 0x41F0;
+
+  if (Subtarget.hasMips3() && IsSrc64)
+    BuildMI(BB, DL, TII->get(Mips::DMTC1), FPSrc).addReg(Src);
+  else
+    BuildMI(BB, DL, TII->get(Mips::MTC1), FPSrc).addReg(Src);
+
+  BuildMI(BB, DL, TII->get(CvtOp), FPCvtResult).addReg(FPSrc);
+  BuildMI(BB, DL, TII->get(IsSrc64 ? Mips::BGEZ64 : Mips::BGEZ))
+      .addReg(Src, RegState::Kill)
+      .addMBB(exitMBB);
+
+  BuildMI(newMBB, DL, TII->get(IsSrc64 ? Mips::LUi64 : Mips::LUi), GPAddValue)
+      .addImm(AddValue);
+
+  if (!IsFP64)
+    BuildMI(newMBB, DL, TII->get(Mips::BuildPairF64), FPAddValue)
+        .addReg(Mips::ZERO)
+        .addReg(GPAddValue);
+  else if (IsFGR64onMips32)
+    BuildMI(newMBB, DL, TII->get(Mips::BuildPairF64_64), FPAddValue)
+        .addReg(Mips::ZERO)
+        .addReg(GPAddValue);
+  else if (IsFGR64onMips64) {
+    unsigned GPTemp = RegInfo.createVirtualRegister(GPSrcClass);
+    BuildMI(newMBB, DL, TII->get(Mips::DSLL), GPTemp)
+        .addReg(GPAddValue)
+        .addImm(32);
+    BuildMI(newMBB, DL, TII->get(Mips::DMTC1), FPAddValue).addReg(GPTemp);
+  }
+
+  MachineBasicBlock::iterator exitMBBI = exitMBB->begin();
+  BuildMI(newMBB, DL, TII->get(FAddOp), FPAddResult)
+      .addReg(FPCvtResult)
+      .addReg(FPAddValue);
+  BuildMI(*exitMBB, exitMBBI, DL, TII->get(Mips::PHI), FPDest)
+      .addReg(FPCvtResult)
+      .addMBB(BB)
+      .addReg(FPAddResult)
+      .addMBB(newMBB); 
+  if (!IsSrc64 && !IsDest64 && !IsFP64) {
+    BuildMI(*exitMBB, exitMBBI, DL, TII->get(Mips::CVT_S_D32), Dest)
+        .addReg(FPDest);
+  } else {
+    BuildMI(*exitMBB, exitMBBI, DL, TII->get(Mips::COPY), Dest)
+        .addReg(FPDest);
+  }
+
+  MI.eraseFromParent();
+  return exitMBB;
+}
+
+// Emit the FpToUIntPseudo pseudo instruction.
+//
+// FP_TO_UINT FGR32Opnd:$fs, GPR32Opnd:$rd
+// =>
+//        lui     $rt1, 0x4F00
+//        mtc1    $ft1, $rt1
+//        c.le.s  $fcc0, $ft1, $fs
+//        bc1t    $fcc0,$L2
+//        nop
+//        trunc.w.s $f0,$f0
+//        mfc1    $2,$f0
+//        b       $L3
+//        nop
+// $L2:
+//        sub.s   $f0,$f0,$f1
+//        li      $3,-2147483648
+//        trunc.w.s $f0,$f0
+//        mfc1    $2,$f0
+//        or      $2,$2,$3
+// $L3:
+
+//
+// FP_TO_UINT FGR64Opnd:$fs, GPR32Opnd:$rd
+// For Mips32: Lowered to libcall
+// For Mips32r2 with FP64i:
+// TODO: Provide a combine that replaces fp_to_uint with the correct psuedo
+// that will generate the correct sequemce.
+//
+// For Mips64r2:
+// =>
+//        c.le.d  $fcc0,$f1,$f0
+//        bc1t    $fcc0,.L2
+//        nop
+//        trunc.l.d $f0,$f0
+//        dmfc1   $3,$f0
+//        b       .L3
+//        nop
+// .L2:
+//        sub.d   $f0,$f0,$f1
+//        lui     $2,0x8000
+//        trunc.l.d $f0,$f0
+//        dmfc1   $3,$f0
+//        or      $3,$3,$2
+// .L3:
+//
+// FP_TO_UINT FGR64Opnd:$rs, GPR64Opnd:$fd
+// For Mips32: Lowered to libcall
+// For Mips32 with 64-bit FPU:
+// =>
+//        c.le.d  $fcc0,$f1,$f0
+//        bc1t    $fcc0,$L2
+//        nop
+//        trunc.l.d $f0,$f0
+//        mfc1    $2,$f0
+//        mfhc1   $3,$f0
+//        b       $L3
+//        nop
+// $L2:
+//        lw      $2,%got($LC0)($28)
+//        ldc1    $f1,%lo($LC0)($2)
+//        sub.d   $f0,$f0,$f1
+//        trunc.l.d $f0,$f0
+//        mfc1    $2,$f0
+//        mfhc1   $3,$f0
+//        xori    $4,$2,0
+//        li      $6,-2147483648
+//        xor     $5,$3,$6
+//        move    $2,$4
+//        move    $3,$5
+// $L3:
+//
+// For Mips64r2:
+// =>
+//        c.le.d  $fcc0,$f1,$f0
+//        bc1t    $fcc0,.L2
+//        nop
+//        trunc.l.d $f0,$f0
+//        dmfc1   $3,$f0
+//        b       .L3
+//        nop
+// .L2:
+//        sub.d   $f0,$f0,$f1
+//        lui     $2,0x8000
+//        dsll    $2,$2,31
+//        trunc.l.d $f0,$f0
+//        dmfc1   $3,$f0
+//        or      $3,$3,$2
+// .L3:
+//
+MachineBasicBlock *MipsSETargetLowering::emitFP_TO_UINT(MachineInstr &MI,
+                                                        MachineBasicBlock *BB,
+                                                        unsigned TruncOp,
+                                                        unsigned FSubOp,
+                                                        bool IsFP64) const {
+
+  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+  DebugLoc DL = MI.getDebugLoc();
+  const BasicBlock *LLVM_BB = BB->getBasicBlock();
+
+  const bool IsFGR64onMips64 = Subtarget.hasMips3() && IsFP64;
+  const bool IsFGR64onMips32 = !Subtarget.hasMips3() && IsFP64;
+
+  unsigned Dest = MI.getOperand(0).getReg();
+  unsigned Src = MI.getOperand(1).getReg();
+
+  const TargetRegisterClass *GPDestClass = RegInfo.getRegClass(Dest);
+  const TargetRegisterClass *FPSrcClass = RegInfo.getRegClass(Src);
+
+  const bool IsSrc64 = FPSrcClass != &Mips::FGR32RegClass;
+  const bool IsDest64 = GPDestClass == &Mips::GPR64RegClass;
+
+  // Transfer the remainder of BB and its successor edges to exitMBB.
+  MachineFunction *MF = BB->getParent();
+  MachineBasicBlock *truncateMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *correctionMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
+
+  MachineFunction::iterator It = ++BB->getIterator();
+  MF->insert(It, truncateMBB);
+  MF->insert(It, correctionMBB);
+  MF->insert(It, exitMBB);
+
+  exitMBB->splice(exitMBB->begin(), BB,
+                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
+  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
+
+  BB->addSuccessor(truncateMBB);
+  BB->addSuccessor(correctionMBB);
+  correctionMBB->addSuccessor(exitMBB, BranchProbability::getOne());
+  truncateMBB->addSuccessor(exitMBB, BranchProbability::getOne());
+  unsigned GPSubValue = RegInfo.createVirtualRegister(
+      (IsSrc64 && IsFGR64onMips64) ? &Mips::GPR64RegClass
+                                   : &Mips::GPR32RegClass);
+  unsigned FPSubValue = RegInfo.createVirtualRegister(
+      IsSrc64 ? (IsFP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass)
+              : &Mips::FGR32RegClass);
+  unsigned TruncatedValue1 = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::FGR64RegClass : &Mips::FGR32RegClass);
+  unsigned TruncatedValue2 = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::FGR64RegClass : &Mips::FGR32RegClass);
+  unsigned TempResult1 = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+  unsigned TempResult2 = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+  unsigned SubtractedValue = RegInfo.createVirtualRegister(
+      IsSrc64 ? (IsFP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass)
+              : &Mips::FGR32RegClass);
+  unsigned TruncatedValueGP = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+  unsigned MSBBit = RegInfo.createVirtualRegister(
+      IsDest64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass);
+
+  const uint64_t SubValue = IsSrc64 ? 0x41E0 : (IsDest64 ? 0x5F00 : 0x4F00);
+
+  BuildMI(BB, DL,
+          TII->get((IsSrc64 && IsFGR64onMips64) ? Mips::LUi64 : Mips::LUi),
+          GPSubValue)
+      .addImm(SubValue);
+
+  if (IsSrc64) {
+    if (!IsFP64)
+      BuildMI(BB, DL, TII->get(Mips::BuildPairF64), FPSubValue)
+          .addReg(Mips::ZERO)
+          .addReg(GPSubValue);
+    else if (IsFGR64onMips32)
+      BuildMI(BB, DL, TII->get(Mips::BuildPairF64_64), FPSubValue)
+          .addReg(Mips::ZERO)
+          .addReg(GPSubValue);
+    else {
+      unsigned GPTemp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+      BuildMI(BB, DL, TII->get(Mips::DSLL32), GPTemp)
+          .addReg(GPSubValue)
+          .addImm(0);
+      BuildMI(BB, DL, TII->get(Mips::DMTC1), FPSubValue).addReg(GPTemp);
+    }
+  } else
+    BuildMI(BB, DL, TII->get(Mips::MTC1), FPSubValue).addReg(GPSubValue);
+  BuildMI(BB, DL,
+          TII->get(IsSrc64 ? (IsFP64 ? Mips::C_LE_D64 : Mips::C_LE_D32)
+                           : Mips::C_LE_S),
+          Mips::FCC0)
+      .addReg(FPSubValue)
+      .addReg(Src);
+  BuildMI(BB, DL, TII->get(Mips::BC1T))
+      .addReg(Mips::FCC0)
+      .addMBB(correctionMBB);
+
+  BuildMI(truncateMBB, DL, TII->get(TruncOp), TruncatedValue1)
+      .addReg(Src, RegState::Kill);
+
+  if (IsDest64) {
+    if (IsFGR64onMips32)
+      BuildMI(truncateMBB, DL, TII->get(Mips::ExtractElementF64_64),
+              TempResult1)
+          .addReg(TruncatedValue1);
+    else if (IsFGR64onMips64)
+      BuildMI(truncateMBB, DL, TII->get(Mips::DMFC1), TempResult1)
+          .addReg(TruncatedValue1);
+  } else {
+    BuildMI(truncateMBB, DL, TII->get(Mips::MFC1), TempResult1)
+        .addReg(TruncatedValue1);
+  }
+
+  BuildMI(truncateMBB, DL, TII->get(Mips::B)).addMBB(exitMBB);
+
+  BuildMI(correctionMBB, DL, TII->get(FSubOp), SubtractedValue)
+      .addReg(Src, RegState::Kill)
+      .addReg(FPSubValue);
+  BuildMI(correctionMBB, DL, TII->get(TruncOp), TruncatedValue2)
+      .addReg(SubtractedValue);
+
+  if (IsDest64) {
+    unsigned GPTemp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
+    if (IsFGR64onMips32)
+      BuildMI(correctionMBB, DL, TII->get(Mips::ExtractElementF64_64),
+              TruncatedValueGP)
+          .addReg(TruncatedValue2);
+    else
+      BuildMI(correctionMBB, DL, TII->get(Mips::DMFC1), TruncatedValueGP)
+          .addReg(TruncatedValue2);
+    // FIXME: The delay slot filler fails to schedule LUi(64) into the delay
+    // slot of the BC1T.
+    BuildMI(correctionMBB, DL, TII->get(Mips::LUi64), MSBBit).addImm(0x8000);
+    BuildMI(correctionMBB, DL, TII->get(Mips::DSLL), GPTemp)
+        .addReg(MSBBit)
+        .addImm(31);
+    BuildMI(correctionMBB, DL, TII->get(Mips::OR64), TempResult2)
+        .addReg(TruncatedValueGP)
+        .addReg(GPTemp);
+  } else {
+    BuildMI(correctionMBB, DL, TII->get(Mips::MFC1), TruncatedValueGP)
+        .addReg(TruncatedValue2);
+    BuildMI(correctionMBB, DL, TII->get(Mips::LUi), MSBBit).addImm(0x8000);
+    BuildMI(correctionMBB, DL, TII->get(Mips::OR), TempResult2)
+        .addReg(TruncatedValueGP)
+        .addReg(MSBBit);
+  }
+
+  BuildMI(*exitMBB, exitMBB->begin(), DL, TII->get(Mips::PHI), Dest)
+      .addReg(TempResult1)
+      .addMBB(truncateMBB)
+      .addReg(TempResult2)
+      .addMBB(correctionMBB);
+
+  MI.eraseFromParent();
+  return exitMBB;
+}
+
 // Emit the FEXP2_W_1 pseudo instructions.
 //
 // fexp2_w_1_pseudo $wd, $wt
 // =>
 // ldi.w $ws, 1
 // fexp2.w $wd, $ws, $wt
 MachineBasicBlock *
 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr &MI,
                                     MachineBasicBlock *BB) const {
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
   const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
   unsigned Ws1 = RegInfo.createVirtualRegister(RC);
   unsigned Ws2 = RegInfo.createVirtualRegister(RC);
   DebugLoc DL = MI.getDebugLoc();
 
   // Splat 1.0 into a vector
   BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
   BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
 
   // Emit 1.0 * fexp2(Wt)
   BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
       .addReg(Ws2)
       .addReg(MI.getOperand(1).getReg());

test/CodeGen/Mips/2008-07-07-Float2Int.ll

 ; RUN: llc -march=mips < %s | FileCheck %s
 
 define i32 @fptoint(float %a) nounwind {
 entry:
+; CHECK-LABEL: fptoint
 ; CHECK: trunc.w.s 
   fptosi float %a to i32    ; <i32>:0 [#uses=1]
   ret i32 %0
 }
 
 define i32 @fptouint(float %a) nounwind {
 entry:
-; CHECK: fptouint
-; CHECK: trunc.w.s 
+; CHECK-LABEL: fptouint
 ; CHECK: trunc.w.s 
   fptoui float %a to i32    ; <i32>:0 [#uses=1]
   ret i32 %0
 }

test/CodeGen/Mips/cconv/vector.ll

 
 define float @mixed_i8(<2 x float> %a, i8 %b, <2 x float> %c) {
 entry:
 ; ALL-LABEL: mixed_i8:
 
 ; MIPS32-DAG: mtc1 $5, $f{{[0-9]+}}
 ; MIPS32: andi $[[R7:[0-9]+]], $6, 255
 ; MIPS32: mtc1 $[[R7]], $f[[F0:[0-9]+]]
-; MIPS32: cvt.s.w $f{{[0-9]+}}, $f[[F0]]
+; MIPS32: cvt.d.w $f{{[0-9]+}}, $f[[F0]]
 
 ; MIPS32-DAG: mtc1 $4, $f{{[0-9]+}}
 ; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 16($sp)
 ; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 20($sp)
 ; MIPS32-DAG: add.s $f0, $f{{[0-9]+}}, $f{{[0-9]+}}
 
 ; MIPS32R5: andi $[[R0:[0-9]+]], $6, 255
 ; MIPS32R5: sw $[[R0]], {{[0-9]+}}($sp)
 ; MIPS32R5: sw $[[R0]], {{[0-9]+}}($sp)
 ; MIPS32R5-DAG: sw $5, {{[0-9]+}}($sp)
 ; MIPS32R5-DAG: sw $4, {{[0-9]+}}($sp)
 
 ; MIPS64EB-DAG: sll $[[R0:[0-9]+]], $4, 0
 ; MIPS64EB-DAG: mtc1 $[[R0]], $f{{[0-9]+}}
 ; MIPS64EB: sll $[[R6:[0-9]+]], $5, 0
 ; MIPS64EB: andi $[[R7:[0-9]+]], $[[R6]], 255
 ; MIPS64EB: mtc1 $[[R7]], $f[[F0:[0-9]+]]
-; MIPS64EB: cvt.s.w $f{{[0-9]+}}, $f[[F0]]
+; MIPS64EB: cvt.s.l $f{{[0-9]+}}, $f[[F0]]
 
 ; MIPS64EB-DAG: dsrl $[[R1:[0-9]+]], $4, 32
 ; MIPS64EB-DAG: sll $[[R2:[0-9]+]], $[[R1]], 0
 ; MIPS64EB-DAG: mtc1 $[[R2:[0-9]+]], $f{{[0-9]+}}
 
 ; MIPS64EB-DAG: sll $[[R3:[0-9]+]], $6, 0
 ; MIPS64EB-DAG: mtc1 $[[R3]], $f{{[0-9]+}}
 ; MIPS64EB-DAG: dsrl $[[R4:[0-9]+]], $6, 32
 ; MIPS64EB-DAG: sll $[[R5:[0-9]+]], $[[R4]], 0
 ; MIPS64EB-DAG: mtc1 $[[R5:[0-9]+]], $f{{[0-9]+}}
 
 ; MIPS64EL-DAG: dsrl $[[R1:[0-9]+]], $4, 32
 ; MIPS64EL-DAG: sll $[[R2:[0-9]+]], $[[R1]], 0
 ; MIPS64EL-DAG: mtc1 $[[R2:[0-9]+]], $f{{[0-9]+}}
 
 ; MIPS64EL: sll $[[R6:[0-9]+]], $5, 0
 ; MIPS64EL: andi $[[R7:[0-9]+]], $[[R6]], 255
 ; MIPS64EL: mtc1 $[[R7]], $f[[F0:[0-9]+]]
-; MIPS64EL: cvt.s.w $f{{[0-9]+}}, $f[[F0]]
+; MIPS64EL: cvt.s.l $f{{[0-9]+}}, $f[[F0]]
 
 ; MIPS64EL-DAG: dsrl $[[R4:[0-9]+]], $6, 32
 ; MIPS64EL-DAG: sll $[[R5:[0-9]+]], $[[R4]], 0
 ; MIPS64EL-DAG: mtc1 $[[R5:[0-9]+]], $f{{[0-9]+}}
 
 ; MIPS64EL-DAG: sll $[[R0:[0-9]+]], $4, 0
 ; MIPS64EL-DAG: mtc1 $[[R0]], $f{{[0-9]+}}
 ; MIPS64EL-DAG: sll $[[R3:[0-9]+]], $6, 0

 }
 
 define <4 x float> @mixed_32(<4 x float> %a, i32 %b) {
 entry:
 ; ALL-LABEL: mixed_32:
 
 ; MIPS32-DAG: mtc1 $6, $f{{[0-9]+}}
 ; MIPS32-DAG: mtc1 $7, $f{{[0-9]+}}
-; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 28($sp)
-; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 24($sp)
+; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 20($sp)
+; MIPS32-DAG: lwc1 $f{{[0-9]+}}, 16($sp)
 ; MIPS32-DAG: swc1 $f{{[0-9]+}}, 0($4)
 ; MIPS32-DAG: swc1 $f{{[0-9]+}}, 4($4)
 ; MIPS32-DAG: swc1 $f{{[0-9]+}}, 8($4)
 ; MIPS32-DAG: swc1 $f{{[0-9]+}}, 12($4)
 
 ; MIPS32R5: insert.w $w[[W0:[0-9]+]][0], $6
 ; MIPS32R5: insert.w $w[[W0:[0-9]+]][1], $7
 ; MIPS32R5: lw $[[R0:[0-9]+]], 16($sp)

 ; This test is slightly more fragile than I'd like as the offset into the
 ; outgoing arguments area is dependant on the size of the stack frame for
 ; this function.
 
 define <4 x float> @cast(<4 x i32> %a) {
 entry:
 ; ALL-LABEL: cast:
 
-; MIPS32: addiu $sp, $sp, -32
-; MIPS32-DAG: sw $6, {{[0-9]+}}($sp)
-; MIPS32-DAG: sw $7, {{[0-9]+}}($sp)
-; MIPS32-DAG: lw ${{[0-9]+}}, 48($sp)
-; MIPS32-DAG: lw ${{[0-9]+}}, 52($sp)
-
 ; MIPS32R5-DAG: insert.w  $w0[0], $6
 ; MIPS32R5-DAG: insert.w  $w0[1], $7
 ; MIPS32R5-DAG: lw  $[[R0:[0-9]+]], 16($sp)
 ; MIPS32R5-DAG: insert.w  $w0[2], $[[R0]]
 ; MIPS32R5-DAG: lw  $[[R1:[0-9]+]], 20($sp)
 ; MIPS32R5-DAG: insert.w  $w0[3], $[[R1]]
 
 ; MIPS64-DAG: sll ${{[0-9]+}}, $4, 0

test/CodeGen/Mips/mips64-f128.ll

 
 define i64 @conv_LL_LD(fp128 %a) {
 entry:
   %conv = fptosi fp128 %a to i64
   ret i64 %conv
 }
 
 ; ALL-LABEL: conv_UChar_LD:
-; ALL: ld $25, %call16(__fixtfsi)
+; ALL: ld $25, %call16(__fixunstfsi)
 
 define zeroext i8 @conv_UChar_LD(fp128 %a) {
 entry:
   %conv = fptoui fp128 %a to i8
   ret i8 %conv
 }
 
 ; ALL-LABEL: conv_UShort_LD:
-; ALL: ld $25, %call16(__fixtfsi)
+; ALL: ld $25, %call16(__fixunstfsi)
 
 define zeroext i16 @conv_UShort_LD(fp128 %a) {
 entry:
   %conv = fptoui fp128 %a to i16
   ret i16 %conv
 }
 
 ; ALL-LABEL: conv_UInt_LD:

test/CodeGen/Mips/msa/f16-llvm-ir.ll

 }
 
 define i32 @ffptoui() {
 entry:
 ; ALL-LABEL: ffptoui:
   %0 = load half, half * @h, align 2
   %1 = fptoui half %0 to i32
 
-; MIPS32:       lwc1 $f[[FC:[0-9]+]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64-N32:   lwc1 $f[[FC:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64-N64:   lwc1 $f[[FC:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-
-; ALL:          lh $[[R0:[0-9]+]]
-; ALL:          fill.h $w[[W0:[0-9]+]], $[[R0]]
-; ALL:          fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
-; ALL:          copy_s.w $[[R1:[0-9]+]], $w[[W1]][0]
-; ALL:          mtc1 $[[R1]], $f[[F0:[0-9]+]]
-; MIPSR6:       cmp.lt.s  $f[[F1:[0-9]+]], $f[[F0]], $f[[FC]]
-; ALL:          sub.s $f[[F2:[0-9]+]], $f[[F0]], $f[[FC]]
-; ALL:          mfc1 $[[R2:[0-9]]], $f[[F2]]
-; ALL:          fill.w $w[[W2:[0-9]+]], $[[R2]]
-; ALL:          fexdo.h $w[[W3:[0-9]+]], $w[[W2]], $w[[W2]]
-; ALL:          fexupr.w $w[[W4:[0-9]+]], $w[[W3]]
-; ALL:          fexupr.d $w[[W5:[0-9]+]], $w[[W4]]
-
-; MIPS32:       copy_s.w $[[R3:[0-9]+]], $w[[W5]][0]
-; MIPS32:       mtc1 $[[R3]], $f[[F3:[0-9]+]]
-; MIPS32:       copy_s.w $[[R4:[0-9]+]], $w[[W5]][1]
-; MIPS32:       mthc1 $[[R3]], $f[[F3]]
-
-; MIPS64:       copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
-; MIPS64:       dmtc1 $[[R2]], $f[[F3:[0-9]+]]
-
-; ALL:          trunc.w.d $f[[F4:[0-9]+]], $f[[F3]]
-; ALL:          mfc1 $[[R4:[0-9]+]], $f[[F4]]
-; ALL:          fexupr.d $w[[W6:[0-9]+]], $w[[W1]]
-
-; MIPS32:       copy_s.w $[[R5:[0-9]+]], $w[[W6]][0]
-; MIPS32:       mtc1 $[[R5]], $f[[F5:[0-9]+]]
-; MIPS32:       copy_s.w $[[R6:[0-9]+]], $w[[W6]][1]
-; MIPS32:       mthc1 $[[R6]], $f[[F5]]
-
-; MIPS64:       copy_s.d $[[R2:[0-9]+]], $w[[W2]][0]
-; MIPS64:       dmtc1 $[[R2]], $f[[F5:[0-9]+]]
-
-; ALL:          trunc.w.d $f[[F6:[0-9]]], $f[[F5]]
-; ALL:          mfc1 $[[R7:[0-9]]], $f[[F6]]
-
-; MIPS32R5-O32: lw $[[R13:[0-9]+]], %got($CPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS32R5-O32: addiu $[[R14:[0-9]+]], $[[R13]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
-
-; MIPS64R5-N32: lw $[[R13:[0-9]+]], %got_page(.LCPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64R5-N32: addiu $[[R14:[0-9]+]], $[[R13]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-
-; MIPS64R5-N64: ld $[[R13:[0-9]+]], %got_page(.LCPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64R5-N64: daddiu $[[R14:[0-9]+]], $[[R13]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-
-; ALL:          lui $[[R8:[0-9]+]], 32768
-; ALL:          xor $[[R9:[0-9]+]], $[[R4]], $[[R8]]
-
-; MIPSR5:       lh $[[R15:[0-9]+]], 0($[[R14]])
-; MIPSR5:       fill.h $w[[W7:[0-9]+]], $[[R15]]
-; MIPSR5:       fexupr.w $w[[W8:[0-9]+]], $w[[W7]]
-; MIPSR5:       copy_s.w $[[R16:[0-9]+]], $w[[W8]][0]
-; MIPSR5:       mtc1 $[[R16]], $f[[F7:[0-9]+]]
-; MIPSR5:       c.olt.s $f[[F0]], $f[[F7]]
-; MIPSR5:       movt $[[R9]], $[[R7]], $fcc0
-
-; MIPSR6:       mfc1 $[[R10:[0-9]+]], $f[[F1]]
-; MIPSR6:       seleqz $[[R11:[0-9]]], $[[R9]], $[[R10]]
-; MIPSR6:       selnez $[[R12:[0-9]]], $[[R7]], $[[R10]]
-; MIPSR6:       or $2, $[[R12]], $[[R11]]
+; ALL: lh $[[R0:[0-9]+]]
+; ALL: fill.h $w[[W0:[0-9]+]], $[[R0]]
+; ALL: fexupr.w $w[[W1:[0-9]+]], $w[[W0]]
+; ALL: ftint_u.w $w[[W2:[0-9]+]], $w[[W1]]
+; ALL: copy_u.w $2, $w[[W2]][0]
 
   ret i32 %1
 }
 
 define i32 @ffptosi() {
 entry:
 ; ALL-LABEL: ffptosi:
   %0 = load half, half * @h, align 2

 ; ALL:    trunc.w.d $f[[F1:[0-9]+]], $f[[F0]]
 ; ALL:    mfc1 $2, $f[[F1]]
 }
 
 define void @uitofp(i32 %a) {
 entry:
 ; ALL-LABEL: uitofp:
 
-; MIPS32-O32: ldc1 $f[[F0:[0-9]+]], %lo($CPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS32-O32: ldc1 $f[[F1:[0-9]+]], 0($sp)
-
-; MIPS64-N32: ldc1 $f[[F0:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64-N32: ldc1 $f[[F1:[0-9]+]], 8($sp)
-
-; MIPS64-N64: ldc1 $f[[F0:[0-9]+]], %got_ofst(.LCPI{{[0-9]+}}_{{[0-9]+}})
-; MIPS64-N64: ldc1 $f[[F1:[0-9]+]], 8($sp)
+; MIPS32:     lw $[[R3:[0-9]+]], %got(h)
+; MIPS32:     fill.w $w[[W0:[0-9]+]], $4
+; MIPS32:     ffint_u.w $w[[W1:[0-9]+]], $w[[W0]]
 
-; MIPSR5:     sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
-; MIPSR6-O32: sub.d $f[[F2:[0-9]+]], $f[[F0]], $f[[F1]]
-; MIPSR6-N32: sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
-; MIPSR6-N64: sub.d $f[[F2:[0-9]+]], $f[[F1]], $f[[F0]]
-
-; MIPS32:     mfc1 $[[R0:[0-9]+]], $f[[F2]]
-; MIPS32:     fill.w $w[[W0:[0-9]+]], $[[R0]]
-; MIPS32:     mfhc1 $[[R1:[0-9]+]], $f[[F2]]
-; MIPS32:     insert.w $w[[W0]][1], $[[R1]]
-; MIPS32:     insert.w $w[[W0]][3], $[[R1]]
-
-; MIPS64-N64-DAG: ld $[[R3:[0-9]+]], %got_disp(h)
+; MIPS64-DAG:     sll $[[R1:[0-9]+]], $4, 0
 ; MIPS64-N32-DAG: lw $[[R3:[0-9]+]], %got_disp(h)
-; MIPS64-DAG:     dmfc1 $[[R1:[0-9]+]], $f[[F2]]
-; MIPS64-DAG:     fill.d $w[[W0:[0-9]+]], $[[R1]]
+; MIPS64-N64-DAG: ld $[[R3:[0-9]+]], %got_disp(h)
+; MIPS64-DAG:     fill.w $w[[W0:[0-9]+]], $[[R1]]
 
-; ALL-DAG:        fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]
 ; ALL-DAG:        fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]
 
-; MIPS32-DAG:     lw $[[R3:[0-9]+]], %got(h)
-
 ; ALL:        copy_u.h $[[R2:[0-9]+]], $w[[W2]]
 ; ALL:        sh $[[R2]], 0($[[R3]])
   %0 = uitofp i32 %a to half
   store half %0, half * @h, align 2
   ret void
 }