[AARCH64] Incorrect relocation name TLSDESC_LD64_LO12_NC

[joelkevinjones]

Summary

The document "ELF for the ARM 64-bit Architecture (AArch64)" at http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056c/IHI0056C_beta_aaelf64.pdf
gives the name as R_AARCH64_TLSDESC_LD64_LO12 (NB: without the trailing "_NC").

This patch fixes the naming, adjusts tests, and modifies the asm printer to remove the VK_NC target flag when expanding TLSDESC_CALLSEQ.

[joelkevinjones]

This revision is included in an omnibus ILP32 relocation change: https://reviews.llvm.org/D32072

include/llvm/Support/ELFRelocs/AArch64.def

 ELF_RELOC(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,      0x22b)
 ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12,         0x22c)
 ELF_RELOC(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,      0x22d)
 ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12,         0x22e)
 ELF_RELOC(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,      0x22f)
 ELF_RELOC(R_AARCH64_TLSDESC_LD_PREL19,               0x230)
 ELF_RELOC(R_AARCH64_TLSDESC_ADR_PREL21,              0x231)
 ELF_RELOC(R_AARCH64_TLSDESC_ADR_PAGE21,              0x232)
-ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12_NC,            0x233)
-ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12_NC,             0x234)
+ELF_RELOC(R_AARCH64_TLSDESC_LD64_LO12,               0x233)
+ELF_RELOC(R_AARCH64_TLSDESC_ADD_LO12,                0x234)
 ELF_RELOC(R_AARCH64_TLSDESC_OFF_G1,                  0x235)
 ELF_RELOC(R_AARCH64_TLSDESC_OFF_G0_NC,               0x236)
 ELF_RELOC(R_AARCH64_TLSDESC_LDR,                     0x237)
 ELF_RELOC(R_AARCH64_TLSDESC_ADD,                     0x238)
 ELF_RELOC(R_AARCH64_TLSDESC_CALL,                    0x239)
 ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12,        0x23a)
 ELF_RELOC(R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC,     0x23b)
 ELF_RELOC(R_AARCH64_TLSLD_LDST128_DTPREL_LO12,       0x23c)

 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC,   0x071)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,     0x072)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,  0x073)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,     0x074)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,  0x075)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,     0x076)
 ELF_RELOC(R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,  0x077)
 ELF_RELOC(R_AARCH64_P32_TLSDESC_ADR_PAGE21,          0x051)
-ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12_NC,        0x07d)
-ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12_NC,         0x034)
+ELF_RELOC(R_AARCH64_P32_TLSDESC_LD32_LO12,           0x07d)
+ELF_RELOC(R_AARCH64_P32_TLSDESC_ADD_LO12,            0x034)
 ELF_RELOC(R_AARCH64_P32_TLSDESC_CALL,                0x07f)
 ELF_RELOC(R_AARCH64_P32_COPY,                        0x0b4)
 ELF_RELOC(R_AARCH64_P32_GLOB_DAT,                    0x0b5)
 ELF_RELOC(R_AARCH64_P32_JUMP_SLOT,                   0x0b6)
 ELF_RELOC(R_AARCH64_P32_RELATIVE,                    0x0b7)
 ELF_RELOC(R_AARCH64_P32_IRELATIVE,                   0x0bc)

lib/Target/AArch64/AArch64AsmPrinter.cpp

case AArch64::TLSDESC_CALLSEQ: {
     ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
     ///    add   x0, x0, #:tlsdesc_lo12:var
     ///    .tlsdesccall var
     ///    blr   x1
     ///    (TPIDR_EL0 offset now in x0)
     const MachineOperand &MO_Sym = MI->getOperand(0);
     MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
     MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
-    MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
-                                   AArch64II::MO_NC);
+    MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
     MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
     MCInstLowering.lowerOperand(MO_Sym, Sym);
     MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
     MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
 
     MCInst Adrp;
     Adrp.setOpcode(AArch64::ADRP);
     Adrp.addOperand(MCOperand::createReg(AArch64::X0));

lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

case AArch64::fixup_aarch64_add_imm12:
         return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
       if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
         return R_CLS(TLSLD_ADD_DTPREL_LO12);
       if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
         return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
       if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
         return R_CLS(TLSLE_ADD_TPREL_LO12);
       if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
-        return R_CLS(TLSDESC_ADD_LO12_NC);
+        return R_CLS(TLSDESC_ADD_LO12);
       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
         return R_CLS(ADD_ABS_LO12_NC);
 
       Ctx.reportError(Fixup.getLoc(),
                       "invalid fixup for add (uimm12) instruction");
       return ELF::R_AARCH64_NONE;
     case AArch64::fixup_aarch64_ldst_imm12_scale1:
       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
case AArch64::fixup_aarch64_ldst_imm12_scale4:
       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
         return R_CLS(TLSLD_LDST32_DTPREL_LO12);
       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
         return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
         return R_CLS(TLSLE_LDST32_TPREL_LO12);
       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
         return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
+      if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
+        if (IsILP32) {
+          return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
+        } else {
+          Ctx.reportError(Fixup.getLoc(),
+                          "LP64 4 byte TLSDESC load/store relocation "
+                          "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
+          return ELF::R_AARCH64_NONE;
+        }
+      }
 
       Ctx.reportError(Fixup.getLoc(),
                       "invalid fixup for 32-bit load/store instruction");
       return ELF::R_AARCH64_NONE;
     case AArch64::fixup_aarch64_ldst_imm12_scale8:
       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
         return R_CLS(LDST64_ABS_LO12_NC);
       if (SymLoc == AArch64MCExpr::VK_GOT && IsNC)
         return R_CLS(LD64_GOT_LO12_NC);
       if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
         return R_CLS(TLSLD_LDST64_DTPREL_LO12);
       if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
         return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
       if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
         return R_CLS(TLSLE_LDST64_TPREL_LO12);
       if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
         return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
       if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC)
         return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC
                        : ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
-      if (SymLoc == AArch64MCExpr::VK_TLSDESC && IsNC)
-        return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC
-                       : ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
+      if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
+        if (IsILP32) {
+          Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
+                          "relocation not supported (LP64 eqv: "
+                          "TLSDESC_LD64_LO12");
+          return ELF::R_AARCH64_NONE;
+        } else {
+          return ELF::R_AARCH64_TLSDESC_LD64_LO12;
+        }
+      }
 
       Ctx.reportError(Fixup.getLoc(),
                       "invalid fixup for 64-bit load/store instruction");
       return ELF::R_AARCH64_NONE;
     case AArch64::fixup_aarch64_ldst_imm12_scale16:
       if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
         return R_CLS(LDST128_ABS_LO12_NC);
 

lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h

enum VariantKind {
     VK_TPREL_G2          = VK_TPREL    | VK_G2,
     VK_TPREL_G1          = VK_TPREL    | VK_G1,
     VK_TPREL_G1_NC       = VK_TPREL    | VK_G1      | VK_NC,
     VK_TPREL_G0          = VK_TPREL    | VK_G0,
     VK_TPREL_G0_NC       = VK_TPREL    | VK_G0      | VK_NC,
     VK_TPREL_HI12        = VK_TPREL    | VK_HI12,
     VK_TPREL_LO12        = VK_TPREL    | VK_PAGEOFF,
     VK_TPREL_LO12_NC     = VK_TPREL    | VK_PAGEOFF | VK_NC,
-    VK_TLSDESC_LO12      = VK_TLSDESC  | VK_PAGEOFF | VK_NC,
+    VK_TLSDESC_LO12      = VK_TLSDESC  | VK_PAGEOFF,
     VK_TLSDESC_PAGE      = VK_TLSDESC  | VK_PAGE,
 
     VK_INVALID  = 0xfff
   };
 
 private:
   const MCExpr *Expr;
   const VariantKind Kind;

test/CodeGen/AArch64/arm64-tls-dynamics.ll

 
 
 ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
 ; CHECK: ldr w0, [x[[TP]], x0]
 ; CHECK-NOLD: mrs x[[TP:[0-9]+]], TPIDR_EL0
 ; CHECK-NOLD: ldr w0, [x[[TP]], x0]
 
 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
 
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
 
 }
 
 define i32* @test_generaldynamic_addr() {
 ; CHECK-LABEL: test_generaldynamic_addr:
 
   ret i32* @general_dynamic_var
 
 ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
 ; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
 ; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
 ; CHECK-NEXT: .tlsdesccall general_dynamic_var
 ; CHECK-NEXT: blr [[CALLEE]]
 
 ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
 ; CHECK: add x0, [[TP]], x0
 
 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
 
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
 
 }
 
 @local_dynamic_var = external thread_local(localdynamic) global i32
 
 define i32 @test_localdynamic() {
 ; CHECK-LABEL: test_localdynamic:

 ; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var
 ; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var
 ; CHECK-NOLD-NEXT: blr [[CALLEE]]
 ; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
 ; CHECK-NOLD: ldr w0, [x[[TPIDR]], x0]
 
 
 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
 
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
 
 }
 
 define i32* @test_localdynamic_addr() {
 ; CHECK-LABEL: test_localdynamic_addr:
 
 ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_

 ; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var
 ; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var
 ; CHECK-NOLD-NEXT: blr [[CALLEE]]
 ; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
 ; CHECK-NOLD: add x0, x[[TPIDR]], x0
   ret i32* @local_dynamic_var
 
 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
 ; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
 
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
 ; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
 }
 
 ; The entire point of the local-dynamic access model is to have a single call to
 ; the expensive resolver. Make sure we achieve that goal.
 
 @local_dynamic_var2 = external thread_local(localdynamic) global i32
 

test/MC/AArch64/arm32-elf-relocs.s

 // CHECK-OBJ-ILP32: c R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym
 
    add x9, x12, #:tprel_lo12_nc:sym
 // CHECK: add x9, x12, :tprel_lo12_nc:sym
 // CHECK-OBJ-ILP32: 10 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym
 
    add x5, x0, #:tlsdesc_lo12:sym
 // CHECK: add x5, x0, :tlsdesc_lo12:sym
-// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym
+// CHECK-OBJ-ILP32: 14 R_AARCH64_P32_TLSDESC_ADD_LO12 sym
 
         add x0, x2, #:lo12:sym+8
 // CHECK: add x0, x2, :lo12:sym
 // CHECK-OBJ-ILP32: 18 R_AARCH64_P32_ADD_ABS_LO12_NC sym+8
 
    add x5, x7, #:dtprel_lo12:sym+1
 // CHECK: add x5, x7, :dtprel_lo12:sym+1
 // CHECK-OBJ-ILP32: 1c R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12 sym+1
 
    add x9, x12, #:dtprel_lo12_nc:sym+2
 // CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
 // CHECK-OBJ-ILP32:20 R_AARCH64_P32_TLSLD_ADD_DTPREL_LO12_NC sym+2
 
    add x20, x30, #:tprel_lo12:sym+12
 // CHECK: add x20, x30, :tprel_lo12:sym+12
 // CHECK-OBJ-ILP32: 24 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12 sym+12
 
    add x9, x12, #:tprel_lo12_nc:sym+54
 // CHECK: add x9, x12, :tprel_lo12_nc:sym+54
 // CHECK-OBJ-ILP32: 28 R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC sym+54
 
    add x5, x0, #:tlsdesc_lo12:sym+70
 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
-// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12_NC sym+70
+// CHECK-OBJ-ILP32: 2c R_AARCH64_P32_TLSDESC_ADD_LO12 sym+70
 
         .hword sym + 4 - .
 // CHECK-OBJ-ILP32: 30 R_AARCH64_P32_PREL16 sym+4
         .word sym - . + 8
 // CHECK-OBJ-ILP32 32 R_AARCH64_P32_PREL32 sym+8
 
         .hword sym
 // CHECK-OBJ-ILP32 3e R_AARCH64_P32_ABS16 sym

 // CHECK: ldr x24, [x23, :tprel_lo12:sym]
 // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
 // CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12 sym
 // CHECK-OBJ-ILP32 R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC sym
 
 #   ldr x24, [x23, :gottprel_lo12:sym]
 #   ldr d22, [x21, #:gottprel_lo12:sym]
 
-   ldr x24, [x23, #:tlsdesc_lo12:sym]
-   ldr d22, [x21, :tlsdesc_lo12:sym]
-// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
-// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
-// Why is there a "_NC" at the end? "ELF for the ARM 64-bit architecture
-// (AArch64) beta" doesn't have that.
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12_NC sym
-// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12_NC sym
+   ldr w24, [x23, #:tlsdesc_lo12:sym]
+   ldr s22, [x21, :tlsdesc_lo12:sym]
+// CHECK: ldr w24, [x23, :tlsdesc_lo12:sym]
+// CHECK: ldr s22, [x21, :tlsdesc_lo12:sym]
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD32_LO12 sym
+// CHECK-OBJ-ILP32 R_AARCH64_P32_TLSDESC_LD64_LO12 sym
 
    ldr q20, [x19, #:lo12:sym]
 // CHECK: ldr q20, [x19, :lo12:sym]
 // CHECK-OBJ-ILP32 R_AARCH64_P32_LDST128_ABS_LO12_NC sym
 
 // Since relocated instructions print without a '#', that syntax should
 // certainly be accepted when assembling.
    add x3, x5, :lo12:imm
 // CHECK: add x3, x5, :lo12:imm

test/MC/AArch64/arm64-elf-relocs.s

 // CHECK-OBJ-LP64: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
 
    add x9, x12, #:tprel_lo12_nc:sym
 // CHECK: add x9, x12, :tprel_lo12_nc:sym
 // CHECK-OBJ-LP64: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
 
    add x5, x0, #:tlsdesc_lo12:sym
 // CHECK: add x5, x0, :tlsdesc_lo12:sym
-// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
+// CHECK-OBJ-LP64: 14 R_AARCH64_TLSDESC_ADD_LO12 sym
 
         add x0, x2, #:lo12:sym+8
 // CHECK: add x0, x2, :lo12:sym
 // CHECK-OBJ-LP64: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
 
    add x5, x7, #:dtprel_lo12:sym+1
 // CHECK: add x5, x7, :dtprel_lo12:sym+1
 // CHECK-OBJ-LP64: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
 
    add x9, x12, #:dtprel_lo12_nc:sym+2
 // CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
 // CHECK-OBJ-LP64:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
 
    add x20, x30, #:tprel_lo12:sym+12
 // CHECK: add x20, x30, :tprel_lo12:sym+12
 // CHECK-OBJ-LP64: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
 
    add x9, x12, #:tprel_lo12_nc:sym+54
 // CHECK: add x9, x12, :tprel_lo12_nc:sym+54
 // CHECK-OBJ-LP64: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
 
    add x5, x0, #:tlsdesc_lo12:sym+70
 // CHECK: add x5, x0, :tlsdesc_lo12:sym+70
-// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
+// CHECK-OBJ-LP64: 2c R_AARCH64_TLSDESC_ADD_LO12 sym+70
 
         .hword sym + 4 - .
 // CHECK-OBJ-LP64: 30 R_AARCH64_PREL16 sym+4
         .word sym - . + 8
 // CHECK-OBJ-LP64 32 R_AARCH64_PREL32 sym+8
         .xword sym-.
 // CHECK-OBJ-LP64 36 R_AARCH64_PREL64 sym{{$}}
 

 // CHECK: ldr d22, [x21, :gottprel_lo12:sym]
 // CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
 // CHECK-OBJ-LP64 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
 
    ldr x24, [x23, #:tlsdesc_lo12:sym]
    ldr d22, [x21, :tlsdesc_lo12:sym]
 // CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
 // CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
-// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
-// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12_NC sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12 sym
+// CHECK-OBJ-LP64 R_AARCH64_TLSDESC_LD64_LO12 sym
 
    ldr q20, [x19, #:lo12:sym]
 // CHECK: ldr q20, [x19, :lo12:sym]
 // CHECK-OBJ-LP64 R_AARCH64_LDST128_ABS_LO12_NC sym
 
 // Since relocated instructions print without a '#', that syntax should
 // certainly be accepted when assembling.
    add x3, x5, :lo12:imm
 // CHECK: add x3, x5, :lo12:imm

test/MC/AArch64/arm64-tls-relocs.s

 // CHECK: add     x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12
 // CHECK: .tlsdesccall var                // encoding: []
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call
 // CHECK: blr     x3                      // encoding: [0x60,0x00,0x3f,0xd6]
 
 
 // CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADR_PAGE21 [[VARSYM]]
-// CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
-// CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]]
+// CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_CALL [[VARSYM]]
 
         // Make sure symbol 5 has type STT_TLS:
 
 // CHECK-ELF:      Symbols [
 // CHECK-ELF:        Symbol {
 // CHECK-ELF:          Name: var
 // CHECK-ELF-NEXT:     Value:
 // CHECK-ELF-NEXT:     Size:
 // CHECK-ELF-NEXT:     Binding: Global
 // CHECK-ELF-NEXT:     Type: TLS

test/MC/AArch64/inline-asm-modifiers.s

// BB#0:
   add x0, x0, #:tprel_lo12:var_tlsle
   //NO_APP
   ret
 .Ltmp0:
   .size test_inline_modifier_L, .Ltmp0-test_inline_modifier_L
 
 // CHECK: R_AARCH64_ADD_ABS_LO12_NC var_simple
 // CHECK: R_AARCH64_LD64_GOT_LO12_NC var_got
-// CHECK: R_AARCH64_TLSDESC_ADD_LO12_NC var_tlsgd
+// CHECK: R_AARCH64_TLSDESC_ADD_LO12 var_tlsgd
 // CHECK: R_AARCH64_TLSLD_ADD_DTPREL_LO12 var_tlsld
 // CHECK: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var_tlsie
 // CHECK: R_AARCH64_TLSLE_ADD_TPREL_LO12 var_tlsle
 
   .globl  test_inline_modifier_G
   .type test_inline_modifier_G,@function
 test_inline_modifier_G:                 // @test_inline_modifier_G
 // BB#0:

test/MC/AArch64/tls-relocs.s

 // CHECK:                                    //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8
 // CHECK: add    x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
 // CHECK:                                  //   fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12
 // CHECK: .tlsdesccall var                // encoding: []
 // CHECK:                                 //   fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call
 // CHECK: blr    x3                      // encoding: [0x60,0x00,0x3f,0xd6]
 
 // CHECK-ELF-NEXT:     0x104 R_AARCH64_TLSDESC_ADR_PAGE21 [[VARSYM]]
-// CHECK-ELF-NEXT:     0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
-// CHECK-ELF-NEXT:     0x10C R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]]
+// CHECK-ELF-NEXT:     0x108 R_AARCH64_TLSDESC_LD64_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT:     0x10C R_AARCH64_TLSDESC_ADD_LO12 [[VARSYM]]
 // CHECK-ELF-NEXT:     0x110 R_AARCH64_TLSDESC_CALL [[VARSYM]]
 
 
 // Make sure symbol 5 has type STT_TLS:
 
 // CHECK-ELF:      Symbols [
 // CHECK-ELF:        Symbol {
 // CHECK-ELF:          Name: var
 // CHECK-ELF-NEXT:     Value:
 // CHECK-ELF-NEXT:     Size:
 // CHECK-ELF-NEXT:     Binding: Global
 // CHECK-ELF-NEXT:     Type: TLS

test/tools/llvm-readobj/reloc-types.test

 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC (555)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12 (556)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC (557)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12 (558)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC (559)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD_PREL19 (560)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PREL21 (561)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PAGE21 (562)
-ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12_NC (563)
-ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12_NC (564)
+ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12 (563)
+ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12 (564)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_OFF_G1 (565)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_OFF_G0_NC (566)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_LDR (567)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD (568)
 ELF-AARCH64: Type: R_AARCH64_TLSDESC_CALL (569)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST128_TPREL_LO12 (570)
 ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC (571)
 ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST128_DTPREL_LO12 (572)