Index: cmake/config-ix.cmake =================================================================== --- cmake/config-ix.cmake +++ cmake/config-ix.cmake @@ -173,7 +173,7 @@ set(ALL_CFI_SUPPORTED_ARCH ${X86} ${X86_64} ${MIPS64}) set(ALL_ESAN_SUPPORTED_ARCH ${X86_64} ${MIPS64}) set(ALL_SCUDO_SUPPORTED_ARCH ${X86} ${X86_64}) -set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64}) +set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64}) if(APPLE) include(CompilerRTDarwinUtils) Index: lib/xray/CMakeLists.txt =================================================================== --- lib/xray/CMakeLists.txt +++ lib/xray/CMakeLists.txt @@ -28,6 +28,26 @@ xray_trampoline_AArch64.S ${XRAY_SOURCES}) +set(mips_SOURCES + xray_mips.cc + xray_trampoline_mips.S + ${XRAY_SOURCES}) + +set(mipsel_SOURCES + xray_mips.cc + xray_trampoline_mips.S + ${XRAY_SOURCES}) + +set(mips64_SOURCES + xray_mips64.cc + xray_trampoline_mips64.S + ${XRAY_SOURCES}) + +set(mips64el_SOURCES + xray_mips64.cc + xray_trampoline_mips64.S + ${XRAY_SOURCES}) + include_directories(..) include_directories(../../include) Index: lib/xray/tests/CMakeLists.txt =================================================================== --- lib/xray/tests/CMakeLists.txt +++ lib/xray/tests/CMakeLists.txt @@ -41,7 +41,7 @@ list(APPEND TEST_DEPS gtest_main xray-fdr) endif() if(NOT APPLE) - add_compiler_rt_test(XRayUnitTests ${testname} + add_compiler_rt_test(XRayUnitTests ${testname}-${arch} OBJECTS ${TEST_OBJECTS} DEPS ${TEST_DEPS} LINK_FLAGS ${TARGET_LINK_FLAGS} Index: lib/xray/xray_inmemory_log.cc =================================================================== --- lib/xray/xray_inmemory_log.cc +++ lib/xray/xray_inmemory_log.cc @@ -27,7 +27,7 @@ #if defined(__x86_64__) #include -#elif defined(__arm__) || defined(__aarch64__) +#elif defined(__arm__) || defined(__aarch64__) || defined(__mips__) static const int64_t NanosecondsPerSecond = 1000LL * 1000 * 1000; #else #error "Unsupported CPU Architecture" @@ -195,7 +195,7 @@ } else { Report("Unable to determine CPU frequency for TSC accounting.\n"); } -#elif defined(__arm__) || defined(__aarch64__) +#elif defined(__arm__) || defined(__aarch64__) || defined(__mips__) // There is no instruction like RDTSCP in user mode on ARM. ARM's CP15 does // not have a constant frequency like TSC on x86(_64), it may go faster // or slower depending on CPU turbo or power saving mode. Furthermore, @@ -243,7 +243,7 @@ R.TSC = __rdtscp(&CPU); R.CPU = CPU; } -#elif defined(__arm__) || defined(__aarch64__) +#elif defined(__arm__) || defined(__aarch64__) || defined(__mips__) { timespec TS; int result = clock_gettime(CLOCK_REALTIME, &TS); Index: lib/xray/xray_interface.cc =================================================================== --- lib/xray/xray_interface.cc +++ lib/xray/xray_interface.cc @@ -35,6 +35,10 @@ static const int16_t cSledLength = 32; #elif defined(__arm__) static const int16_t cSledLength = 28; +#elif SANITIZER_MIPS32 +static const int16_t cSledLength = 40; +#elif SANITIZER_MIPS64 +static const int16_t cSledLength = 56; #else #error "Unsupported CPU Architecture" #endif /* CPU architecture */ Index: lib/xray/xray_mips.cc =================================================================== --- /dev/null +++ lib/xray/xray_mips.cc @@ -0,0 +1,136 @@ +//===-- xray_mips.cc --------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// Implementation of MIPS-specific routines (32-bit). +// +//===----------------------------------------------------------------------===// +#include "sanitizer_common/sanitizer_common.h" +#include "xray_defs.h" +#include "xray_interface_internal.h" +#include + +namespace __xray { + +// The machine codes for some instructions used in runtime patching. +enum class PatchOpcodes : uint32_t { + PO_CreateStackSpace = 0x27BDFFF8, // ADDIU SP, SP, -8 + PO_StoreRA = 0xAFBF0004, // SW RA, 4(SP) + PO_StoreT9 = 0xAFB90000, // SW T9, 0(SP) + PO_LoadUpperImmT9 = 0x3C190000, // LUI T9,
<< 16 + PO_ORI = 0x37390000, // ORI T9, T9,
| 0xffff + PO_JALR = 0x0320f809, // JALR T9 + PO_PassFuncId = 0x24080000, // ADDIU T0, ZERO, + PO_LoadT9 = 0x8FB90000, // SW T9, 0(SP) + PO_LoadRA = 0x8FBF0004, // LW RA, 4(SP) + PO_DeleteStackSpace = 0x27BD0008, // ADDIU SP, SP, 8 + PO_B36 = 0x10000009, // B #36 + PO_NOP = 0x0, // NOP +}; + +inline static bool patchSled(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled, + void (*TracingHook)()) XRAY_NEVER_INSTRUMENT { + // When |Enable| == true, + // We replace the following compile-time stub (sled): + // + // xray_sled_n: + // B .tmpN + // 9 NOPs (36 bytes) + // .tmpN + // ADDIU T9, T9, 44 + // + // With the following runtime patch: + // + // xray_sled_n (32-bit): + // addiu sp, sp, -8 ;create stack frame + // sw ra, 4(sp) ;save return address + // sw t9, 0(sp) ;save register t9 + // lui t9, + // ori t9, t9, + // jalr t9 ;call Tracing hook + // addiu t0 , zero, # ;pass function id (delay slot) + // lw t9, 0(sp) ;restore register t9 + // lw ra, 4(sp) ;restore return address + // addiu sp, sp, 8 ;delete stack frame + // + // We add 44 bytes to t9 because we want to adjust the function pointer to + // the actual start of function i.e. the address just after the noop sled. + // We do this because gp displacement relocation is emitted at the start of + // of the function i.e after the nop sled and to correctly calculate the + // global offset table address, t9 must hold the address of the instruction + // containing the gp displacement relocation. + // FIXME: Is this correct for the static relocation model? + // + // Replacement of the first 4-byte instruction should be the last and atomic + // operation, so that the user code which reaches the sled concurrently + // either jumps over the whole sled, or executes the whole sled when the + // latter is ready. + // + // When |Enable|==false, we set back the first instruction in the sled to be + // B #36 + + if (Enable) { + uint32_t LowerTracingHookAddr = + reinterpret_cast(TracingHook) & 0xffff; + uint32_t UpperTracingHookAddr = + reinterpret_cast(TracingHook) >> 16; + *reinterpret_cast(Sled.Address + 4) = + uint32_t(PatchOpcodes::PO_StoreRA); + *reinterpret_cast(Sled.Address + 8) = + uint32_t(PatchOpcodes::PO_StoreT9); + *reinterpret_cast(Sled.Address + 12) = + uint32_t(PatchOpcodes::PO_LoadUpperImmT9) | UpperTracingHookAddr; + *reinterpret_cast(Sled.Address + 16) = + uint32_t(PatchOpcodes::PO_ORI) | LowerTracingHookAddr; + *reinterpret_cast(Sled.Address + 20) = + uint32_t(PatchOpcodes::PO_JALR); + *reinterpret_cast(Sled.Address + 24) = + uint32_t(PatchOpcodes::PO_PassFuncId) | FuncId; + *reinterpret_cast(Sled.Address + 28) = + uint32_t(PatchOpcodes::PO_LoadT9); + *reinterpret_cast(Sled.Address + 32) = + uint32_t(PatchOpcodes::PO_LoadRA); + *reinterpret_cast(Sled.Address + 36) = + uint32_t(PatchOpcodes::PO_DeleteStackSpace); + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address), + uint32_t(PatchOpcodes::PO_CreateStackSpace), std::memory_order_release); + } else { + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address), + uint32_t(PatchOpcodes::PO_B36), std::memory_order_release); + + // Adding nop after branch for delay slot + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address + 4), + uint32_t(PatchOpcodes::PO_NOP), std::memory_order_release); + } + return true; +} + +bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + return patchSled(Enable, FuncId, Sled, __xray_FunctionEntry); +} + +bool patchFunctionExit(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); +} + +bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + // FIXME: In the future we'd need to distinguish between non-tail exits and + // tail exits for better information preservation. + return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); +} + +} // namespace __xray Index: lib/xray/xray_mips64.cc =================================================================== --- /dev/null +++ lib/xray/xray_mips64.cc @@ -0,0 +1,143 @@ +//===-- xray_mips64.cc ------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// Implementation of MIPS64-specific routines. +// +//===----------------------------------------------------------------------===// +#include "sanitizer_common/sanitizer_common.h" +#include "xray_defs.h" +#include "xray_interface_internal.h" +#include + +namespace __xray { + +// The machine codes for some instructions used in runtime patching. +enum class PatchOpcodes : uint32_t { + PO_CreateStackSpace = 0x67BDFFF0, // DADDIU SP, SP, -16 + PO_StoreRA = 0xFFBF0008, // SD RA, 8(SP) + PO_StoreT9 = 0xFFB90000, // SD T9, 0(SP) + PO_LoadUpperImmT9 = 0x3C190000, // LUI T9,
<< 16 + PO_ORI = 0x37390000, // ORI T9, T9,
| 0xffff + PO_DSLL16 = 0x0019CC38, // DSLL T9, T9, 16 + PO_JALR = 0x0320f809, // JALR T9 + PO_PassFuncId = 0x24080000, // ADDIU T0, ZERO, + PO_LoadT9 = 0xDFB90000, // LD T9, 0(SP) + PO_LoadRA = 0xDFBF0008, // LD RA, 8(SP) + PO_DeleteStackSpace = 0x67BD0010, // DADDIU SP, SP, 16 + PO_B52 = 0x1000000d, // B #52 + PO_NOP = 0x0, // NOP +}; + +inline static bool patchSled(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled, + void (*TracingHook)()) XRAY_NEVER_INSTRUMENT { + // When |Enable| == true, + // We replace the following compile-time stub (sled): + // + // xray_sled_n: + // B .tmpN + // 13 NOPs (52 bytes) + // .tmpN + // + // With the following runtime patch: + // + // xray_sled_n (64-bit): + // addiu sp, sp, -8 ;create stack frame + // sw ra, 4(sp) ;save return address + // sw t9, 0(sp) ;save register t9 + // lui t9, %highest(__xray_FunctionEntry/Exit) + // ori t9, t9, %higher(__xray_FunctionEntry/Exit) + // dsll t9, t9, 16 + // ori t9, t9, %hi(__xray_FunctionEntry/Exit) + // dsll t9, t9, 16 + // ori t9, t9, %lo(__xray_FunctionEntry/Exit) + // jalr t9 ;call Tracing hook + // addiu t0 , zero, # ;pass function id (delay slot) + // lw t9, 0(sp) ;restore register t9 + // lw ra, 4(sp) ;restore return address + // addiu sp, sp, 8 ;delete stack frame + // + // Replacement of the first 4-byte instruction should be the last and atomic + // operation, so that the user code which reaches the sled concurrently + // either jumps over the whole sled, or executes the whole sled when the + // latter is ready. + // + // When |Enable|==false, we set back the first instruction in the sled to be + // B #52 + + if (Enable) { + uint32_t LoTracingHookAddr = + reinterpret_cast(TracingHook) & 0xffff; + uint32_t HiTracingHookAddr = + (reinterpret_cast(TracingHook) >> 16); + uint32_t HigherTracingHookAddr = + (reinterpret_cast(TracingHook) >> 32); + uint32_t HighestTracingHookAddr = + (reinterpret_cast(TracingHook) >> 48); + *reinterpret_cast(Sled.Address + 4) = + uint32_t(PatchOpcodes::PO_StoreRA); + *reinterpret_cast(Sled.Address + 8) = + uint32_t(PatchOpcodes::PO_StoreT9); + *reinterpret_cast(Sled.Address + 12) = + uint32_t(PatchOpcodes::PO_LoadUpperImmT9) | HighestTracingHookAddr; + *reinterpret_cast(Sled.Address + 16) = + uint32_t(PatchOpcodes::PO_ORI) | HigherTracingHookAddr; + *reinterpret_cast(Sled.Address + 20) = + uint32_t(PatchOpcodes::PO_DSLL16); + *reinterpret_cast(Sled.Address + 24) = + uint32_t(PatchOpcodes::PO_ORI) | HiTracingHookAddr; + *reinterpret_cast(Sled.Address + 28) = + uint32_t(PatchOpcodes::PO_DSLL16); + *reinterpret_cast(Sled.Address + 32) = + uint32_t(PatchOpcodes::PO_ORI) | LoTracingHookAddr; + *reinterpret_cast(Sled.Address + 36) = + uint32_t(PatchOpcodes::PO_JALR); + *reinterpret_cast(Sled.Address + 40) = + uint32_t(PatchOpcodes::PO_PassFuncId) | FuncId; + *reinterpret_cast(Sled.Address + 44) = + uint32_t(PatchOpcodes::PO_LoadT9); + *reinterpret_cast(Sled.Address + 48) = + uint32_t(PatchOpcodes::PO_LoadRA); + *reinterpret_cast(Sled.Address + 52) = + uint32_t(PatchOpcodes::PO_DeleteStackSpace); + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address), + uint32_t(PatchOpcodes::PO_CreateStackSpace), std::memory_order_release); + } else { + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address), + uint32_t(PatchOpcodes::PO_B52), std::memory_order_release); + // Adding nop after branch for delay slot + std::atomic_store_explicit( + reinterpret_cast *>(Sled.Address + 8), + uint32_t(PatchOpcodes::PO_NOP), std::memory_order_release); + } + return true; +} + +bool patchFunctionEntry(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + return patchSled(Enable, FuncId, Sled, __xray_FunctionEntry); +} + +bool patchFunctionExit(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); +} + +bool patchFunctionTailExit(const bool Enable, const uint32_t FuncId, + const XRaySledEntry &Sled) XRAY_NEVER_INSTRUMENT { + // FIXME: In the future we'd need to distinguish between non-tail exits and + // tail exits for better information preservation. + return patchSled(Enable, FuncId, Sled, __xray_FunctionExit); +} + +} // namespace __xray Index: lib/xray/xray_trampoline_mips.S =================================================================== --- /dev/null +++ lib/xray/xray_trampoline_mips.S @@ -0,0 +1,115 @@ +//===-- xray_trampoline_mips.s ----------------------------------*- ASM -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the MIPS-specific assembler for the trampolines. +// +//===----------------------------------------------------------------------===// + + .text + .file "xray_trampoline_mips.S" + .globl __xray_FunctionEntry + .p2align 2 + .type __xray_FunctionEntry,@function +__xray_FunctionEntry: + .cfi_startproc + .cpload $t9 + // Save caller provided registers before doing any actual work. + .cfi_def_cfa_offset 40 + addiu $sp, $sp, -40 + sw $a0, 0($sp) + sw $a1, 4($sp) + sw $a2, 8($sp) + sw $a3, 12($sp) + swc1 $f12, 16($sp) + swc1 $f13, 20($sp) + swc1 $f14, 24($sp) + swc1 $f15, 28($sp) + sw $ra, 32($sp) + sw $gp, 36($sp) + + la $t9, _ZN6__xray19XRayPatchedFunctionE + lw $t9, 0($t9) + + beqz $t9, FunctionExit_restore + + // a1=0 means that we are tracing an entry event + addiu $a1, $zero, 0 + // Function ID is in t0 (the first parameter). + addu $a0, $zero, $t0 + jalr $t9 + +FunctionEntry_restore: + // Restore caller provided registers + lw $gp, 36($sp) + lw $ra, 32($sp) + lwc1 $f15, 28($sp) + lwc1 $f14, 24($sp) + lwc1 $f13, 20($sp) + lwc1 $f12, 16($sp) + lw $a3, 12($sp) + lw $a2, 8($sp) + lw $a1, 4($sp) + lw $a0, 0($sp) + addiu $sp, $sp, 40 + jr $ra +FunctionEntry_end: + .size __xray_FunctionEntry, FunctionEntry_end-__xray_FunctionEntry + .cfi_endproc + + .text + .globl __xray_FunctionExit + .p2align 2 + .type __xray_FunctionExit,@function +__xray_FunctionExit: + .cfi_startproc + .cpload $t9 + // Save caller provided registers before doing any actual work. + .cfi_def_cfa_offset 40 + addiu $sp, $sp, -40 + sw $a0, 0($sp) + sw $a1, 4($sp) + sw $a2, 8($sp) + sw $a3, 12($sp) + swc1 $f12, 16($sp) + swc1 $f13, 20($sp) + swc1 $f14, 24($sp) + swc1 $f15, 28($sp) + sw $ra, 32($sp) + sw $gp, 36($sp) + la $t9, _ZN6__xray19XRayPatchedFunctionE + lw $t9, 0($t9) + + beqz $t9, FunctionExit_restore + + // a1=1 means that we are tracing an exit event + addiu $a1, $zero, 1 + // Function ID is in t0 (the first parameter). + addu $a0, $zero, $t0 + jalr $t9 + +FunctionExit_restore: + // Restore caller provided registers + lw $gp, 36($sp) + lw $ra, 32($sp) + lwc1 $f15, 28($sp) + lwc1 $f14, 24($sp) + lwc1 $f13, 20($sp) + lwc1 $f12, 16($sp) + lw $a3, 12($sp) + lw $a2, 8($sp) + lw $a1, 4($sp) + lw $a0, 0($sp) + addiu $sp, $sp, 40 + jr $ra + +FunctionExit_end: + .size __xray_FunctionExit, FunctionExit_end-__xray_FunctionExit + .cfi_endproc Index: lib/xray/xray_trampoline_mips64.S =================================================================== --- /dev/null +++ lib/xray/xray_trampoline_mips64.S @@ -0,0 +1,115 @@ +//===-- xray_trampoline_mips64.s --------------------------------*- ASM -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is a part of XRay, a dynamic runtime instrumentation system. +// +// This implements the MIPS64-specific assembler for the trampolines. +// +//===----------------------------------------------------------------------===// + + .text + .file "xray_trampoline_mips64.S" + .globl __xray_FunctionEntry + .p2align 2 + .type __xray_FunctionEntry,@function +__xray_FunctionEntry: + .cfi_startproc + .cpload $t9 + // Save caller provided registers before doing any actual work. + .cfi_def_cfa_offset 80 + daddiu $sp, $sp, -80 + sd $a0, 0($sp) + sd $a1, 8($sp) + sd $a2, 16($sp) + sd $a3, 24($sp) + sdc1 $f12, 32($sp) + sdc1 $f13, 40($sp) + sdc1 $f14, 48($sp) + sdc1 $f15, 56($sp) + sd $ra, 64($sp) + sd $gp, 72($sp) + + dla $t9, _ZN6__xray19XRayPatchedFunctionE + ld $t9, 0($t9) + + beqz $t9, FunctionExit_restore + + // a1=0 means that we are tracing an entry event + addiu $a1, $zero, 0 + // Function ID is in t0 (the first parameter). + addu $a0, $zero, $t0 + jalr $t9 + +FunctionEntry_restore: + // Restore caller provided registers + ld $gp, 72($sp) + ld $ra, 64($sp) + ldc1 $f15, 56($sp) + ldc1 $f14, 48($sp) + ldc1 $f13, 40($sp) + ldc1 $f12, 32($sp) + ld $a3, 24($sp) + ld $a2, 16($sp) + ld $a1, 8($sp) + ld $a0, 0($sp) + daddiu $sp, $sp, 80 + jr $ra +FunctionEntry_end: + .size __xray_FunctionEntry, FunctionEntry_end-__xray_FunctionEntry + .cfi_endproc + + .text + .globl __xray_FunctionExit + .p2align 2 + .type __xray_FunctionExit,@function +__xray_FunctionExit: + .cfi_startproc + .cpload $t9 + // Save caller provided registers before doing any actual work. + .cfi_def_cfa_offset 80 + daddiu $sp, $sp, -80 + sd $a0, 0($sp) + sd $a1, 8($sp) + sd $a2, 16($sp) + sd $a3, 24($sp) + sdc1 $f12, 32($sp) + sdc1 $f13, 40($sp) + sdc1 $f14, 48($sp) + sdc1 $f15, 56($sp) + sd $ra, 64($sp) + sd $gp, 72($sp) + dla $t9, _ZN6__xray19XRayPatchedFunctionE + ld $t9, 0($t9) + + beqz $t9, FunctionExit_restore + + // a1=1 means that we are tracing an exit event + addiu $a1, $zero, 1 + // Function ID is in t0 (the first parameter). + addu $a0, $zero, $t0 + jalr $t9 + +FunctionExit_restore: + // Restore caller provided registers + ld $gp, 72($sp) + ld $ra, 64($sp) + ldc1 $f15, 56($sp) + ldc1 $f14, 48($sp) + ldc1 $f13, 40($sp) + ldc1 $f12, 32($sp) + ld $a3, 24($sp) + ld $a2, 16($sp) + ld $a1, 8($sp) + ld $a0, 0($sp) + daddiu $sp, $sp, 80 + jr $ra + +FunctionExit_end: + .size __xray_FunctionExit, FunctionExit_end-__xray_FunctionExit + .cfi_endproc Index: test/xray/TestCases/Linux/pic_test.cc =================================================================== --- /dev/null +++ test/xray/TestCases/Linux/pic_test.cc @@ -0,0 +1,33 @@ +// Test to check if we handle pic code properly. + +// RUN: %clangxx_xray -fxray-instrument -std=c++11 -fpic %s -o %t +// RUN: XRAY_OPTIONS="verbosity=1 xray_logfile_base=pic-test-logging-" %run %t 2>&1 | FileCheck %s +// After all that, clean up the output xray log. +// +// RUN: rm pic-test-logging-* + +#include + +[[clang::xray_always_instrument]] +unsigned short foo (unsigned b); + +[[clang::xray_always_instrument]] +unsigned short bar (unsigned short a) +{ + printf("bar() is always instrumented!\n"); + return foo(a); +} + +unsigned short foo (unsigned b) +{ + printf("foo() is always instrumented!\n"); + return b + b + 5; +} + +int main () +{ + // CHECK: XRay: Log file in 'pic-test-logging-{{.*}}' + bar(10); + // CHECK: bar() is always instrumented! + // CHECK-NEXT: foo() is always instrumented! +}