[ARM] Better error message for invalid flag-preserving Thumb1 insts

[olista01]

Summary

When we see a non flag-setting instruction for which only the flag-setting version is available in Thumb1, we should give a better error message than "invalid instruction".

[rengolin]

LGTM. Thanks!

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 
 public:
   enum ARMMatchResultTy {
     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
     Match_RequiresNotITBlock,
     Match_RequiresV6,
     Match_RequiresThumb2,
     Match_RequiresV8,
+    Match_RequiresFlagSetting,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "ARMGenAsmMatcher.inc"
 
   };
 
   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
                const MCInstrInfo &MII, const MCTargetOptions &Options)
     : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
     // Find the optional-def operand (cc_out).
     unsigned OpNo;
     for (OpNo = 0;
          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
          ++OpNo)
       ;
     // If we're parsing Thumb1, reject it completely.
     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
-      return Match_MnemonicFail;
+      return Match_RequiresFlagSetting;
     // If we're parsing Thumb2, which form is legal depends on whether we're
     // in an IT block.
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
         !inITBlock())
       return Match_RequiresITBlock;
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
         inITBlock())
       return Match_RequiresNotITBlock;
bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_RequiresITBlock:
     return Error(IDLoc, "instruction only valid inside IT block");
   case Match_RequiresV6:
     return Error(IDLoc, "instruction variant requires ARMv6 or later");
   case Match_RequiresThumb2:
     return Error(IDLoc, "instruction variant requires Thumb2");
   case Match_RequiresV8:
     return Error(IDLoc, "instruction variant requires ARMv8 or later");
+  case Match_RequiresFlagSetting:
+    return Error(IDLoc, "no flag-preserving variant of this instruction available");
   case Match_ImmRange0_15: {
     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
   }
   case Match_ImmRange0_239: {
     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;

llvm/trunk/test/MC/ARM/thumb-diagnostics.s

 @ RUN: not llvm-mc -triple=thumbv6-apple-darwin -o /dev/null < %s 2>&1 \
 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS %s
 @ RUN: not llvm-mc -triple=thumbv5-apple-darwin -o /dev/null < %s 2>&1 \
 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V5 %s
 @ RUN: not llvm-mc -triple=thumbv7m -o /dev/null < %s 2>&1 \
 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V7M %s
 @ RUN: not llvm-mc -triple=thumbv8 -o /dev/null < %s 2>&1 \
 @ RUN:     | FileCheck --check-prefix=CHECK-ERRORS-V8 %s
 
 @ Check for various assembly diagnostic messages on invalid input.
 
 @ ADD instruction w/o 'S' suffix.
         add r1, r2, r3
-@ CHECK-ERRORS: error: invalid instruction
+@ CHECK-ERRORS: error: no flag-preserving variant of this instruction available
 @ CHECK-ERRORS:         add r1, r2, r3
 @ CHECK-ERRORS:         ^
 
 @ Instructions which require v6+ for both registers to be low regs.
         add r2, r3
         mov r2, r3
 @ CHECK-ERRORS: error: instruction variant requires Thumb2
 @ CHECK-ERRORS:         add r2, r3