[AArch64] Introduce features that will allow only assembler support for neon, crypto, fp-armv8 and fullfp16.

[sbaranga]

Summary

The purpose of these features is to allow us to change the
behaviour of the -mgeneral-regs-only option to match
the gcc behavior (restrict code generation but not add
constraints for the assembler).

Fixes https://llvm.org/bugs/show_bug.cgi?id=30792

[t.p.northover]

This option seems like a near duplicate for -mno-implicit-float in the backend, which already works in this configuration. It differs over what happens if explicit floats are used, but we seem to produce thoroughly unsupported soft-float code at the moment, so that probably doesn't matter.

So I'd suggest changing how Clang treats -mgeneral-regs-only to match -mno-implicit-float. Then maybe deciding what that should do if someone actually uses floats.

Tim. (Also commented on bug along similar lines).

[sbaranga]

Thanks, that makes sense. I also wasn't aware of no-implicit-float.

If gcc rejects floating point uses we should probably do the same, but it's not exactly clear to me what the rules are for rejecting these uses.
For example it seems that declaring a global float is ok, and it is also fine to write "int a(float t);", so I think we need to only reject the uses inside a function body?

What about explicit uses of vector types? Would that be solved because the user wouldn't be able to include arm_neon.h?

-Silviu

[t.p.northover]

If gcc rejects floating point uses we should probably do the same

Possibly, the error message rather suggests that's not the desired behaviour though:

tmp.c:2:7: sorry, unimplemented: ‘-mgeneral-regs-only’ and floating point code

It's not even got "error:". Might be worth having a chat with Marcus or Richard on the GCC side to see if they have some long-term behaviour in mind.

What about explicit uses of vector types? Would that be solved because the user wouldn't be able to include arm_neon.h?

I think we support the vector attributes independently of arm_neon.h so they should probably be disallowed too.

[sbaranga]

It looks like gcc should have been emitting an error here instead of the "sorry, not implemented".

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
   SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy(DL));
   Chain = DAG.getStore(Chain, Location, OpInfo.CallOperand, StackSlot,
                        MachinePointerInfo::getFixedStack(MF, SSFI));
   OpInfo.CallOperand = StackSlot;
 
   return Chain;
 }
 
+static MVT getFirstLegalVT(const TargetRegisterClass *RC,
+                            const TargetLowering &TLI) {
+  for (auto *I = RC->vt_begin(); I != RC->vt_end(); ++I) {
+    auto RegVT = *I;
+    if (TLI.isTypeLegal(RegVT))
+      return RegVT;
+  }
+
+  return MVT::Other;
+}
+
 /// GetRegistersForValue - Assign registers (virtual or physical) for the
 /// specified operand.  We prefer to assign virtual registers, to allow the
 /// register allocator to handle the assignment process.  However, if the asm
 /// uses features that we can't model on machineinstrs, we have SDISel do the
 /// allocation.  This produces generally horrible, but correct, code.
 ///
 ///   OpInfo describes the operand.
 ///
static void GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI,
   MVT RegVT;
   EVT ValueVT = OpInfo.ConstraintVT;
 
   // If this is a constraint for a specific physical register, like {r17},
   // assign it now.
   if (unsigned AssignedReg = PhysReg.first) {
     const TargetRegisterClass *RC = PhysReg.second;
     if (OpInfo.ConstraintVT == MVT::Other)
-      ValueVT = *RC->vt_begin();
+      ValueVT = getFirstLegalVT(RC, TLI);
 
     // Get the actual register value type.  This is important, because the user
     // may have asked for (e.g.) the AX register in i32 type.  We need to
     // remember that AX is actually i16 to get the right extension.
-    RegVT = *RC->vt_begin();
+    //
+    // There are edge cases where the register cannot hold a legal type but we
+    // still want to have the constraint (for example when using the
+    // -mgeneral-regs-only option). In these cases we will assign an MVT::Other
+    // type under the assumption that we don't need any extensions.
+    RegVT = getFirstLegalVT(RC, TLI);
 
     // This is a explicit reference to a physical register.
     Regs.push_back(AssignedReg);
 
     // If this is an expanded reference, add the rest of the regs to Regs.
     if (NumRegs != 1) {
       TargetRegisterClass::iterator I = RC->begin();
       for (; *I != AssignedReg; ++I)

lib/Target/AArch64/AArch64.td

def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
   "Enable ARMv8 PMUv3 Performance Monitors extension">;
 
 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
   "Full FP16", [FeatureFPARMv8]>;
 
 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
   "Enable Statistical Profiling extension">;
 
+def FeatureNEONAsm : SubtargetFeature<"neonasm", "HasNEONAsm", "true",
+  "Enable assembling Advanced SIMD instructions">;
+
+def FeatureCryptoAsm : SubtargetFeature<"cryptoasm", "HasCryptoAsm", "true",
+  "Enable assembling cryptographic instructions">;
+
+def FeatureFPARMv8Asm : SubtargetFeature<"fp-armv8asm", "HasFPARMv8Asm",
+  "true", "Enable assembling ARMv8 FP instructions">;
+
+def FeatureFullFP16Asm : SubtargetFeature<"fullfp16asm", "HasFullFP16Asm",
+  "true", "Enable assembling Full FP16 instructions", [FeatureFPARMv8Asm]>;
+
 /// Cyclone has register move instructions which are "free".
 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
                                         "Has zero-cycle register moves">;
 
 /// Cyclone has instructions which zero registers for "free".
 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
                                         "Has zero-cycle zeroing instructions">;
 

lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
   bool HasCRC = false;
   bool HasRAS = false;
   bool HasPerfMon = false;
   bool HasFullFP16 = false;
   bool HasSPE = false;
+  bool HasFPARMv8Asm = false;
+  bool HasNEONAsm = false;
+  bool HasCryptoAsm = false;
+  bool HasFullFP16Asm = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing = false;
 
   // StrictAlign - Disallow unaligned memory accesses.
public:
   bool isXRaySupported() const override { return true; }
 
   bool isX18Reserved() const { return ReserveX18; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON; }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
   bool hasRAS() const { return HasRAS; }
+  bool hasFPARMv8Asm() const { return HasFPARMv8Asm; }
+  bool hasNEONAsm() const { return HasNEONAsm; }
+  bool hasCryptoAsm() const { return HasCryptoAsm; }
   bool balanceFPOps() const { return BalanceFPOps; }
   bool predictableSelectIsExpensive() const {
     return PredictableSelectIsExpensive;
   }
   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
   bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }
   bool useAlternateSExtLoadCVTF32Pattern() const {
public:
   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
 
   /// CPU has TBI (top byte of addresses is ignored during HW address
   /// translation) and OS enables it.
   bool supportsAddressTopByteIgnored() const;
 
   bool hasPerfMon() const { return HasPerfMon; }
   bool hasFullFP16() const { return HasFullFP16; }
+  bool hasFullFP16Asm() const { return HasFullFP16Asm; }
   bool hasSPE() const { return HasSPE; }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
     : MCTargetAsmParser(Options, STI) {
     IsILP32 = Options.getABIName() == "ilp32";
     MCAsmParserExtension::Initialize(Parser);
     MCStreamer &S = getParser().getStreamer();
     if (S.getTargetStreamer() == nullptr)
       new AArch64TargetStreamer(S);
 
     // Initialize the set of available features.
-    setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
+    uint64_t FeatureMask = ComputeAvailableFeatures(getSTI().getFeatureBits());
+    bool HasNEONAsm = STI.getFeatureBits()[AArch64::FeatureNEONAsm];
+    bool HasCryptoAsm = STI.getFeatureBits()[AArch64::FeatureCryptoAsm];
+    bool HasFPARMv8Asm = STI.getFeatureBits()[AArch64::FeatureFPARMv8Asm];
+    bool HasFullFP16Asm = STI.getFeatureBits()[AArch64::FeatureFullFP16Asm];
+
+    // Check for features disabled by -mgeneral-regs-only and re-enable them
+    // in the assembler.
+    if (!HasNEONAsm && !HasCryptoAsm && !HasFPARMv8Asm && !HasFullFP16Asm) {
+      setAvailableFeatures(FeatureMask);
+      return;
+    }
+
+    // We need to enable some features.
+    MCSubtargetInfo &CSTI = copySTI();
+    if (HasNEONAsm)
+      CSTI.ToggleFeature(AArch64::FeatureNEON);
+    if (HasCryptoAsm)
+      CSTI.ToggleFeature(AArch64::FeatureCrypto);
+    if (HasFPARMv8Asm)
+      CSTI.ToggleFeature(AArch64::FeatureFPARMv8);
+    if (HasFullFP16Asm)
+      CSTI.ToggleFeature(AArch64::FeatureFullFP16);
+
+    FeatureMask = ComputeAvailableFeatures(CSTI.getFeatureBits());
+    setAvailableFeatures(FeatureMask);
   }
 
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseDirective(AsmToken DirectiveID) override;
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;

test/CodeGen/AArch64/inlineasm-general-regs-only.ll

+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-neon,-crypto,-fp-armv8,-fullfp16,+neonasm,+cryptoasm,+fp-armv8asm,+fullfp16asm %s -o - | FileCheck %s
+
+; CHECK-LABEL: fun
+; CHECK: ld2
+; CHECK: st2
+; CHECK aese
+; CHECK: dup
+; CHECK: umov
+; CHECK: fabd
+define i32 @fun(i8 *%addr0, i8 *%addr1, i32 %input) {
+entry:
+  ; We can assemble neon instructions
+  tail call void asm "ld2 {v0.16b, v1.16b}, $1 ; st2 {v0.16b, v1.16b}, $0", "=*Q,*Q,~{v0},~{v1}"(i8* %addr0, i8* %addr1)
+
+  ; We can assemble crypto instructions
+  tail call void asm "aese v0.16b, v1.16b;", "~{v0},~{v1}"()
+
+  ; We can move data form the simd register file.
+  %retval = tail call i32 asm "dup v1.4s, ${1:w} ; umov ${0:w}, v1.b[0];", "=r,r,~{v0},~{v1}"(i32 %input)
+
+  ; We can use fullfp16 instructions.
+  tail call void asm "fabd v0.4h, v1.4h, v2.4h;", "~{v0},~{v1},~{v2}"()
+
+  ret i32 %retval
+}